need a cheap student edition FPGA

Your code is not inferring a ROM. When all the values are 0, the
equations reduce to nothing.

Your best bet is to instantiate a coregan ROM.
 
Your code is not inferring a ROM. When all the values are 0, the
equations reduce to nothing.

Your best bet is to instantiate a coregan ROM.
 
Your code is not inferring a ROM. When all the values are 0, the
equations reduce to nothing.

Your best bet is to instantiate a coregan ROM.
 
Your code is not inferring a ROM. When all the values are 0, the
equations reduce to nothing.

Your best bet is to instantiate a coregan ROM.
 
Your code is not inferring a ROM. When all the values are 0, the
equations reduce to nothing.

Your best bet is to instantiate a coregan ROM.
 
Your code is not inferring a ROM. When all the values are 0, the
equations reduce to nothing.

Your best bet is to instantiate a coregan ROM.
 
Your code is not inferring a ROM. When all the values are 0, the
equations reduce to nothing.

Your best bet is to instantiate a coregan ROM.
 
Your code is not inferring a ROM. When all the values are 0, the
equations reduce to nothing.

Your best bet is to instantiate a coregan ROM.
 
Your code is not inferring a ROM. When all the values are 0, the
equations reduce to nothing.

Your best bet is to instantiate a coregan ROM.
 
I started this thread, because I found what appears to be a named-parameter
assignment to a UDP instance in the OpenSparc files.

This doesn't appear to be legal according to standard Verilog,
at least what I see in the 2001 standard.
I haven't gotten a clear response on this,
but I'm sure the community knows.

Can somebody with experience here say if this is supposed
to be legal, or if it is a manufacturer's extension
(and suggest which manufacterer?)

Thanks,

--
Ira Baxter, CTO
www.semanticdesigns.com

"Allan Herriman" <allanherriman@hotmail.com> wrote in message
news:hmke229g4ufv7h35htt4ohqhbikrvc26mo@4ax.com...
On Mon, 27 Mar 2006 01:12:41 GMT, mk <kal*@dspia.*comdelete> wrote:

On Sun, 26 Mar 2006 22:47:13 +1000, Allan Herriman
allanherriman@hotmail.com> wrote:

dff #4 park_reg(.din (next_pv),
.clk (clk),
.q (park_vec),
.se (se), .si(), .so());
...
dff isn't a gate primitive, so it must be a UDP. However, it seems
that the standard only allows ordered parameter assignments and not
named parameter assigments for UDPs.


Therefore the code isn't legal according to the standard.

This seems to be a mistake in the standard. Does anyone know why it
doesn't allow named parameter assignments for UDPs?

I must be missing something. Why is a named parameter assignment
needed ? Isn't this an ordered parameter assignment ?

In the above code,

(
.din(next_pv),
.clk(clk),
.q(park_vec),
.se(se),
.si(),
.so()
)

is a named parameter assignment.


An ordered parameter assignment would look more like

(
next_pv,
clk,
park_vec,
se
)


Regards,
Allan
Click to expand...
 
Ira Baxter wrote:
I started this thread, because I found what appears to be a named-parameter
assignment to a UDP instance in the OpenSparc files.

This doesn't appear to be legal according to standard Verilog,
at least what I see in the 2001 standard.
I haven't gotten a clear response on this,
but I'm sure the community knows.

Can somebody with experience here say if this is supposed
to be legal, or if it is a manufacturer's extension
(and suggest which manufacterer?)

Thanks,
Click to expand...
dff #4 park_reg(.din (next_pv),
.clk (clk)
.q (park_vec),
.se (se), .si(), .so());


Does the database contain a module description for dff
that has a parametized width ? If so this is simply instantiating
that module with a width of 4.

John Eaton
 
amitsheth@gmail.com wrote:
Hi All,
I am using Icarus Verilog compiler and GTKWave as a viewer.
My question is, can I pause a simulation in Icarus, take a .vcd dump
(till the paused point), view it in GTKWave and then continue the
simulation till another point, again pause it there and view the
results of the second part without loading a new dump altogether ?

I have tried to find out whether this is possible in GTKWave (using
whatever online help that's available), but couldn't get anywhere.

Any help on this would be really appreciated.

Thanks in advance,
Amit.
Click to expand...
Thank you all for your help. It was really appreciated.
-Amit.
 
amitsheth@gmail.com wrote:
Hi All,
I am using Icarus Verilog compiler and GTKWave as a viewer.
My question is, can I pause a simulation in Icarus, take a .vcd dump
(till the paused point), view it in GTKWave and then continue the
simulation till another point, again pause it there and view the
results of the second part without loading a new dump altogether ?

I have tried to find out whether this is possible in GTKWave (using
whatever online help that's available), but couldn't get anywhere.

Any help on this would be really appreciated.

Thanks in advance,
Amit.
Click to expand...
Thank you all for your help. It was really appreciated.
-Amit.
 
amitsheth@gmail.com wrote:
Hi All,
I am using Icarus Verilog compiler and GTKWave as a viewer.
My question is, can I pause a simulation in Icarus, take a .vcd dump
(till the paused point), view it in GTKWave and then continue the
simulation till another point, again pause it there and view the
results of the second part without loading a new dump altogether ?

I have tried to find out whether this is possible in GTKWave (using
whatever online help that's available), but couldn't get anywhere.

Any help on this would be really appreciated.

Thanks in advance,
Amit.
Click to expand...
Thank you all for your help. It was really appreciated.
-Amit.
 
amitsheth@gmail.com wrote:
Hi All,
I am using Icarus Verilog compiler and GTKWave as a viewer.
My question is, can I pause a simulation in Icarus, take a .vcd dump
(till the paused point), view it in GTKWave and then continue the
simulation till another point, again pause it there and view the
results of the second part without loading a new dump altogether ?

I have tried to find out whether this is possible in GTKWave (using
whatever online help that's available), but couldn't get anywhere.

Any help on this would be really appreciated.

Thanks in advance,
Amit.
Click to expand...
Thank you all for your help. It was really appreciated.
-Amit.
 
amitsheth@gmail.com wrote:
Hi All,
I am using Icarus Verilog compiler and GTKWave as a viewer.
My question is, can I pause a simulation in Icarus, take a .vcd dump
(till the paused point), view it in GTKWave and then continue the
simulation till another point, again pause it there and view the
results of the second part without loading a new dump altogether ?

I have tried to find out whether this is possible in GTKWave (using
whatever online help that's available), but couldn't get anywhere.

Any help on this would be really appreciated.

Thanks in advance,
Amit.
Click to expand...
Thank you all for your help. It was really appreciated.
-Amit.
 
The module you should specify for the "top module" is the verilog code
that starts wil "module" and ends with "endmodule" rather than the file
name. One file can contain many modules; SynplifyPro simply wants to
know which of these many modules across several files is top? Which
module specifies your pins?

srini wrote:
Hi,
When I am synthesizing using Synplify Pro, I am getting the following
errors:
1. Internal error in m_xilinx
2. No component with name top_module.v

Actually I have created a file called top_module.v and instantiated
other modules in that file. I have included this file name in Top level
module option in Implementation options. Is that wrong?
Click to expand...
 
Hi,
The top_module.v is my TOP module in which I am instantiating all the
other modules. This will be the module that specifies my pins. Do I
have to include some pin information in my TOP module?
 
"srini" <g.shrinivasan@gmail.com> wrote in message
news:1144817093.047840.185190@z34g2000cwc.googlegroups.com...
Hi,
The top_module.v is my TOP module in which I am instantiating all the
other modules. This will be the module that specifies my pins. Do I
have to include some pin information in my TOP module?
Click to expand...
There are modules and there are files.
top_module.v is a file.
In that file if you find:

module top_module ( input ...
full pin list
);
... // lots of code, some of which instantiates other modules

endmodule

then your top module is top_module, not the file top_module.v.

Synplify is NOT asking for the file that contains your top module.
 
It's located outside of US, that's all I can reveal.

Guenter wrote:
ngsayjoe@gmail.com wrote:
Try out LogicSim, it's free for the time being. I'm constantly making
frequent updates to improve the Quality of Result. It supports
WinXP-platform, Verilog text editor, VCD, SDF, Verilog-2001,
multi-files project, and many more. However, no PLI/VPI and Waveform
editor support at the moment. I will release v1.9 somewhere this month,
it is going to be a very stable release. Thanks.

Joe
LogicSim - Your Personal Verilog Simulator
http://www.logicsim.com

Joe, where is your Company located at?
Click to expand...
 
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