need a cheap student edition FPGA

Correct me if I'm wrong, but I think the above looping constructs are
synthesizable provided N and THE_BASE are constant.
 
Correct me if I'm wrong, but I think the above looping constructs are
synthesizable provided N and THE_BASE are constant.
 
Correct me if I'm wrong, but I think the above looping constructs are
synthesizable provided N and THE_BASE are constant.
 
Correct me if I'm wrong, but I think the above looping constructs are
synthesizable provided N and THE_BASE are constant.
 
Correct me if I'm wrong, but I think the above looping constructs are
synthesizable provided N and THE_BASE are constant.
 
Correct me if I'm wrong, but I think the above looping constructs are
synthesizable provided N and THE_BASE are constant.
 
Correct me if I'm wrong, but I think the above looping constructs are
synthesizable provided N and THE_BASE are constant.
 
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Stephen Williams wrote:
What you are looking for is a generate statement. I believe that
the Xilinx xst synthesizer supports it, and the latest snapshots
of Icarus Verilog have recently added support for generate loops.

You might want to try it out and maybe send a few bug reports
before sending me your eye-teeth. Also, cash may be more sanitary.
Click to expand...
Sorry Steve, no cigar (and I get to keep my eye-teeth, Ha). According
to:
http://www.synplicity.com/literature/pdf/Verilog_%202001.pdf

"Verilog 2001 has a new construct called generate that provides the
capability of creating MULTIPLE INSTANCES of the object within a
module"

This isn't what I want. I would like the compiler to generate a
simple two or three state FSM that loops over the same chunk of
verilog code rather than generating multiple copies of the code. Ah
well, maybe someday.

Ron


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Can you show us an example of what you would like to do using pseudo
code? Isn't a for loop in an always block synthesizable (under certain
restrictions)?

---
PDTi [ http://www.productive-eda.com ]
SpectaReg -- Spec-down code and doc generation for register maps
 
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Ron wrote:
Stephen Williams wrote:
What you are looking for is a generate statement. I believe that
the Xilinx xst synthesizer supports it, and the latest snapshots
of Icarus Verilog have recently added support for generate loops.

You might want to try it out and maybe send a few bug reports
before sending me your eye-teeth. Also, cash may be more sanitary.

Sorry Steve, no cigar (and I get to keep my eye-teeth, Ha). According
to:
http://www.synplicity.com/literature/pdf/Verilog_%202001.pdf

"Verilog 2001 has a new construct called generate that provides the
capability of creating MULTIPLE INSTANCES of the object within a
module"

This isn't what I want. I would like the compiler to generate a
simple two or three state FSM that loops over the same chunk of
verilog code rather than generating multiple copies of the code. Ah
well, maybe someday.
Click to expand...

I think we need a better idea what you are trying to do. There
are multiple places where you can loop, so if you can maybe draw
a little pseudo-code example, we can show you how to make it
work in real verilog.

- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
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Hi Guys,

I'm really sorry for almost forgetting about this thread. Please feel
free to email me personally in the future if you'd like.

Here is some simple bogus code that demonstrates a two state Finite
State Machine in Verilog that implements the equivalent of a "while
(a>b)" loop.

Ideally, the synthesizer's implementation of the FSM would be done
within the synthesizer itself rather than actually generating the
Verilog source code, so that the designer would see a "while()"
in his Verilog code rather than the actual FSM code implementation. On
the other hand, even a preprocessor macro might make things like this
less repetitive to code.

Ron



// The following Verilog code implements the "while"
// loop example on the next four lines,
// with a two state FSM in Verilog.
//
// while (a > b)
// b<= b+c;
// return (b-a);
//
module EXAMPLE_LOOP(reset,clock,a,b,c, finished,solution);
parameter N=32; // Bus Width
parameter S0=0,S1=1,S2=2,S3=3;
input reset, clock;
input [N-1:0] a,b,c;
output reg finished, solved;
output reg [N-1:0] solution;

reg state;

always @(posedge clock)
if (reset==1)
begin
finished<= 0;
state<=S0;
end
else
begin
case (state)
S0: begin
if (a > b) // while (a > b)
b<= b+c; // b<= b+c
else
state<= S1;
end
S1: begin
solution<= b-a; // return (b-a)
finished<= 1;
end
endcase
end
endmodule
 
So you're looking for some type of looping construct that works over
multiple clock cycles. Typically in RTL things are described one cycle
at a time with state-machines or counters to maintain state between
cycles (as you've shown). If you're looking for inferred hardware for
higher-level, multi-cycle operations I'd look into behavioural
synthesis.

The following code (if it works as I expect) should be work the same as
your example:

always @(posedge clock)
if (reset==1)
begin
finished<= 0;
solution<= 0;
end
else
begin
if (!finished && a > b) b <= b+c;
else
begin
finished <= 1;
solution <= b-a;
end
end
endmodule

This example is very sequential and could be implemented with a
generic/shared/timesliced ALU. Otherwise you'd have the logic just
sitting doing nothing after the solution is ready.

---
PDTi [ http://www.productive-eda.com ]
SpectaReg -- Spec-down code and doc generation for register maps
 
It's really as easy as it looks.

wire [11:0] aout;
a ( .a(aout) )
b ( .b(aout[3:0]) )
c ( .c(aout[11:4]) )
 
thanks .
I used to write A M_a(.a[11:0] (a[11:0]));

so foolish I am ....
 
If your simulator supports, try and use SystemVerilog bind for this -
that's exactly what you are looking for. If not, how about a simple
`include in your RTL and surround it with `ifdef SYNTHESIS etc.?

Ajeetha, CVC
www.noveldv.com
 
Nikhil,
I'm not EDA tool developer so am not sure of a common data model,
however Icarus Verilog has a synthesis engine and is open source. See
www.icarus.com/iverilog. GHDL is a GNU VHDL compiler/simulator, open
source. CVER is another popular open source Verilog simulator.

HTH
Ajeetha, CVC
www.noveldv.com
Nikhil Patil wrote:
Hi,

I am trying to write a tool that shall process synthesizable HDL. I
wish to do this in a way such that I can support both Verilog and VHDL
without too much extra effort. (I don't really care about the
simulation specific syntactic structures of the languages, the
synthesizable subset is good enough.)

Does anybody know of any good open-source parsers for verilog and vhdl
that produce a common dataflow tree, that I might use as my starting
point?

Thanks.
Nikhil
Click to expand...
 
"KJ" <kkjennings@sbcglobal.net> wrote in message
news:puThg.112234$dW3.88906@newssvr21.news.prodigy.com...
Unless this diagram though is taken as something to design to it becomes
obsolete and out of date real quickly though since it doesn't get
maintained.
Click to expand...
Under the assumption that the designer is a lazy weasel, yes you're right.
:) It's too often the case, but it ain't necessarily so.

If it IS something that will be designed to then it should be
part of the design specification.
Click to expand...
100% agreed.

For timing diagrams I have a neat web-based tool I wrote myself...
Yet another proprietary format!!! (Sorry, couldn't resist, even if you do
have a wonderful tool)
Click to expand...
Yet another format: yes, OK. Proprietary: no, I wouldn't have thought so.
Surely that would mean I kept it secret in some way?

Cheers,

-Ben-
 
"KJ" <kkjennings@sbcglobal.net> wrote in message
news:puThg.112234$dW3.88906@newssvr21.news.prodigy.com...
Unless this diagram though is taken as something to design to it becomes
obsolete and out of date real quickly though since it doesn't get
maintained.
Click to expand...
Under the assumption that the designer is a lazy weasel, yes you're right.
:) It's too often the case, but it ain't necessarily so.

If it IS something that will be designed to then it should be
part of the design specification.
Click to expand...
100% agreed.

For timing diagrams I have a neat web-based tool I wrote myself...
Yet another proprietary format!!! (Sorry, couldn't resist, even if you do
have a wonderful tool)
Click to expand...
Yet another format: yes, OK. Proprietary: no, I wouldn't have thought so.
Surely that would mean I kept it secret in some way?

Cheers,

-Ben-
 
"KJ" <kkjennings@sbcglobal.net> wrote in message
news:puThg.112234$dW3.88906@newssvr21.news.prodigy.com...
Unless this diagram though is taken as something to design to it becomes
obsolete and out of date real quickly though since it doesn't get
maintained.
Click to expand...
Under the assumption that the designer is a lazy weasel, yes you're right.
:) It's too often the case, but it ain't necessarily so.

If it IS something that will be designed to then it should be
part of the design specification.
Click to expand...
100% agreed.

For timing diagrams I have a neat web-based tool I wrote myself...
Yet another proprietary format!!! (Sorry, couldn't resist, even if you do
have a wonderful tool)
Click to expand...
Yet another format: yes, OK. Proprietary: no, I wouldn't have thought so.
Surely that would mean I kept it secret in some way?

Cheers,

-Ben-
 
Henry wrote:
Dear all,
I am trying to implement a complex number multiplier. However, when
I write down the code and simulate it in Modelsim, everything is ok.
However, when I used the same code to simualte it in VCS, some errors
occured and I captured the waveform and attached.

At the time of the vertical dotted line, ar=55d, ai=89d, br=127d,
bi=0. After a clock cycle, it will calculate ar*br, ar*bi, ai*br and ai*bi.

I expect the result should be:
ar*br=55*127 = 6985;
ar*bi=55*0 = 0;
ai*br=89*127=11303
ai*bi=89*0 = 0

However, from the simulation, the result is:
ar*br=6096;
ar*bi= 0;
ai*br=9779;
ai*bi=0

Here is my relevant source code:

always@ (posedge clk or posedge rst)
begin
if (rst != 1)
begin
arMulbr <= $signed(ar) * $signed(br);
aiMulbi <= $signed(ai) * $signed(bi);
arMulbi <= $signed(ar) * $signed(bi);
aiMulbr <= $signed(ai) * $signed(br);
yr <= $signed(arMulbr) - $signed(aiMulbi);
yi <= $signed(arMulbi) + $signed(aiMulbr);
end
else
begin
arMulbr <= 0;
aiMulbi <= 0;
arMulbi <= 0;
aiMulbr <= 0;
yr <= 0;
yi <= 0;
end

Anyone knows why this errors occured? (Notes that I used ModelSim
to simulate the above code and everything is ok). Thank you very much!!

Henry
Click to expand...

Where is the posedge clk in your simulation relative to the values of
ar, ai, and br changing? I have the feeling that the simulation is
scheduling the new ar, ai, and br values just *before* the clock. If
you look at your simulation, the *next* cycle's input values are what
you expect for the current cycle's output values. It's a good idea to
schedule your inputs so the transition somewhere outside the clock
transition area or run them off the same clock.

48*127=6096, 77*127=9779.
 
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