I
Ira Baxter
Guest
I found this in design/sys/iop/sparc/ifu/rtl/sparc_ifu_rndrob.v
....
assign next_pv[0] = pv[0] | reset;
dff #4 park_reg(.din (next_pv),
.clk (clk),
.q (park_vec),
.se (se), .si(), .so());
....
I don't see how the #4 is legal is Verilog 2001.
Can someone explain to me under what it means,
and under what circumstances this is legal?
Is this construct part of Verilog 2001, or is it vendor specific?
-- IDB
....
assign next_pv[0] = pv[0] | reset;
dff #4 park_reg(.din (next_pv),
.clk (clk),
.q (park_vec),
.se (se), .si(), .so());
....
I don't see how the #4 is legal is Verilog 2001.
Can someone explain to me under what it means,
and under what circumstances this is legal?
Is this construct part of Verilog 2001, or is it vendor specific?
-- IDB