need a cheap student edition FPGA

Hi,
Synplify Pro carries out synthesis even if dont specify ant top module.
Then what is the significance of this option? Also there is a "extract
parameters" button. When I press this button, I am not seeing
difference in my window. How to use these options?

Thanks & Regards,
Srini.
 
robquigley@gmail.com wrote:

Thing is tho, they trigger the
always blocks in the exact reverse order of what i think shud happen.
Click to expand...
If you want to preserve the order,
put all the $displays in one block.

-- Mike Treseler
 
Mike Treseler <mike_treseler@comcast.net> wrote:

If you want to preserve the order,
put all the $displays in one block.
Click to expand...
And replace the $displays with $strobe.

Steve
 
You guys should also look into Innoveda's Visual hdl (Now bought by
Mentor, I think). It translates State Machines, Flow Diagrams, FSM into
Verilog, vhdl and SystemC. All ready for synthesys.

Well, maybe. But I've felt for years that my chances of getting a
design to work are inversely proportional to the number of tools
between me and the target device.

Bob Perlman
Cambrian Design Works
Click to expand...
LOL. Just looking through older messages after joining this group. I
know this one is from 2003, but Bob's advice is always worth reviving.
I couldn't agree more.
 
Top module is the last file when no other possibility.
The option is used when mixed HDL are used.
T
 
* MikeShepherd564@btinternet.com <MikeShepherd564@btinternet.com> wrote:
You guys should also look into Innoveda's Visual hdl (Now bought by
Mentor, I think). It translates State Machines, Flow Diagrams, FSM into
Verilog, vhdl and SystemC. All ready for synthesys.

I believe such visual tools have been around for quite a long time now
Click to expand...
but am still not seeing any mass adoption. What is the problem with such
toolsets that prevent mass adoption?
Do the readers of this newsgroup use any automated code generators? If
yes which?

Regards
Jahagirdar Vijayvithal S
--
"Some part of a mistake is always correct." -- TARTAKOVER
 
Jahagirdar Vijayvithal S wrote:

I believe such visual tools have been around for quite a long time now
but am still not seeing any mass adoption. What is the problem with such
toolsets that prevent mass adoption?
Click to expand...
Such tools are perhaps useful to learn an HDL.
The problem is that they don't do the whole job.
To finish the job, I have to learn the language anyway,
and in that process I discover how ugly the generated
code really is.

Do the readers of this newsgroup use any automated code generators? If
yes which?
Click to expand...
I use a netlist generator also known as synthesis.
My visual tool is simulation.

-- Mike Treseler
 
On Fri, 28 Apr 2006 10:42:01 +0530, Jahagirdar Vijayvithal S
<jvs+060425@india.ti.com> wrote:

* MikeShepherd564@btinternet.com <MikeShepherd564@btinternet.com> wrote:
You guys should also look into Innoveda's Visual hdl (Now bought by
Mentor, I think). It translates State Machines, Flow Diagrams, FSM into
Verilog, vhdl and SystemC. All ready for synthesys.

I believe such visual tools have been around for quite a long time now
but am still not seeing any mass adoption. What is the problem with such
toolsets that prevent mass adoption?
Do the readers of this newsgroup use any automated code generators? If
yes which?

Regards
Jahagirdar Vijayvithal S
Click to expand...
You should reply to the original message. I did not write what you
quote. I wouldn't know "Innoveda's Visual hdl" if it hit me on the
head.

Mike
 
I think one of the reasons is short of communication between the
software engineers and the hardware/logic engineers. Trust is
important. Sometimes a hardware/logic engineer feels the tool generated
code is not good, and does not use that tool again. Why the both sides
can not talk together and decide what the generated code should be?
I also like software development although I do hardware/logic work in
the daytime. I have just finished a tool named TME, a table based edit
tool for HDL module's interface definition, to unify the process of HDL
coding and document writing. It is a free Verilog/VHDL framework
generation tool. It has not been listed on the website's index page
(quickly it will be). But you have already been able to download it
from http://www.topweaver.com/download/tme_1.zip
Screenshot: http://www.topweaver.com/doc/tme/images/overview.jpg
Demo Movie: http://www.topweaver.com/demo/TME_1.htm
Please let me know if you have any suggestion, whether about TME or
not.
Thank you.
T
 
Mike Treseler wrote:
Jahagirdar Vijayvithal S wrote:

I believe such visual tools have been around for quite a long time now
but am still not seeing any mass adoption. What is the problem with such
toolsets that prevent mass adoption?

Such tools are perhaps useful to learn an HDL.
On the other hand code generators are normally written by those who
Click to expand...
know the in's and out of the language and the design and find the
actual coding work to be monotonous.

The problem is that they don't do the whole job.
To finish the job, I have to learn the language anyway,
Click to expand...
I dont think code generators are an alternative to learning the
language. Generators are normally used to reduce the amount of time
spent on an 'already solved problem'. Such a technique can still be
helpful if it generates 50-90%+ of the required code leaving the rest
for the user to write. (For example a C programmer may use an GUI
builder tool which generated the required C code for the GUI and only
code the actions for the events.)
and in that process I discover how ugly the generated
code really is.


Do the readers of this newsgroup use any automated code generators? If
yes which?
The Original thread (back in 2003) was about using Excel to capture
Click to expand...
design information and using VB, Perl, Python,Lisp etc to generate the
equivalent verilog code. It might be helpful to use this technique
where ever code repeatability can be seen, and may save days of coding
followed by weeks of debugging.

Examples where automated code generators can be useful are
1> Back plane generator
2> Rule based integration
3> Pin mux generator
4> Others?

The original poster Martin Euredjian had an interesting question. "I've
been wondering if anyone has published useful worksheets/utilities in
order to facilitate the use of Excel in FPGA programming."

In cases where we are already using Excel or other tools to capture
design information in either tabular or graphical form, It would be
useful to create a repositery of template of such documents and any
scripts based on them.

Regards
H.H.I Tracy ,
hail! java is a major graveyard


I use a netlist generator also known as synthesis.
My visual tool is simulation.

-- Mike Treseler
Click to expand...
 
Jahagirdar Vijayvithal S <jvs+060425@india.ti.com> writes:

Do the readers of this newsgroup use any automated code generators?
Click to expand...
No, my experience is that it takes longer to draw the fsm diagrams
etc. than writing out the verilog code itself.

Petter

--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?
 
PDTi (http://www.productive-eda.com) provides SpectaReg, a tool that
generates code and docs for memory mapped registers (MMR). It captures
MMR specs then can generate:

* RTL implementation (verilog, vhdl)
* self checking testbench (SystemVerilog, VHDL, e, ...)
* C/C++ to abstract register/bitfield locations
* datasheet (HTML, DocBook, DITA, Framemaker, ...)
* System level C/C++ memory-map tests

This enables significant efficiency improvements, reducing errors and
allowing engineers to focus on the value added design. Perhaps the
most value comes from the tool's ability synchronize the various code
and documentation views with the golden spec. Certainly debugging a
datasheet or software driver that doesn't match the RTL can be
frustrating -- SpectaReg eliminates this.

Register maps become easy to maintain and you can add in all sorts of
debugging registers that you might otherwise have avoided due to the
tediousness of registers. SpectaReg also does formal checking on the
spec to identify errors and ambiguities before they are propagated to
the RTL.

If you haven't figured it already I work for PDTi and I'm big on code
generators. Please contact me if you would like to learn more.

Regards,
Jeremy Ralph
http://www.productive-eda.com
 
I
Jahagirdar Vijayvithal S wrote:

I believe such visual tools have been around for quite a long time now
but am still not seeing any mass adoption. What is the problem with such
toolsets that prevent mass adoption?
I believe representatives from the respective tool vendors would be the
Click to expand...
best people to comment on the usage pattern for their tools.
Do the readers of this newsgroup use any automated code generators? If
yes which?
Click to expand...
 
Jahagirdar Vijayvithal S wrote:
Do the readers of this newsgroup use any automated code generators? If
yes which?
Click to expand...
Personally I use the Icarus Verilog simulator and whatever synthesis
tool the FPGA vendor provides.

As an ex-programmer, what I would give my eye teeth for is a looping
contruct in synthesizable Verilog (while, for, etc). It seems to me that
generating a simple FSM when presented with a "while" statement
should be within the capabilities of a compiler, yet I've seen no
mention anywhere of extending Verilog to include such a feature.

Ron
 
* MikeShepherd564@btinternet.com <MikeShepherd564@btinternet.com> wrote:
You should reply to the original message. I did not write what you
quote. I wouldn't know "Innoveda's Visual hdl" if it hit me on the
head.

Mike
Click to expand...
Sorry that my post implied that the post on Innoveda's Visual HDL was
posted by you. I should have dug up the original post from Google groups
or atleast snipped the reference to your name.

Regards
Jahagirdar Vijayvithal S
--
My software never has bugs. It just develops random features.
Jahagirdar .V.S
 
* Ron <News5@spamex.com> wrote:
As an ex-programmer, what I would give my eye teeth for is a looping
contruct in synthesizable Verilog (while, for, etc). It seems to me that
generating a simple FSM when presented with a "while" statement
should be within the capabilities of a compiler, yet I've seen no
mention anywhere of extending Verilog to include such a feature.

Ron
what I miss is the VHDL style tick commands to access the MSB, LSB,
Click to expand...
range etc. values to do any sort of complicated calculations on
buswidths etc.

Regards
Jahagirdar Vijayvithal S
--
My software never has bugs. It just develops random features.
Jahagirdar .V.S 91-80-25099129(O) 91-80-28540394(R)
IC Design Engineer RGES-WLAN,
Texas Instruments (India) Ltd.
 
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Hash: SHA1

Ron wrote:
Jahagirdar Vijayvithal S wrote:
Do the readers of this newsgroup use any automated code generators? If
yes which?

Personally I use the Icarus Verilog simulator and whatever synthesis
tool the FPGA vendor provides.

As an ex-programmer, what I would give my eye teeth for is a looping
contruct in synthesizable Verilog (while, for, etc). It seems to me that
generating a simple FSM when presented with a "while" statement should
be within the capabilities of a compiler, yet I've seen no mention
anywhere of extending Verilog to include such a feature.
Click to expand...
What you are looking for is a generate statement. I believe that
the Xilinx xst synthesizer supports it, and the latest snapshots
of Icarus Verilog have recently added support for generate loops.

You might want to try it out and maybe send a few bug reports
before sending me your eye-teeth. Also, cash may be more sanitary.

:)

- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
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Correct me if I'm wrong, but I think the above looping constructs are
synthesizable provided N and THE_BASE are constant.
 
Correct me if I'm wrong, but I think the above looping constructs are
synthesizable provided N and THE_BASE are constant.
 
Correct me if I'm wrong, but I think the above looping constructs are
synthesizable provided N and THE_BASE are constant.
 
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