need a cheap student edition FPGA

So I did the following, but the output turns zero after the first reset
and doesn't change after that. I kind of sense it has something to do
with sum <= ans (where ans is assigned a + b + cin)
Click to expand...
Clue: How wide is ans? How wide should it be?

-Chris
 
Chris F Clark wrote:
So I did the following, but the output turns zero after the first reset
and doesn't change after that. I kind of sense it has something to do
with sum <= ans (where ans is assigned a + b + cin)

Clue: How wide is ans? How wide should it be?

-Chris
Click to expand...
Wow! I'm quite absentminded. But... let's just blame the simulator for
not complaining :)

It works now. I just had to make sure I didn't provide inputs faster
than the induced delay time. Otherwise, it would show the "latest"
addition (with the inputs closest to the final clock edge in
"pipeline") and make you think it performed the calculation in 1 cycle.
But that's just a case of providing input vectors properly and it has
nothing to do with the design.

And coming to design: so, is this the way you model a pipelined adder
for real?

Mahurshi Akilla
 
John McGrath wrote:
What's the betting that Antti is the first to get this going on an
FPGA?
Though I imagine it is huge when synthesized...
Click to expand...
Has anyone seen Sizes / and MHz for this, finally sitting in a FPGA ?
How does it compare with Leon ?

-jg

Pablo Bleyer Kocik wrote:

For those who are interested, SUN released Open SPARC today:

http://opensparc-t1.sunsource.net/download_hw.html
Click to expand...
 
Hihi,

I was thinking about that at the time of the first announcement (a few
months ago), but well I will sure look at it, and decide what todo
(if).

but funny you asked, I am considering adopting some micro for one
specific FPGA right now, but it would need to fit with SDRAM controller
into 3000LUTs and there must be uclinux support for it. its very tight
if doable using existing cores so I may end up re-writing something

Antti
 
A self-checking test bench is one that runs and prints "GOOD" or "BAD"
at the end. Or pass/fail, etc. This is a way better than having to
look at wave files to see if it worked or not.

For a DSP algorithm, one way to do it is to generate the "correct"
results in C, then have the bench compare them to the results of the
simulation. The C program can write the results to the file, and those
can be read by the test bench. Or the test bench can call the C
program directly.

(reply trimmed to one group)
 
Weng Tianxiang wrote:
Hi Pablo,
Thank you for your useful information.

Weng
Click to expand...
The problem is "System Requirements": "SPARC CPU based system"
 
Michael wrote:
Weng Tianxiang wrote:

Hi Pablo,
Thank you for your useful information.

Weng


The problem is "System Requirements": "SPARC CPU based system"
Click to expand...
Is that for the software development environment?. Seems like the
verilog rtl code should be pretty generic. From the description it
sounds more like a big compute farm engine rather than something
you would put in a fpga for an embedded system.



John Eaton
 
J o h n _ E a t o n (at) hp . com (no spaces) wrote:
Michael wrote:

Weng Tianxiang wrote:

Hi Pablo,
Thank you for your useful information.

Weng



The problem is "System Requirements": "SPARC CPU based system"


Is that for the software development environment?. Seems like the
verilog rtl code should be pretty generic. From the description it
sounds more like a big compute farm engine rather than something
you would put in a fpga for an embedded system.



John Eaton
Click to expand...
Why not? This would be a great teaching tool for fpga design and/or
computer system design courses at college level.

~jz
 
Jason Zheng wrote:
J o h n _ E a t o n (at) hp . com (no spaces) wrote:

Michael wrote:

Weng Tianxiang wrote:

Hi Pablo,
Thank you for your useful information.

Weng




The problem is "System Requirements": "SPARC CPU based system"


Is that for the software development environment?. Seems like the
verilog rtl code should be pretty generic. From the description it
sounds more like a big compute farm engine rather than something
you would put in a fpga for an embedded system.



John Eaton


Why not? This would be a great teaching tool for fpga design and/or
computer system design courses at college level.

~jz
Click to expand...

Only if it can fit into an FPGA. Anybody have a gatecount?

John Eaton
 
"Davy" <zhushenli@gmail.com> wrote in message
news:1143252117.350503.262470@i39g2000cwa.googlegroups.com...
Hi all,

Sometimes I have to write long DFF chain like below:

//------code--------------
...
reg [7:0] DFF0,DFF1,DFF2,...DFF50;

always@(posedge clk)
if(rst)
begin
DFF0 <= 0;
...
DFF50 <= 0;
end
else
begin
DFF0 <= INPUT;
...
DFF50 <= DFF49;
end

//------code end-----------
It's too long, is there any good compact style?
Click to expand...
Can't you declare it as :

reg [7:0] DFF[0:50];

and then use for loops with the loop counter declared as an integer? I
believe this is synthesizeable. Am I right?
 
You could make another verilog95 way:

reg [8*51-1:0] DFFs;
wire [7:0] DFF0,DFF1,DFF2,...DFF50;
assign {DFF50, DFF49, ..., DFF0} = DFFs;

always @(posedge clk) begin
if(rst) DFFs <= {51{8'h00}};
else begin
DFFs <= DFFs << 8;
DFFs[7:0] <= INPUT;
end
end

Of course you can omit assigning and use only required bits from vector
DFFs.
 
Task arguments are passed by value and hence is what you have
seen/observed. Your option will be to pass the clk as input to test_lib
module.

HTH
Ajeetha, CVC
www.noveldv.com
 
The source comes with scripts for Design Compiler. I guess they want
you to use that tool; which is for targetting ASICs.
 
Oh, and I don't have a gate count but the design is quite large:

[gliss@precision design]$ find ~/opensparc/design -name "*.v" -exec cat
{} \; | wc -l
323957

There are over 320,000 lines of Verilog and the support scripts are
built for a DC ASIC synthesis environment... good luck getting that to
fit in an FPGA.
 
Chris,

Brings up a question for the group: how many lines of verilog can you
fit in any given FPGA?

Anyone out there in the ASIC emulation world care to comment?

Being a 'hardware' type, I am just ignorant...

Austin

chrisbw@gmail.com wrote:

Oh, and I don't have a gate count but the design is quite large:

[gliss@precision design]$ find ~/opensparc/design -name "*.v" -exec cat
{} \; | wc -l
323957

There are over 320,000 lines of Verilog and the support scripts are
built for a DC ASIC synthesis environment... good luck getting that to
fit in an FPGA.
Click to expand...
 
Austin Lesea wrote:
Chris,

Brings up a question for the group: how many lines of verilog can you
fit in any given FPGA?
Click to expand...
It's a meaningless question without considering the exact nature of
the Verilog code.

For example, a complex control FSM described in several pages of
code may require less than 100 gates. On the other hand, a simple
(but wide) flip-flop intensive data path, described in a few lines,
may require 10000 gates or more.

As for the SPARC code, it seems like an extreme example. I wouldn't
call this RTL code. It's more like a manually generated technology-
independent netlist. For example, they don't even use flip-flop
inference. And they do have excessive hierarchy.

I suspect that it should be possible to gain at least an order
of magnitude in terms of lines of code by using a proper RTL
style. And the synthesis results might be better. (Excessive
hierarchy tends to yield suboptimal synthesis results).

Regards,

Jan

--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
From Python to silicon:
http://myhdl.jandecaluwe.com
 
Jan,

OK, that makes sense. I had thought the "law of large numbers" would
take over with enough code, but if this code is handcrafted for ASIC
cell applications (with extremely primitive cells), then it would
synthesize very poorly for anything but that application.

Austin

Jan Decaluwe wrote:

Austin Lesea wrote:

Chris,

Brings up a question for the group: how many lines of verilog can you
fit in any given FPGA?


It's a meaningless question without considering the exact nature of
the Verilog code.

For example, a complex control FSM described in several pages of
code may require less than 100 gates. On the other hand, a simple
(but wide) flip-flop intensive data path, described in a few lines,
may require 10000 gates or more.

As for the SPARC code, it seems like an extreme example. I wouldn't
call this RTL code. It's more like a manually generated technology-
independent netlist. For example, they don't even use flip-flop
inference. And they do have excessive hierarchy.

I suspect that it should be possible to gain at least an order
of magnitude in terms of lines of code by using a proper RTL
style. And the synthesis results might be better. (Excessive
hierarchy tends to yield suboptimal synthesis results).

Regards,

Jan
Click to expand...
 
Hi Ajeetha,

If I pass clk to test_lib, shall I use `include "test_lib.v"?

Best regards,
Davy
 
Davy,
That wouldn't change from the way you currently compile it. Say:

vcs test_lib.v test.v

Only the instantiation changes:

test_lib test_lib();
test_lib test_lib(.clk(clk));
Click to expand...

HTH
Ajeetha CVC
www.noveldv.com
 
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