need a cheap student edition FPGA

[Davy]

Hi,

Thank you for your help!

I just want to learn the simplest one-bit Sigma Delta DAC.

And I found a link interesting:
http://www.embedded.com/shared/printableArticle.jhtml?articleID=22101730

I have one more question:
If I want the one-bit Sigma Delta DAC have better performance, shall I
accelerate the integrator (move the frequency Fs to higher frequency)?

Best regards,
Davy

 

Hi,

If you want to understand more about internals of ADC/DAC with
differentiation of various methods
I will refer one book

It titles something like Designing Methods of ADC/DAC from an author
named Joshpher...

I am very sorry that I am not able to give correct name of both book
and author but what ever I knew I have told I had referred this book
some time back.

But for delta sigma type of conversion you have to limit the data width
also as you increase the data width for more resolution the noise will
cause problems.

Thanks,
Regards,
Kedar

 

In sci.electronics.basics Davy <zhushenli@gmail.com> wrote:
: Hi,

: Thank you for your help!

: I just want to learn the simplest one-bit Sigma Delta DAC.

: And I found a link interesting:
: http://www.embedded.com/shared/printableArticle.jhtml?articleID=22101730

: I have one more question:
: If I want the one-bit Sigma Delta DAC have better performance, shall I
: accelerate the integrator (move the frequency Fs to higher frequency)?

: Best regards,
: Davy

Yes, that is one way to achieve slightly higher performance.

Joe

 

[Randy Yates]

"Davy" <zhushenli@gmail.com> writes:

Hi,

Thank you for your help!

I just want to learn the simplest one-bit Sigma Delta DAC.

And I found a link interesting:
http://www.embedded.com/shared/printableArticle.jhtml?articleID=22101730

I have one more question:
If I want the one-bit Sigma Delta DAC have better performance, shall I
accelerate the integrator (move the frequency Fs to higher frequency)?

You can read the presentation I made at the comp.dsp conference on
delta sigma conversion here:

http://www.digitalsignallabs.com/presentation.pdf

See especially Figure 9 on page 18, which shows how SNR is related to
modulator order and oversampling ratio.
--
% Randy Yates % "...the answer lies within your soul
%% Fuquay-Varina, NC % 'cause no one knows which side
%%% 919-577-9882 % the coin will fall."
%%%% <yates@ieee.org> % 'Big Wheels', *Out of the Blue*, ELO
http://home.earthlink.net/~yatescr

 

[mk]

On 31 Jan 2006 16:03:35 -0800, "aman" <aman.bindra@gmail.com> wrote:

In verilog 2001 it is allowed to say always(*) and there is no need to
specify long sensitivity lists. Will the always block trigger on only
the signals which are read in that always block or will it trigger on
every input ?

The spec says: "The implicit event_expression, @*, is a
convenient shorthand that eliminates these problems by adding all nets
and variables which are read by the
statement (which can be a statement group) of a
procedural_timing_control_statement to the
event_expression."

HTH.

 

[Ajeetha]

Hi Davy,

CDN recently started CDNLive that tries similar thing as SNUG, but it
is too new to be compared to SNUG. Also see www.cdnuser.org - few weeks
old site.
HTH
Ajeetha, CVC
www.noveldv.com

 

[Vikas Mishra]

uday.das@gmail.com wrote:

Consider the code below ,

// code start
reg a;
initial a = 0;

always@(posedge clk)
begin
a = 1'b0;
a <= 1'b1;
end
// code end

What will be the waveform of a ? In my logic second assignment
overwrite first one , waveform of "a" should be 1 always. Am i right ?

What does the simulator say ?

Read the paper by Cliff Cummings on his website - " Nonblocking
Assignments in Verilog Synthesis, Coding Styles That Kill! " for a
detailed explanation to all sorts of blocking and nonblocking assignment
questions.

http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf

 

[Chris F Clark]

What will be the waveform of a ? In my logic second assignment
overwrite first one , waveform of "a" should be 1 always. Am i right ?

According to how I read the standard, there should be "glitches"
(spikes) where the value of a goes to 0 every clock edge and then goes
to 1. There is some time between the blocking and non-blocking
assignments, where the blocking assignment has taken place and the
update event for the non-blocking assign has not been executed yet.

However, there is no "digital" hardware that corresponds to that
behavior. Although there are certainly circuits that do glitch, There
are none that intentionally glitch. Glitches are violations of the
model, which says that the hardware makes well-defined transitions at
the clock edges. Thus, a synthesizer could (and "should") easily
discard that effect.

To me that code is just a recipe for pre-/post-synthesis simulation
mismatches. Either your pre-synthesis simulator ignores the parts of
the standard that require the glitch or the post-synthesis simulator
gives a different waveform from pre-synthesis due to their being no
glitch circuits in the design.

Is there some reason you want to write code like that? If not, don't.

And while I don't recommend it, you can get reliable behavior if both
assignment statements are non-blocking. In that case, the standard
requires the first one to be discarded, which seems to be the behavior
you want.

Hope this helps,
-Chris

*****************************************************************************
Chris Clark Internet : compres@world.std.com
Compiler Resources, Inc. Web Site : http://world.std.com/~compres
23 Bailey Rd voice : (508) 435-5016
Berlin, MA 01503 USA fax : (978) 838-0263 (24 hours)
------------------------------------------------------------------------------

 

Thanks... i have started it.

Ajeetha wrote:

Shantanu,
Read their document (cdsdoc command should get you started),
IIRC, ncelab -coverage is starting point.

Good Luck
Ajeetha, CVC

 

[gabor]

Chris F Clark wrote:

What will be the waveform of a ? In my logic second assignment
overwrite first one , waveform of "a" should be 1 always. Am i right ?

According to how I read the standard, there should be "glitches"
(spikes) where the value of a goes to 0 every clock edge and then goes
to 1. There is some time between the blocking and non-blocking
assignments, where the blocking assignment has taken place and the
update event for the non-blocking assign has not been executed yet.

In Modelsim, I've noticed these 0-width glitches even if both
statements
were non-blocking.

 

[Art Stamness]

If both are non-blocking, Then a 0-width glitch would be a requirement
of the LRM.

from IEEE-1364-2001 5.4.1 Determinisim :

initial begin
a <= 0 ;
a <= 1 ;
end

When this block is executed, there will be two events added to the
nonblocking assign update queue. The previous rule requires that they
be entered on the queue in source order; this rule requires that they
be taken from the queue and performned in source order as well. Hence,
at the end of time step1, the variable a will be assigned 0 and then 1.

--- End LRM Quote ----

I had to look it up myself just to be sure.

-Art

 

[Chris F Clark]

I stand corrected. Somewhere in Verilog there is the concept of an
assignment being dropped if later another assignment to the same
variable is scheduled. However, this apparently is not it. I won't
speculate further, as I don't have a copy of the standard readily
available, nor is such behavior a particularly good thing to be
relying on for the reasons I mentioned before.

The underlying problem is the Verilog was first a simulation language,
where it is important to be able to simulate glitches if that's what
the circuit does. However, it has been ursurped as a design language,
and for that purpose one doesn't want to be designing glitches in. And
under those circumstances, one doesn't want to be worrying about the
exact semantics of what a simulator will do with a particular
construct, (e.g. how blocking and non-blocking assigns interact to
create glitches), because one can't depend upon such glitches being
synthesizable, unless of course, you've got such code written by
someone else and you are looking for the lever to figure out how to
fix the code.

One can and should read the papers by Cliff Cummings on how to
reliably use blocking and non-blocking assignments and avoid the weird
corners of the language as much as one can.

Just one persons opinion,
-Chris

 

[Art Stamness]

You are probably thinking about "net delays" which can get cancelled (
descheduled ) in the event the new evaluated value is different than
the one currently scheduled on the net :

----- IEEE-1364-2001 Sect. 6.1.3 ----
wire #10 wireA ;
....
In situations where a right hand side operand changes before a previous
change has had time to propogate to the left hand side, the the
following steps are taken :
....
b) If this RHS value differs from the value currently scheduled to
left-hand side, then the currently scheduled propogation event is
descheduled.
....
------- end --------

This can be a real annoyance, or incredibly helpful in de-glitching
gate level simulations with # delays.

-Art

 

[Claude Sylvain]

I bought one, and I think that although there are some minor errors (like
most of books); it is a good book for Verilog beginner.

Claude.


"Mahurshi Akilla" <mahurshi@gmail.com> wrote in message
news:1141418227.426502.87240@z34g2000cwc.googlegroups.com...

Verilog HDL by Samir Palnitkar

do you guys think this is a good book for a beginner?

i am thinking of buying this but i wanted to know what you guys thought
about this before i end up spending $$$ on it.

the book's link is at:
http://www.amazon.com/gp/product/0130449113/sr=8-1/qid=1141417912/ref=sr_1_1/002-5064463-1842462?%5Fencoding=UTF8

 

[mel]

tnx michael!

i guess your right, the only around this problem
is through a soft link or PLIs.

 

[Petter Gustad]

"mel" <emmanuel.rigor@gmail.com> writes:

i guess your right, the only around this problem
is through a soft link or PLIs.

No, see my message with ID <87irqqftso.fsf@filestore.home.gustad.com>
in this thread. You can also use defparams with different relative
paths in your two testbenches. The advantages of this is that you can
move your entire simulation tree (very useful when you check out your
design from CVS etc.) to a different location/machine and run
without modifications.

Petter

--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

 

[Ron]

Mahurshi Akilla wrote:

i am trying to model a simple adder that takes 4 cycles to complete the
addition.

How about something like this?

module adder (a,b, sum);
input [7:0] a, b;
output [8:0] sum;
wire [8:0] sum;
assign sum = a + b;
endmodule

 

[Mahurshi Akilla]

Ron wrote:

Mahurshi Akilla wrote:

i am trying to model a simple adder that takes 4 cycles to complete the
addition.

How about something like this?


module adder (a,b, sum);
input [7:0] a, b;
output [8:0] sum;
wire [8:0] sum;
assign sum = a + b;
endmodule

In that case, how would you model the 4 cycle delay ?

Mahurshi Akilla

 

[Ron]

Mahurshi Akilla wrote:

In that case, how would you model the 4 cycle delay ?

Mahurshi Akilla


I would simply wait 4 cycles before sampling the output. ;-)

-- Ron

 

[Mahurshi Akilla]

Ron wrote:

Mahurshi Akilla wrote:

In that case, how would you model the 4 cycle delay ?

Mahurshi Akilla


I would simply wait 4 cycles before sampling the output. ;-)

-- Ron

Ahh... I think I know what you mean..

So I did the following, but the output turns zero after the first reset
and doesn't change after that. I kind of sense it has something to do
with sum <= ans (where ans is assigned a + b + cin)

Could someone tell me where I am wrong here ?


module add_pipeline(a, b, cin, clk, sum, reset);
input [7:0] a;
input [7:0] b;
input cin;
input clk;
input reset;
output [8:0] sum;
wire ans;

reg [8:0] sum;
reg [1:0] count;

assign ans = a + b + cin;

always @(posedge clk or posedge reset)
begin
if (reset == 1'b1)
begin
count <= 2'b00;
sum <= 8'b0000_0000;
end
else if (reset == 1'b0)
begin
count <= count + 1;
if (count == 2'b11)
begin
sum <= ans;
end

end

end

endmodule


Mahurshi Akilla