need a cheap student edition FPGA

[john jakson]

Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in message news:<9hv8c0l660vlsg9iukfv51fbhlr30cp26a@4ax.com>...

On 7 Jun 2004 07:21:48 -0700, johnjakson@yahoo.com (john jakson)
wrote:

"davidbarby" <danyangqu@suou.waseda.jp> wrote in message news:<6eb3db6ca7f5485d9d696440776471c6@localhost.talkaboutprogramming.com>...
Hi,

I am a new student majoring in LSI. Now I have to design a calculator
using verilog. It is the homework of a course.
I am looking for some reference code about it as I have very little
experience to program in Verilog. I would be very appreciated with your
help.
BTW, the functions I have to realize include Add, Subtract, Multiply,
Division, N!, C, Shift, MC, MS, MR, M+, M-.

Thank you...

Although you did not say real/floating point I would forget about
verilog real as that will lead you into endless complexity and
potentially dead end.

You did not not include dec pt key in your list, if its not there then
its all integer. If its implied (see spec/tutor), then you are still
dealing with integer but with an exponent for simple floating point.
As far as I know, pocket calculators don't do floating point by
converting the input to IEEE anyway. They do digit by digit
arithmetic. The dec pt is just a separate little state bit that tracks
where .. well you know how to do it on paper right.

Wish I had this sort of asignment in school too, but HDL didn't really
exist back then, only TTL.

We had a similar assignment, but we had to make it work in TTL.

Think in terms of FSMs. You can collect the key strokes into buffers
or regs. If the key is a digit, push down. If its an operator then do
that operator on whats in the buff. It up to you to make it work
though.

Why not do what real calculators do?

Design a small 4 or 8 bit microcontroller and code it in Verilog.

Write the calculator application in assembly language.

Regards,
Allan.

Naw, I think that might be just a little tough for the OP, but if you
were doing millions of em, it would certainly be the way.

Another way might be to use handelc and work at a more abstract way
with a C behavioural model. Either way would allow the architecture to
grow and support trigs etc.

regards

johnjakson_usa_com

 

[Tommy Thorn]

Chris F Clark wrote:

// what hardware will implement this?
always@(posedge clk)
begin
j <= max; // j looks like a flip-flop output
for (i = 0; i < max; i=i+1 )
begin
if (a == value) then j <= i; // a had better be aset of flip-flops
// and not a 1-port ram
end;
end;
....
If that is the hardware desired, one needs to write it out
explicitly, something like the following:

wire [3:0] max;
reg [3:0] a[14:0]; // flip flop array (hopefully!)
wire [3:0] value;
reg [15:0] max_decode; // internal signal
reg [15:0] comp; // internal signal
reg [3:0] enocode; // internal signal
reg [3:0] j; // flip-flop output

// decoder

always @(max)
case max of
0: max_decode = 16'b0000000000000000;
1: max_decode = 16'b0000000000000001;
2: max_decode = 16'b0000000000000011;
3: max_decode = 16'b0000000000000111;
4: max_decode = 16'b0000000000001111;
...
15: max_decode = 16'b1111111111111111;
endcase


// comparitors and associated logic

always@(value or a[0] or max_decode[0])
comp[0] = max_decode[0] && (value == a[0]);
always@(value or a[1] or max_decode[1])
comp[1] = max_decode[1] && (value == a[1]);
.....

What kind of advise is that? The straightforward (untested)

j = value == a[15] ? 15 :
value == a[14] ? 14 :
...
value == a[ 0] ? 0 :
16;

works, is far more readable, and leads to better logic if used with a
decent synthesizer (which immediately recoqnises this as a priority
encoder).

Tommy

 

[Manoj Vekaria]

Hi !
Tell him to use foloowing style instead.

`define CtoD #1.0

always @(posedge clk)
reg_var <= `CtoD expression;

Now for your simulations, you can redefine CtoD to be empty like this :
`define CtoD

So your simulations will work without this delay.

Apart from, this simulator you use may have some means to ignore
assignment delays like this.

-Manoj

Lawrence Nospam wrote:

I have a coworker who uses a very annoying style
of writing verilog. Unfortunately, he does this
for a reason, and I cannot think of a better way
to write it.

I hope someone can help me get rid of his style.

The bad style:

always @(posedge clk)
reg_var <= #CtoD expression;

The reason he does this is because he (sometimes)
mixes behaviorial code and gate-level code in
verification on a module-by-module basis.

The gate-level code has a clock tree which has
different non-zero delays to it's flops. The #CtoD
is needed so that the behaviorial output comes after
the latest gate-level flop captures. This avoids
hold-time problems which don't happen in real life.
Without this, a mixed gate/verilog system will FAIL.

Plus this lets him see something like gate delays
in simulating behaviorial code.


I want those delays (strewn throughout ALL of his
code) to go away. Can anyone help me out?


Is there any way to do something, like a spec-param
per file, or ANYTHING on a command line, module, or
file basis, so that he can satisfy his need for a
delay fom clock to data without cluttering the code?

(I want to stay with always blocks. I can't talk
him into instantiating a flop module with internal
delay.)

Thanks for any ideas.

Lawrence NoSpam

 

[Steven Sharp]

"Joy Chatterjee" <joy.chatterjee@intel.com> wrote in message news:<can70s$ous$1@news01.intel.com>...

I am new to verilog and saw that you had answered a question on a very
similar question I have. I have two bidi signals on my board. t_obs and
f_obs that are connected thru an active low quickswitch, obsiso. If obsiso
is low and they don't equal each other then t_obs and f_obs should be the
same.

It sounds like your quickswitch is supposed to be a bidirectional switch
(i.e. with drivers and inputs on both sides). It is not possible for a
user to write a correct model for a bidirectional switch themselves.
There is a built-in primitive, tranif0, that implements a bidirectional
switch with an active-low control. Because it is built in, it can be
treated specially by the simulator so that it works correctly.

 

[glen herrmannsfeldt]

Joy Chatterjee wrote:

I am new to verilog and saw that you had answered a question on a very
similar question I have. I have two bidi signals on my board. t_obs and
f_obs that are connected thru an active low quickswitch, obsiso. If obsiso
is low and they don't equal each other then t_obs and f_obs should be the
same. The problem I see with verilog is that they do not like a pin being
used like a reg and a wire. How do I get around this? Please look at my
example code.

(snip)

It might be that this is best done with verilog primitives.

Look at the tranif0 primitive, which sounds like what you want.

Also, look at tri and trireg net declarators. Maybe:

tranif0 gate1(t_obs,f_obs,obsiso);

tranif0 is a primitive, just like nand and nor, something
like a pass transistor or CMOS analog switch.

I don't know if there are higher level constructs which
will generate it, or not.

-- glen

 

[John_H]

Basically, you're not writing Verilog.
Very, very basic structures such as

if( condition ) begin [block of statements] end else begin [block of
statements] end

are necessary. I'd suggest learning a little more before trying to do a
conversion.
One suggestion for syntax related issues is to use a quick reference guide
such as that found at www.sutherland-hdl.com - check the "On-line Verilog
Ref" link toward the bottom of the list on the left.

Other statements like "assign" rather than
reg y; always@(x) case (x) 0: y=0; 1: y=1; default: y=0; endcase
you can use
wire y; assign y=x;
or even more simply if x is defined before wire y,
wire y = x;

Maybe a quick Verilog course is appropriate.


"Dave Wilson" <da_wils@hotmail.com> wrote in message
news:6895fdb2.0406180241.5bb1f918@posting.google.com...

Hello all,

I'm trying to convert some VHDL code to Verilog and have a few syntax
problems. Can anyone see what I'm doing wrong in this code ?

// 18-06-04

module sync_compare_verilog(clk,aclr,enable,out,get_ready_pulse
,main_sync,sync_polarity,missing_sync,sync_valid,sync_out);

input
clk,aclr,enable,get_ready_pulse,main_sync,sync_polarity,missing_sync;

output sync_valid,sync_out;

reg sync_valid;
reg sync_out;
reg state;

parameter zero=0, one=1;

always @(state)
begin
case (state)
zero:
out = 1'b0;
one:
out = 1'b1;
default:
out = 1'b0;
endcase
end

always @(posedge clk or posedge aclr)
begin
if (aclr)

sync_valid = 1'b0;
sync_out = 1'b0;
state = zero;
else
case (state)
zero: // ----------------------------- STATE 0

if (enable == 1'b1) // wait for enable
if (get_ready_pulse == 1'b1)
if (main_sync == 1'b1) and (sync_polarity = 1'b0) // check which
way ..
sync_valid = 1'b1;
// sync_out = main_sync; -- = 1
state = one;
else if (main_sync == 1'b0) and (sync_polarity == 1'b1)
sync_valid = 1'b1;
// sync_out = main_sync; -- = '0'
state = one;
else
sync_valid = 1'b0;
// sync_out = main_sync; -- = '0'
state = zero; // wait for the start conditions ..
end;
else
sync_valid = 1'b0;
//sync_out = main_sync; -- = '0'
state = zero; // wait for the start conditions ..
end;
else
state = zero;
end;

one: // ---------------------------------------- STATE 1

if (missing_sync == 1'b1)
sync_valid = 1'b0;
state = zero;
else
state = one;
//sync_out = main_sync;
end;
endcase
end;
endmodule

 

[Peng Cong]

"duststar" <g9102025@mail.ttu.edu.tw> Đ´ČëÓĘźţ
news:88809cfd.0406181417.250ca130@posting.google.com...

The XST User Guide says that it supports the indexed vector part
selects.
I tried to write a simple module as follows to test the part-select.
However, when i run synthesize in ISE 6.1i, the "ERROR:Xst:850 - ttt.v
line 14: Unsupported" message occured.
What's the problem? I have already updated my ise version to 6.1.03i.

////////////////////////////////////////////////////////////////
module ttt(clk, Din, Dout);
input clk;
input [127:0] Din;
output [127:0] Dout;
reg [127:0] Dout;
reg [7:0] temp [0:15];
integer i;
always@(posedge clk)
begin
for(i=0;i<=15;i=i+1)
begin
temp=Din[(127-8*i) -:8]; //line 14
~~What's this mean?
end
Dout={temp[0],temp[1],temp[2],temp[3],
temp[4],temp[5],temp[6],temp[7],
temp[8],temp[9],temp[10],temp[11],
temp[12],temp[13],temp[14],temp[15]};
end
endmodule
////////////////////////////////////////////////////////////////

 

[Steven Sharp]

g9102025@mail.ttu.edu.tw (duststar) wrote in message news:<88809cfd.0406181417.250ca130@posting.google.com>...

The XST User Guide says that it supports the indexed vector part
selects.
I tried to write a simple module as follows to test the part-select.
However, when i run synthesize in ISE 6.1i, the "ERROR:Xst:850 - ttt.v
line 14: Unsupported" message occured.
What's the problem? I have already updated my ise version to 6.1.03i.

Your code works fine in NC-Verilog, so this must be an issue with XST.
Perhaps they require a command-line option to enable Verilog-2001
features. Or perhaps they support +: but not -:. Or perhaps they
don't like something about the expression you are using for the
starting bit position.

 

[Allan Herriman]

On 18 Jun 2004 15:17:42 -0700, g9102025@mail.ttu.edu.tw (duststar)
wrote:

The XST User Guide says that it supports the indexed vector part
selects.
I tried to write a simple module as follows to test the part-select.
However, when i run synthesize in ISE 6.1i, the "ERROR:Xst:850 - ttt.v
line 14: Unsupported" message occured.
What's the problem? I have already updated my ise version to 6.1.03i.

This bug was reported in comp.arch.fpga in January:
http://groups.google.com/groups?threadm=9phv00924evkervdfbj1bti6pf6cqdpsoe%404ax.com

BTW, they're up to 6.2.03i now. You are one release and three patches
behind.

Regards,
Allan.

 

[Dave Wilson]

Thanks for all you replies,

I'll get started on reading a few books ..

Dave

 

[Tom Hawkins]

"The Weiss Family" <weissfamily97@charter.net> wrote in message news:<10dkfo7neq0mfd7@corp.supernews.com>...

Hi All,

I want to create an array of components that I can use an index to access.
I am aware of the "generate" statement, but I don't know if I can do what I
need.

Take a look at Confluence. Unlike either HDL, Confluence elevates
components and systems (aka instances of components) to first-class
datatypes, allowing you to manage and manipulate them just like any
other datatype (integers, floats, bit vectors, etc.).

Here's what your example could look like in Confluence:

component my_component +A +B -C is
(* my_component definition here. *)
end

Let's assume we have a list of records that represent desired port
bindings for a number of systems:

wiring_harness = [(A:r B:s C:t) (A:u B:v C:w) (A:x B:y C:z)]

Now we can instantiate my_component for each record in the
wiring_harness list and return a new list of systems. To do this,
first create a component that takes a single port map and returns a
new instance of my_component:

component my_system_of_port_map +port_map -my_system is
my_system = {my_component} (* New my_component instance. *)
port_map = {ports my_system $} (* Connect the ports. *)
end

Now map my_system_of_port_map across the wiring_harness list, thus
returning a new list of systems:

my_systems = {List.map my_system_of_port_map wiring_harness $}

My_systems is now a list of 3 instantiated components connected by the
wiring_harness. To access those systems, use any of Confluence's list
manipulation functions:

(* head returns 1st element *)
first_system = head my_systems

(* tail returns list w/o 1st element *)
all_but_first = tail my_systems

(* returns nth element (index starts at 0) *)
third_system = {List.nth my_systems 2 $}

(* list unification *)
[sys_a sys_b sys_c] = my_systems

(* list constructor unification *)
head_system :: tail_systems = my_systems


I know the syntax differs from HDL, but I did my best to make it easy
to define components, instantiate systems, and wire blocks together.
If you have any questions, just shout.

Confluence is GPL and can be downloaded from:
http://www.launchbird.com/

I'm in the process of moving CF to it's new home:
http://www.confluent.org/ (should be up shortly)

Regards,
Tom

I need to have non-array signals used in the port map.
This is probably best explained by an example:

------------------------------------------------------------------
component my_component is
port (
A : in std_logic;
B : in std_logic;
C : out std_logic);
end my_component;


--- somewhere in another entity
signal u,v,w,x,y,z : std_logic;

COMP0: my_component port map(
A=>x,
B=>y,
C=>z);

COMP1: my_component port map(
A=>u,
B=>v,
C=>w);
-------------------------------------------------------------------

The problem is that I would like some structure that I can index by 0 to
access COMP0 and by 1 to access COMP1.
For example:

my_comp(0).some_function;
my_comp(1).some_constant;

etc....

Any ideas?

Thanks

 

[Alexander Gnusin]

mamta.chalana@st.com (mamtachalana) wrote in message news:<8dcc918.0406242241.6e5e63e5@posting.google.com>...

hello
i m doing modelling through system verilog,can anybody tellme how to
do that
suppose for example i want to make model of an "and gate",then what
will be the code and how can i compile this through VCS,DPI usage in
it...
in short which libraries i require for it..which compiler,what r the
prerequistes which i need for it..
thanks & regds
mamta

There is "SystemVerilog Support" part in VCS documentation. There are
also examples there.
And also there is another part about DPI.
Running SystemVerilog is simple: just add "+sysvcs" switch to the VCS
command line.

Regards,
Alexander Gnusin

 

[John_H]

The "parallel case" refers to all conditions - each "when" you have labeled
(which is syntactically incorrect) is not evaluated in sequence to provide a
priority structure - they're all evaluated at the same time. You should
still end up with a latch in the unspecified state. Perhaps you meant "full
case"? Check your tool documentation to find the implications of the
full_case.

"zanzyinlove" <zanzyinlove@zanzyland.com> wrote in message
news:cblf85$95k$1@newssrv.muc.infineon.com...

Hello,
WHen we have a condition where we have code like this
case ( a ) // a is a 2 bit number
when "00" : z = b ;
when "01" : z = c ;
when "10" : z = d ;
end case

I understand that if I dont have a default it synthesizes to a latch . But
if we use a "synopsys parallel case" what would it infer ?
if it infers a 3 : 1 mux , what happens if a = "11" ? Does it map to any
other state ? which one?

 

[Duane Clark]

Chris Carlen wrote:

module testbench();

reg [3:0] wave [0:191]; // create 192 x 4-bit waveform data table
initial
begin
$readmemh( "testhex.txt", wave ); // Load RAM from file
end
endmodule

--
My real email is akamail.com@dclark (or something like that).

 

[Kevin Neilson]

"Chris Carlen" <crcarle@BOGUS.sandia.gov> wrote in message
news:cbsjei0nld@news2.newsguy.com...

Hi:

I'm trying to use a memory in a Verilog testbench to generate arbitrary
waveforms to stimulate my Verilog module.

I'm using ModelSim XE II/Starter 5.7c with Xilinx Webpack 5.2i.

Modelsim complains with this message:

# Model Technology ModelSim XE II vlog 5.7c Compiler 2003.03 Mar 15 2003
# -- Compiling module testbench
# ** Error: E:/xilinx/CPLD-Magic-Box/cummins-camprox/testbench.tf(4):
near "$readmemh": syntax error
vlog -reportprogress 300 -work work
{E:/xilinx/CPLD-Magic-Box/cummins-camprox/testbench.tf}



The offending line of testbench code looks like this:

-------------------------------------------
module testbench();

reg [3:0] wave [0:191]; // create 192 x 4-bit waveform data table

$readmemh( "testhex.txt", wave ); // Load RAM from file

endmodule
-------------------------------------------

The text file looks like:

-------------------------------------------
4'h1 //count1(referringtothe74LS193datahere)
4'h1
4'h1
4'h1

4'h0
4'h0
4'h0
4'h0

4'h1 //count2
4'h1
// etc.
--------------------------------------------


Any clues?


Thanks.

Chris,

The format of the text file has to be in hex bytes, like this:
ff // first byte
ff ff // second and third byte
aa bb cc // more bytes

You can't use the 4'hf notation of Verilog.
You can get more flexibility by using the Verilog 2001 I/O commands.
-Kevin

 

[Brian Philofsky]

I agree that the omission of the initial statement is the most likely
cause of the syntax error but the format of the file also needs to be
modified to avoid the next error so both follow-up posters are correct.
The original poster is using 5.2i so this may not help him but for the
benefit of those on the more recent version of ISE, version 6.2i, the
Language Templates were updated for that release and include a fairly
good example I wrote for this function if I must say so myself. For
those that want to see this, open up the 6.2i Language Templates and go
to: Verilog --> Simulation Constructs --> System Tasks and Functions -->
File I/O --> Read Memory. There you will find an info file that explain
how to use this as well as a template that includes the missing initial
statement:

INFO:

// Information on the $readmemb and $readmemh system functions
// ===========================================================
//
// $readmemb is a system function which will read binary data from a
// specified file. The syntax is the following:
// $readmemb ("<file_name>", <reg_name> where the <file_name> is
// the name and location of the file containing the binary data and
// the <reg_name> is a 2-D register array in which the memory data
// is stored. The data file may only contain binary data, white
// spaces and comments. This function is generally executed within
// an initial block.
//
// $readmemh is the same as $readmemb with the exception that it
// inputs hex data as the read values.
//
// Example of reading binary data from a file:

reg [31:0] prom_data[1023:0];

initial
$readmemb("../data/mem_file.dat", prom_data);


Template for $readmemh:

reg [<memory_width>] <reg_name> [<memory_depth>];

initial
$readmemh ("<file_name>", <reg_name>



I did not include a sample file as I did not think it would be necessary
but perhaps I should based on what I have seen here. I may add that as
a possible enhancement for a future release.

-- Brian

 

[Chris Carlen]

Kevin Neilson wrote:

Chris,
The format of the text file has to be in hex bytes, like this:
ff // first byte
ff ff // second and third byte
aa bb cc // more bytes

You can't use the 4'hf notation of Verilog.
You can get more flexibility by using the Verilog 2001 I/O commands.
-Kevin

Thanks for the input.

Using the tip provided by Duane Clark, I have fixed the syntax error. I
simply needed to use an initial statement.

But while my compiler is no longer reporting a syntax error, I have yet
to run a sim and verify that the data is correctly read.

So I will have to confirm what you are saying later. But if you are
correct, then I will need this part of the picture too, so thanks!

Where can I learn about these Verilog 2001 IO commands? Are they
implemented in Modelsim? I have read the documentation a little bit.
I'll have to look in there some more.

Good day!



--
____________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarle@sandia.gov

 

[Jonathan Bromley]

On Tue, 29 Jun 2004 17:42:55 -0700, Chris Carlen
<crcarle@BOGUS.sandia.gov> wrote:

Where can I learn about these Verilog 2001 IO commands?

The IEEE standard (of course); but there's also some useful
stuff on Stuart Sutherland's V2k1 web site
http://www.sutherland-hdl.com/Verilog-2001/

Are they implemented in Modelsim?

AFAIK ModelSim implements all the new file I/O stuff. It
looks very much like the corresponding C functions
(getc, gets, fscanf, fseek, that sort of thing) but there
are many differences of detail, so proceed with caution.
Most of the yukky bits are inevitable because of the
bizarre way Verilog handles strings.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[allanwe]

Thanks for your information. it's helpful for me.

 

[Jim Wu]

Google is always a good start point to find answers:
http://www.google.com/search?hl=en&ie=UTF-8&q=verilog-library-directories+example

Excerpt from the first website that Google returns
http://www.veripool.com/verilog-mode_veritedium.html

Thus if you have a top level module that needs to find submodules in
subdirectories, you need to tell Verilog-Mode to look in the
subdirectories. The best way to do this is to define the library
variables at the end of each Verilog file that needs them:

// Local Variables:
// verilog-library-directories"." "subdir" "subdir2")
// verilog-library-files"/some/path/technology.v" "/some/path/tech2.v")
// verilog-library-extensions".v" ".h")
// End:

HTH,
Jim (jimwu88NOOOSPAM@yahoo.com remve NOOOSPAM)
http://www.geocities.com/jimwu88/chips


allanwe wrote:

dear sir
I have one problem about verilog-mode AUTOINST:
while different verilog at different directory, how to use
"verilog-library-directories" define directory?

allanwe