need a cheap student edition FPGA

[Ajeetha Kumari]

Hi,
As others noted, the straight answer is NO, but good news is
SystemVerilog does support this and I guess DC already supports such
structures (can't verify it though).

HTH,
Ajeetha
Independent ASIC DV Consultant
Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd
Edition
http://www.noveldv.com

ronjacob@gmail.com (Ron) wrote in message news:<84a4021f.0408232247.759540c@posting.google.com>...

Is multidimensional arrays allowed to be used as ports in Verilog 2000 syntax??

Ex. input wire [31:0] dummy [31:0];

 

[cka]

hi there,
there is a book called frquency synthesizer by egan.
c'ka

"Carson" <carson@ieee.org> wrote in message news:<cer2dj$k7f$1@home.itg.ti.com>...

hi

may any one recommend any good references on frequency synthesizer?

Thank you.

Carson

 

[Russell Fredrickson]

Hi Javier,

Well -- it depends on what your SystemC looks like. Generally a SystemC
to Verilog transformation would be thought as a synthesis step because
generally you are translating from a higher level of abstraction (behaviroal
SystemC) to a lower-level of abstraction (Verilog RTL). This is generally
thought to be a hard problem -- though there are several solutions out there
that are just coming to market (though some take C and not SystemC). Though
my understanding is that for those that do support SystemC -- only a certain
subset of the language is supported for synthesis (much like Verilog
synthesis).

One free tool I know of is Spark, but it takes only C as input, (
http://mesl.ucsd.edu/spark/ ) . Of course probably the closest fit to
SystemC to Verilog synthesis (though you would have to pay $$) is what Forte
offers ( http://www.forteds.com ) -- though there are other companies like
Synfora ( http://www.synfora.com/ ) and probably others (I'm sure if you did
a search on the DAC web page you might be able to come up with some others).
A google search on using keywords 'SystemC to Verilog' also seems to provide
interesting results

Though I suppose if the SystemC was written at the lower-level
RTL-level, one could probably come up with more of a translator to Verilog
RTL without too much trouble. However, using SystemC to write an RTL-level
description is generally thought to be a bad idea since Verilog is much more
suited to that task.

Hope that helps,
Russell

"Javier Castillo" <jcastillo@opensocdesign.com> wrote in message
news:Xns954F8152239A2jcastilloopensocdesi@193.147.184.15...

Hello:

I am looking for a free SystemC to Verilog translator. Anybody knows
one?

Regards

Javier Castillo
jcastillo@opensocdesign.com

 

[David Roberts]

On Sat, 21 Aug 2004 03:46:37 -0700, Pankaj Golani wrote:

Hi

While simulating one of my circuits where the delays are specified in
specify blocks,I got an unexpected result.
The code is

module(out,in)

reg A;

specify
if (A) (in => out) = 3;
ensdspecify

lets say out = in & A;lets say in = 1;

so 3ns after A goes to 1 out = 1, but if A is a pulse of 2ns only then
will this statement work as I am getting out = 0,the reason i see that
may be it evaluates at t=3ns while it should evaluate at t=0 and then
delay the output by 3ns.

When ever the driven value of "out" changes the timing output will wake
up and schedule the output to change. The condition of the timing output
is tested when the timing output detects a change on the input. In your
example

in = 1;

a -> 1 at t = 0ns
a -> 0 at t = 2ns

When "a" goes to 1 the output "out" is driven to a 1. The timing output
wakes up finds the condition true and schedules "out" to goto a 1 3ns
later. At t=2ns "a" goes to a 0 and the output "out" now is driven to a 0.
The timing output condition is false so a delay of 0 is chosen and
schedules "out" to goto 0 at 2ns. Because the output "out" is scheduled to
goto a 0 before it can goto a 1 the event for 3ns is canceled.

--David Roberts

I hope i make myself clear.
Please help me regarding this.

Pankaj

 

[Ralf Hildebrandt]

rajan wrote:

Thank you for your great help. Is there a better way to write this so that
it synthesizes well (or synthesizes without latches).

Then let us know, what do you really want! Which input signals (plural -
not singular!) should be muxed to which output (singular, not plural)?

(You did not describe any mux so I can only guess, what your intention was.)

In all cases - the solution I've posted, should be a good template to
adopt it to you own requirements:

process (sel, in_1, in_2, in_3, in_4, in_5, in_6, in_7, in_8)
begin
if (sel = '1') then
out_1 <= in_1;
out_2 <= in_2;
out_3 <= in_3;
out_4 <= in_4;
else
out_1 <= in_5;
out_2 <= in_6;
out_3 <= in_7;
out_4 <= in_8;
end if;
end process;

f'up comp.lang.vhdl

Ralf

 

[Mark W Brehob]

Hi,
Thanks to Srinivasan I can now safely say it is due to the installation
here.

Thanks to all for the help!

Mark

Srinivasan Venkataramanan <svenkat@synopsys.no_spam.co.in> wrote:

Hi Mark,
I hope you are referring to the "return value" as seen by the shell
after vcs detects a compile error. If so, it seems to be working fine, it is
giving me 255 as the status. I use tcsh, vcs under Solaris.
I created a syntax error and tries:

vcs ../syntax_err.v
------ VCS output -----------
*** Using loader /usr/ccs/bin/ld instead of cc ...

Parsing design file '../syntax_err.v'
Error-[SE] Syntax error
"../syntax_err.v", 5: token is 'endmodule'
endmodule // ab
^
1 error
CPU time: 0 seconds to compile

--------------

Now I see the return value:

UNIX> echo $status
255

Thanks,
Srinivasan
"Mark W Brehob" <brehob@wildwood.eecs.umich.edu> wrote in message
news:8hN2d.39$IP1.12004@news.itd.umich.edu...
Hello all,
I'm doing some work with vcs and I've hit what seems like a very silly
problem. When vcs exits with a compile error, the vcs program is still
returning a zero. I've never seen any other tool or complier behave that
way on a Unix box.

Does anyone have any nice suggestions for automatically figuring out if
vcs
failed? I realize I could parse the output from vcs, but that is somewhat
inconvenient (read would take me a few hours of changing other stuff).

Does vcs really behave that way? Is there any way to get it to actually
produce an error code when it actually hits an error?

Thanks for any thoughts or help.

Mark

 

[whizkid]

Thanks to all who replied to my post..

 

[info_]

B. Joshua Rosen wrote:

On Tue, 06 Jul 2004 20:48:58 +0000, A wrote:


Does anyone know of a good low cost (free or less than $50) text editor
(native Windoze executable) that can be used with Verilog? I have looked at:
(1) EditPlus (errors with {} in a PERL program; no BEGIN/END support)
(2) NEdit (not native windows; no BEGIN/END support)
(3) e93 (based on Tcl/Tk 8.4 from Active State; no BEGIN/END support)
(4) jEdit (Java is slow and awkward; no BEGIN/END support)
(5) TextPad (no BEGIN/END support)

But none of these will deal with BEGIN/END syntax (i.e., {} blocks are good
for "C", PERL, etc., but not for Verilog).

Any suggestions?

Thanks,
EigenFunctionsNOSPAM@YahooNOSPAM.com


Xemacs has Verilog and VHDL modes that do every thing you want. Get it
from http://www.xemacs.org.

I like Crimson Editor, it's 100% free and easily customizable.
http://www.crimsoneditor.com

I've extended the Verilog coloring to SystemVerilog in case anyone wants this.

But afaik, it's not capable of begin ... end tokenizing.

Bert Cuzeau

 

[info_]

Vinilkant Tejaswi wrote:

arbiter in verilog
and have tested using simple tests. Here is the problem

For arbiter
Since the arbiter has lot of signals as inputs and outputs. I can
generate stimulus quite easily. The input signals eventually goes
through lot of different states. I am going to write assertions for
them in vera.

Q1. How to write the response generator or monitor for this ? or How do
you generate the expected response to compare against the actual
response for correctness ? I have read some books/[chapters] on
verification I still dont see how to generate these response

Q1a. Should the assertions be embedded into the module or they should
be separate from the actual module and binded. Please share your
experience ?

Q2. How does one know when to use Vera, or System Verilog or SystemC.
Is it based on the comfort factor or other criteria.

Q3. I also want to know if there are reference testbenches[self
checking testbenches or stimulus and response monitors] that I can look
at. If some body can provide a complete example, I would greatly
appreciate.



-vinil

Hope it's not OT : just to mention that there is a commercial
tool (improveHPK OTOMH, google gets it) which formally verifies
the correctness of AHB peripherals. I know it is driven by the
proper assertions so there is no development/validation effort
on this side.
I know customers who tested and used the tool and were impressed.
I see two advantages for this approach : assertions are already
done and validated + vectorless validation (formal tool) which
find offending sequences and provides the counter-example (which
violates the AHB rule).
I have no relationship with the company, but I know the guys.

Bert Cuzeau

 

[Jim Wu]

"Vinilkant Tejaswi" <vinilkant@gmail.com> wrote in message
news:1114850435.950030.138920@z14g2000cwz.googlegroups.com...

arbiter in verilog
and have tested using simple tests. Here is the problem

For arbiter
Since the arbiter has lot of signals as inputs and outputs. I can
generate stimulus quite easily. The input signals eventually goes
through lot of different states. I am going to write assertions for
them in vera.

Q1. How to write the response generator or monitor for this ? or How do
you generate the expected response to compare against the actual
response for correctness ? I have read some books/[chapters] on
verification I still dont see how to generate these response

You need a functional/behavioral model of the DUT to generate the expected
response. The model can be high level abstact of the DUT. The same stimulus
are sent to both the DUT and the model. You can then compare the outputs to
see if they agree.

HTH,
Jim
jimwu88NOOOSPAM@yahoo.com (remove capital letters)

 

[m]

On 2 May 2005 13:02:27 -0700, axl_fugazi@yahoo.com wrote:

i have some verilog code for a synthesizable FIFO. i've declared a
register file. during synthesis with synopsys's design vision (design
compiler) is there any way i can provide hints to the synthesis tool
that it should use SRAM to implement the register file rather than
ordinary registers? what would be the directives for this?

thanks for any help.
pallav

Unlike those for FPGAs, ASIC synthesis tools don't infer memories.
You'll have to compile a block of SRAM and instantiate it in your
netlist yourself.

 

[Rob Dekker]

"botao" <blee@qualcomm.com> wrote in message news:ccjs6o$jd8$1@fair.qualcomm.com...

"ALuPin" <ALuPin@web.de> wrote in message
news:b8a9a7b0.0407080623.57e0d6b1@posting.google.com...
I believe that if you use Verilog 2001 configurations, ModelSim
supports referencing components from both Verilog and VHDL libraries.

As far as you do not use OEM versions of Modelsim ... isn't it?

I do have the full featured version ... Not using Verilog 2001 yet, can you
guys poing me to any webpage which explains the configuration thing?

You should not need to use configurations to get this simulated.
Configurations in Verilog are extremely confusing.

If the vhdl entity is compiled (with vcom) in the same library as you compile your verilog design (with vlog),
then I believe that it does get picked up by name by ModelSim.

Another way to go is to write the top level module in VHDL.
There you can use a component configuration to link the instance to the Verilog module.

Or just compile everything in one library, and then there is certainly no dual-language linking problem.

Rob

---Lee

 

[Avrum]

First, let me say that you must be VERY careful when declaring a path false.
Also, the description below is somewhat dangerous...

The statement below talks about a path being "timing critical". It is very
important to be clear (and I would stay away from this term, since it is too
close to sounding like a "critical path").

Static timing analysis (as the name implies) analyzes the circuit from a
"static" point of view; it is not a simulator, and it does not know (or
care) how circuits operate. Static timing analysis (or STA) analyzes every
timing path in a circuit, and compares it against a set of timing
constraints. By definition a static timing path starts at a timing
startpoint, and ends at a timing endpoint. A startpoint can be
- a primary input to the circuit
- the "CLK" input of a flip flop (propagating out through the Q/Q_ output)
- the gate input of a latch
- an artificially created startpoint using a synthesis constraint

an endpoint can be
- the input to a flip-flop or latch other than the CLK or gate
- a primary output of a circuit
- an artificially created endpoint

The STA tool analyzes ALL paths from each and every startpoint to each and
every endpoint and compares it against the constraint that (should) exist
for that path. All paths should be constrained, and are usually given
constraints by a number of basic constraints for the circuit; most paths are
constrained by the definition of the period of the clock, and the timing
characteristics of the primary inputs and outputs of the circuit.

Taking a typical example, the STA tool will add the delay contributed from
all the logic connecting the Q output of one flop to the D input of the next
(including the CLK->Q of the first flop), and then compare it against the
defined clock period of the CLK pins (assuming both flops are on the same
clock, and taking into account the setup time of the second flop and the
clock skew). This should be strictly less than the clock period defined for
that clock. If the delay is less than the clock period, then the "path meets
timing". If it is greater, than the "path fails timing". The "critical path"
is the path out of all the possible paths that either exceeds its constraint
by the largest amount, or, if all paths pass, then the one that comes
closest to failing.

Again, STA looks at all paths, regardless of the functionality of the
circuit. It also may have multiple constraints on a path; for example it may
have a "setup" constraint (as described above, the propagation path is less
than one clock), and also have a "hold" constraint (the path must be longer
than the hold requirement of the second flop, taking into account all clock
skew).

However, not all paths that exist in a circuit are "real" timing paths. For
example, let us assume that one of the primary inputs to the chip is a
configuration input; on the board it must be tied either to VCC or to GND.
Since this pin can never change, there are never any timing events on that
signal. As a result, all STA paths that start at this particular startpoint
are false. The STA tool (and the synthesis tool) cannot know that this pin
is going to be tied off, so it needs to be told that these STA paths are
false, which the designer can do by telling the tool using a "false_path"
directive. When told that the paths are false, the STA tool will not analyze
it (and hence will not compare it to a constraint, so this path can not
fail), nor will a synthesis tool do any optimizations on that particular
path to make it faster; synthesis tools try and improve paths until they
"meet timing" - since the path is false, the synthesis tool has no work to
do on this path.

Thus, a path should be declared false if the designer KNOWS that the path in
question is not a real timing path, even though it looks like one to the STA
tool. One must be very careful with declaring a path false. If you declare a
path false, and there is ANY situation where it is actually a real path,
then you have created the potential for a circuit to fail, and for the most
part, you will not catch the error until the chip is on a board, and (not)
working. Typically, false paths exists
- from configuration inputs like the one described above
- from "test" inputs; inputs that are only used in the testing of the chip,
and are tied off in normal mode (however, there may still be some static
timing constraints for the test mode of the chip)
- from asynchronous inputs to the chip (and you must have some form of
synchronizing circuit on this input)
(this is not an exhuastive list, but covers the majority of legitimate false
paths).

In answer to the original question, false paths should NOT be derived from
running the STA tool (or synthesis tool); they should be known by the
desinger as part of the definition of the circuit, and constrained
accordingly at the time of initial synthesis.

Also, just as a clarification, "asynchronous clear/reset paths" are NOT
normally false (as the initial statement says). While the ASSERTION of the
preset/clear input of a flip flop can occur at any time, the deasserting
edge of the preset/clear must (normally) be treated as a normal (i.e. not
"false") timing path. Most flops have what is called a "recovery" timing
constraint from the preset/clear input to the clock; the deasserting edge of
the preset/clear must not come too close to the active edge of the clock. If
it does, the flop does not know if it is supposed to continue to behave as a
flop in preset/clear (i.e. take the reset value), or operate as a normal
flop (i.e. take the value on the "D" input), and may do either (or neither,
or become meta-stable). Furthermore, when you have a state machine that has
multiple flops in it, it is important that all flops "emerge" from reset,
cleanly, and on the same clock cycle. Failing to do this can lead to nasty
surprises (i.e. chips that are not guaranteed to function correctly when you
deassert reset).

Avrum


"Chloe" <chloe_music2003@yahoo.co.uk> wrote in message
news:1115173368.649948.214660@z14g2000cwz.googlegroups.com...

Hello everyone,

This was written by Mark Johnson on Oct 17 1992, and for some reason, I
could not reply to the post (perhaps it's too old). Anyway, here is
what he wrote regarding false paths in static timing analysis:

-------------------------------------

IN THE DOMAIN OF STATIC TIMING ANALYSIS (if you don't know
what static timing analysis is, ignore the remainder of
this paragraph), "false path" means a path through the
logic/circuit that does exist, but which is known by
the human designer to NOT be a timing-critical path.
For example, asynchronous clear/reset paths. The static
timing analyzer reports them to the human, and the human
judges them to be "false", i.e. these paths are not
speed critical. Usually the human then puts them into
a list of "dont-annoy-me-any-more" paths, the
"known-false-paths" list, and thereafter the timing
analyzer refrains from reporting them.

--------------------------------------

My question is: what do you define as TIMING-CRITICAL paths? Any useful
examples given would be appreciated.

The idea of defining false paths is to avoid the synthesis tool from
deriving unnecessary logic, I/O replication, and/or false timing
constraint failure report. Are these false paths derived using the STA
tool first, isolated in the false paths list, and then the tool rerun
for further STA? How does the designer determine what the false paths
are before STA?

Please forgive the triviality of the questions as I am very new at
this.

Thanks very much in advance.

Kind regards,
Chloe

 

[Hans]

Hope it's not OT : just to mention that there is a commercial
tool (improveHPK OTOMH, google gets it) which formally verifies
the correctness of AHB peripherals. I know it is driven by the
proper assertions so there is no development/validation effort
on this side.
I know customers who tested and used the tool and were impressed.
I see two advantages for this approach : assertions are already
done and validated + vectorless validation (formal tool) which
find offending sequences and provides the counter-example (which
violates the AHB rule).
I have no relationship with the company, but I know the guys.

Bert Cuzeau

SolidPC is another tool which does the same job, see
http://www.saros.co.uk/amba/

Hans.
www.ht-lab.com

 

[Hans]

"Chloe" <chloe_music2003@yahoo.co.uk> wrote in message
news:1115173368.649948.214660@z14g2000cwz.googlegroups.com...

Hello everyone,
snip

My question is: what do you define as TIMING-CRITICAL paths? Any useful
examples given would be appreciated.

The idea of defining false paths is to avoid the synthesis tool from
deriving unnecessary logic, I/O replication, and/or false timing
constraint failure report. Are these false paths derived using the STA
tool first, isolated in the false paths list, and then the tool rerun
for further STA? How does the designer determine what the false paths
are before STA?

Hi Chloe,

Timing critical path are those path that do not meet your timing. What
normally happens is that after synthesis the tool will give you a number of
path which have a negative slag. The first thing you would do is to make
sure those path are not false or multicycle since it that case you can just
ignore them. This can be quite a lengthy and difficult task but there are
now tools coming to market which can detect these path automatically,
Fishtail automation and BluePearl are 2 companies that springs to mind.

Hans.
www.ht-lab.com

Please forgive the triviality of the questions as I am very new at
this.

Thanks very much in advance.

Kind regards,
Chloe

 

[m]

On 7 May 2005 21:04:53 -0700, "Taha" <thamiral@gmail.com> wrote:

Dear all,

Can someone help me rewrite the segment of code below in order to make
the code read like a real HDL segment as opposed to a netlist whilst
still being able to compile into a maximum of 34 muxes per partial
product row. (i.e. I really dont belive that I should have to write out
the equation for each bit when I use an HDL, or else, whats the
advantage of HDL over schematic capture )

In addition, since I will need 8 rows of partial products, do i have to
create 8 instances of ppRow or can I use a for loop to put the data
into some sort of a matrix.

Please do note that this should be combinational logic only ... no
clocks/sequential ...

how about

reg [15:0] ppRow;
integer i;

always @(*)
begin
for (i=1; i<16;i=i+1)
ppRow = pass ? ((sign)?a: ~a) :
(sign?[a[i-1]:~a[i-1]);
ppRow[0] = (pass) ? ((sign)?a[0]:~a[0]) : 1'b0;
end

?

 

[info_]

Miller2000 wrote:

Hi‎ ‎‎!‎
I‎ ‎have‎ ‎problem‎ ‎with‎ ‎the‎ ‎following‎
‎code‎.‎

Not very surprising.
Where did you learn this style of RTL coding ?
It doesn't look right at all.

Have you looked at usual RTL coding style, synchronous
design basics, how to code an FSM in Verilog etc ?

Bert Cuzeau

 

[Mike Lewis]

"Miller2000" <miller2000@walla.com> wrote in message
news:1115637200.077647.174850@z14g2000cwz.googlegroups.com...

The gool of the program is:
Latch input 8 bits at "posedge of latch8" OR "negedge of latch8tag"
and put it in FF1.
Latch input 8 bits at "negedge of latch8" OR "posedge of latch8tag"
and put it in FF2.
Output FF1 + FF2 to output 16 bits at "posedge of latch16".

There is no clock in the system!

If there is no "clock" in the system ... it would be impossible to latch
anything into a flip-flop. Are there some external signals that are supposed
to be use a as a clock ... a write enable perhaps? A synchronous element
such as a FF requires a clock ... even a latch needs a "clock" ... or at
least
a signal whose edges shuts the latch and holds the value. I think you have
mis-communicated the homework assignment to us.

Mike

 

[Mike Lewis]

"Miller2000" <miller2000@walla.com> wrote in message
news:1115646489.259016.274670@f14g2000cwb.googlegroups.com...

Hi Mike!

The? ?customer? ?wants? ?that? ?there? ?will?
?be? ?no? ??"?clock?"??.?

I? ?want? ?to? ?latch? ??"?input? ??8??
?bit?"?? ?into? ?a? ?flip?-?flop? ?when?
??"?posedge? ?of? ?latch?8??"?? ?OR?
??"?negedge? ?of? ?latch?8?tag?"?? ??,?
so? ?it? ?is? ?external? ?signal? ?that?
?make? ?the? ?latch? ?to? ?the? ?flip?
?flop?.?

Is? ?it? ?imposable? ????

Thanks.
miller2000

So you have two possible "clocks" for the storage element. If this is an
FPGA
implementation I would have to say that the chances of success are slim ...
it really
depends on your IO timing. FPGAs don't deal very well with multiple clocks
feeding
FFs. If it's an ASIC implementation you will probably have success .. the
clocking
aspects are much more versatile in an ASIC.

Basically what you are trying to do is feed two clock sources into a mux ...
not
sure what the mux control is .. and the output of the mux feeds the FF clock
input. In an FPGA this likely won't be on any global routing resources so,
from a timing perspective you will be at the mercy of the FPGA P&R, which
very likely will be different every compile.

Maybe you could step back and give the customer requirements to the
newsgroup
and maybe other solutions can be offered. Your description sounds like you
have already taken the customer requirements and come up with a solution.
Maybe there are other solutions.

Mike

 

[Jim Wu]

<gbirot@yahoo.com> wrote in message
news:1115653537.436549.63460@f14g2000cwb.googlegroups.com...

I try to compile a verilog description into a specific library like
this :
add_file -verilog -lib my_lib "myfile.v"

-lib is not needed for verilog

HTH,
Jim
jimwu88NOOOSPAM@yahoo.com (remove capital letters)

and it doesn't work, whereas its vhdl version works perfectly :
add_file -vhdl -lib my_lib "myfile.vhdl"

i can cope with this problem if i use a shell for the verilog
description, but i have a lot a files to translate and i don't want to
spend my time for this. If i use the correct syntax, its seems there is
a bug in synplify (i tried with 7.7.1 and 8.0)

could anyone help me ?

thanks