need a cheap student edition FPGA

[Jason Zheng]

perltcl@yahoo.com wrote:

Hi

Does any tool so far support synthesizable "part select memory" like:

reg kkk [0:31];
....
kkk [0:4] = 3;
kkk [5:16] =4;
....
...etc.

synplify?

Thanks.

Think about this would mean in terms of hardware. In your example, it
means a memory of 32X1, where the lower 5 rows gets assigned to value of
3 and middle 12 bits gets the value of 4. This requires that all rows of
the memory can be read/write at the same time, which is very hard to
implement (most memory blocks have 1-2 read/write ports).

One alternative is that if you have a small amount of memory to manage,
just use registers or register files.

Another alternative, if you just need to initialize the ram, is to load
the initial values from a rom, and use a state machine (which should be
little more than a counter) to drive the address bus.

cheers,

jz

 

[Jason Zheng]

rufrothy@gmail.com wrote:

All,

The OVL Committee is discussing potentially using Verilog 2001
constructs in future releases the of the OVL Library. I know from my
own experiences that as recently as 6 months ago support for Verilog
2001 was not very robust across the industry. I am trying to gague
peoples opinions on this topic as well as gather info as to the current
state of Verilog 2001 support. I would apprecaite feedback from users
and verilog tool providers on their support of verilog 2001.

Who out there has a complete implimentation of Verilog 2001 in their
product?

Is it available today?

Any information provided will be of help to the OVL Committee

Thanks,
Sean Smith

Did you read Cliff Cumming's scoreboard on verilog 2001?
http://www.sunburst-design.com/papers/CummingsDVCON2003_V2K1_SimScore.pdf

-jz

 

[Outsource_University]

"Jason Zheng" <xin.zheng@jpl.nasa.gov> wrote in message
news:d33qrq$hbs$1@nntp1.jpl.nasa.gov...

rufrothy@gmail.com wrote:
All,

The OVL Committee is discussing potentially using Verilog 2001
constructs in future releases the of the OVL Library. I know from my
own experiences that as recently as 6 months ago support for Verilog
2001 was not very robust across the industry.
Who out there has a complete implimentation of Verilog 2001 in their
product?


Did you read Cliff Cumming's scoreboard on verilog 2001?
http://www.sunburst-design.com/papers/CummingsDVCON2003_V2K1_SimScore.pdf

That paper is more than 2 years old. I believe Mr. Cummings published an
update a while ago, but I can't find a public link. Verilog-2001 support
(among simulators) is much improved from 2 years ago.

As for 'complete', I don't think any one of them is complete. "Gaps" in
support tend to revolve around limitations in the implementation of
generate/endgenerate, and multi-dimensional wire/reg array manipulation.

 

[Srinivasan Venkataramanan]

Hi Sean,
Well, I'm not sure how many vendors will give you a detailed answer
to this question here in this forum - simply b'cos there are just so many
tiny features that gets documented in few pages in tools' documentation
usually. Turning the table around - is it possible for the OVL committee to
list the features that you are considering to use within OVL from
verilog-2001? IMHO that list will be a much smaller list than the "what's
new in Verilog-2001" kind of a list.

My aim is not to throw the ball in the other court, rather to see a quick
resolution to this sincere effort. Hope you appreciate that.

Thanks,
Sri

--
Srinivasan Venkataramanan
Co-Author: SystemVerilog Assertions Handbook, http://www.abv-sva.org
Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition.
http://www.noveldv.com
I own my words and not my employer, unless specifically mentioned
<rufrothy@gmail.com> wrote in message
news:1112890895.694060.287960@f14g2000cwb.googlegroups.com...

All,

The OVL Committee is discussing potentially using Verilog 2001
constructs in future releases the of the OVL Library. I know from my
own experiences that as recently as 6 months ago support for Verilog
2001 was not very robust across the industry. I am trying to gague
peoples opinions on this topic as well as gather info as to the current
state of Verilog 2001 support. I would apprecaite feedback from users
and verilog tool providers on their support of verilog 2001.

Who out there has a complete implimentation of Verilog 2001 in their
product?

Is it available today?

Any information provided will be of help to the OVL Committee

Thanks,
Sean Smith

 

[Rob Dekker]

<perltcl@yahoo.com> wrote in message news:1112858147.590957.173170@f14g2000cwb.googlegroups.com...

Hi

Does any tool so far support synthesizable "part select memory" like:

reg kkk [0:31];
....
kkk [0:4] = 3;
kkk [5:16] =4;
....
...etc.

In Verilog 95/2001, this is simply not allowed by the language definition.
All tools should error out on it (cannot take a part-select of a 'memory').

In System Verilog, the 'memory' (a declaration with a range right of the identifier)
is now called a 'unpacked' array. The 'unpacked' term says that the elements
should be specified separately, and exactly the correct amount of elements.

In 'unpacked' arrays, each individual element is considered to be by itself,
without any relation to the other elements.

So for kkk[0:4] a value of 4 elements of 1 bit each needs to be supplied.
Not 32 bit in a single literal (integer 3). And not any single literal any way.
Prepare to start using concatenations a lot.

The purpose of 'unpacked' arrays is to avoid that users accidentally overwrite
values of elements that they did not intend to change.

This (accidental overwrites) happens very easily with 'packed' arrays (range is
on the left side of the identifier). In 'packed' array's, all the elements are glued
together and can be overwritten by zero/sign extension of a single literal.

Packed arrays are thus a lot easier, but also a lot more dangerous to use.

Rob

 

[Rob Dekker]

Works fine with Quartus II, and a spectrum of other tools.

"ppc" <ppc_google@yahoo.com> wrote in message news:a3d967e8.0504101729.6339dcaf@posting.google.com...

"EdA" <ed.arthur@gmail.com> wrote in message news:<1113045859.767351.161780@g14g2000cwa.googlegroups.com>...
This works fine in the GPL version of "cver":

/Ed

I believe it is okay with all simulators. But I'm not sure about the
synthesizer tool.

 

"jjsandoval1962@aol.com" <jjsandoval1962@aol.com> writes:

I am currently helping some DSP and FPGA engineers with their verilog
test-bench verification environment ...
... I am thinking that the DSP guys could come up with a IQ
generator model (created in their Matlab tool) that would allow me to
introduce all those little exceptions that would really test the design
(noise, bit corruption, etc). Although I am not sure how I would marry
this Matlab model to my verilog test-bench.
Is anyone out there testing something similar. What methodology are
you using for this type of scenario?

You might want to consider this:

http://www.mathworks.com/products/modelsim/

if you happen to be using ModelSim.

Hope this helps!

 

[Egbert Molenkamp]

Sometimes a register in a register file has a constant value. E.g. R0 in the
MIPS is always 0.
http://www.web-ee.com/primers/files/MIPS/MIPS.htm

Maybe you have a similar problem
(hence your IP model is incorrect)

Egbert Molenkamp


"williams" <stud_lang_jap@yahoo.com> schreef in bericht
news:d02ff4ca.0504190226.51d4a56@posting.google.com...

Hello,

I am integrating an IP core and i am facing a strange problem.
One of the register of the IP core which is R/W register is not
writable ..in simulation I am able to write but when ported to FPGA I
am not able to write.its default value is also wrong and when I write
to one fixed register in that core... its value gets reflects on that
register. Reset value of all the register is ok and I am able to read
and write all R/W registers except one. What may be the
problem...since simulation results shows that the IP is ok.so I cannot
pin point that tell the IP vendor that there is a bug in ur IP...

Any feedback???
Thanks and Regards
Williams

 

[Navneet Rao]

Hi Williams:

If you are using Verilog: Check your port-width mismatches in the
instantiation(s)/wire(s)/reg(s) definitions. Even if verilog, does not
report above errors,
go through the synthesis report warnings in detail.

-Navneet

williams wrote:

Hello,

I am integrating an IP core and i am facing a strange problem.
One of the register of the IP core which is R/W register is not
writable ..in simulation I am able to write but when ported to FPGA I
am not able to write…its default value is also wrong and when I write
to one fixed register in that core... its value gets reflects on that
register. Reset value of all the register is ok and I am able to read
and write all R/W registers except one. What may be the
problem…..since simulation results shows that the IP is ok…so I cannot
pin point that tell the IP vendor that there is a bug in ur IP…..

Any feedback???
Thanks and Regards
Williams

 

[backhus]

Hi Williams,
have you made a timing simulation of the placed and routed design?
Maybe the write enable has a high delay for that one register, and
doesn't meet timing requirements anymore. (Just a guess)
Is your IP-core a softcore (only source) or a preplaced and wired hardmacro?

have a nice synthesis
Eilert

williams schrieb:

Hello,

I am integrating an IP core and i am facing a strange problem.
One of the register of the IP core which is R/W register is not
writable ..in simulation I am able to write but when ported to FPGA I
am not able to write…its default value is also wrong and when I write
to one fixed register in that core... its value gets reflects on that
register. Reset value of all the register is ok and I am able to read
and write all R/W registers except one. What may be the
problem…..since simulation results shows that the IP is ok…so I cannot
pin point that tell the IP vendor that there is a bug in ur IP…..

Any feedback???
Thanks and Regards
Williams

 

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Unregistered version

 

[Jason Zheng]

mansoor.naseer@gmail.com wrote:

2. The second question indirectly relates to the PCI, however, before
that, can someone please tell me exactly how plug and play works? When
the computer boots what steps are taken and how the system determine
how many legal devices are connected to the pci.

During the configuration phase of the PCI, the kernel probes the PCI bus
for any PCI devices using the PCI configuration commands. If a device is
found, the following steps are taken:

1. Find out how much address space the device needs for each base address.
2. Allocate the address space within the kernel, usually by updating
some address table.
3. Tell the PCI device to use address xxxx for base address y

During the configuration phase, obviously you can't address the PCI
device with the I/O space or memory space address. You use the device
number, bus number, function number, and register number to address. The
PCI host chip then asserts corresponding the IDSEL pin of the PCI device
to notify that it is being configured.

hth,

jz

 

[Steven Sharp]

ndesi@talk21.com (ndesi) wrote in message news:<cf531019.0405201505.3d2daecd@posting.google.com>...

How i can read file using $fscanf that look like below
--------------
1 1 1 1 1 1 1
1 0 0 1 0 1 0
etc.
--------------
I am able to read file that has all bits together without
space between them

If the file has the bit values separated by white space, then
you will have to read each as a separate number with a separate
format descriptor. If these are supposed to be bits of a vector,
the obvious way to do it is with a loop:

for (i = MSB; i >= LSB; i = i - 1)
code = $fscanf("%b", vector);

Or you could write a script to remove the spaces from the
file before you try to read it.

 

[Jonathan Bromley]

On Thu, 20 May 2004 09:17:56 +0100, "DW"
<dave_wooff@hotmail.com> wrote:

I was thinking of an assert which would raise an error when
synthesizing - not when simulating. Basically I want to
raise an error if a particular combination of (potentially
defparam overriden) parameter values is incorrect, so
there would be no point continuing with the compilation.

Consider using VHDL. I frequently use VHDL assertions for
exactly this purpose. It's a great approach, and synthesis
tools give you appropriate messages.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[John]

Take a look at opencores.org. I've used the ps/2 core, and it was
really easy to integrate into my design. This particular design
supports bidirectional communication with a keyboard, but if you only
want to receive scan codes you can just disable the other features. I
only wanted the scan codes, and it works fine. It doesn't take up much
space either.

Thanks for the tip. For some reason I can't get this module hooked
into my project. Maybe I'm misunderstanding where I'm supposed to
interface with it. All I want is to be able to put this into my
project, hook it up to the main clock, ps2_clock, and ps2_data lines,
and then have the ability know which keys are being held down at any
given time. If you (or anyone else who also has experience using this
module) could explain how you accomplished this it would be great
because the project appears to have no documentation (that I could
find atleast).

Thanks again for your time.

 

[Jeremy Webb]

TheCppMaster@aol.com (John) wrote in message news:<a25b4de5.0405190905.362f41f0@posting.google.com>...

Hello,

Does anyone know of freely available Verilog code for a simple PS/2
keyboard controller. I'm looking to add some really basic keyboard
support to a project that I'm working on and if someone has already
made some sample code available it could speed up my work quite a bit.
I'm looking for something really simple. I just need to be able to
read the scancodes (no mouse support or support for sending data to
the keyboard). Please let me know.

Thanks

Take a look at opencores.org. I've used the ps/2 core, and it was
really easy to integrate into my design. This particular design
supports bidirectional communication with a keyboard, but if you only
want to receive scan codes you can just disable the other features. I
only wanted the scan codes, and it works fine. It doesn't take up much
space either.

Hope this helps,

Jeremy

 

[Steven Sharp]

"NewsHound" <newshound@austin.rr.com> wrote in message news:<P31tc.511$4x2.206@fe2.texas.rr.com>...

I've used it anyway,and our tools grumble but still work. NC-Verilog
warns you about it and defaults the multiplier to 1, so as long as you
realize that you can (carefully) still use it.

Actually, I believe that NC-Verilog produces a 1'b0 for it. This was
what Verilog-XL did for it in non-optimizing mode, so we chose to
regard that as the de facto standard.

The only case where I have seen this come up is in sign-extension of a
value to a different width, before v2001 added signed arithmetic. I.e.

out = {{(out_width-in_width){in[in_width-1]}}, in};

This replicates the sign bit to fill the excess bits of out. But if
out_width is less than or equal to in_width, you get a replication
count that is negative or zero. Fortunately, it doesn't really matter
what you produce for the replication in this situation. Whatever you
produce will get truncated during assignment to out, since the whole
point is that out was too narrow to need any extension bits.

It has been officially proposed that this be allowed in the next version
of the IEEE standard. As Stephen Williams has mentioned, this would
require dealing with the issue of zero-width expressions, which are
currently not possible in Verilog.

 

[Steven Sharp]

"David Wooff" <dave@dmwooff.freeserve.co.uk> wrote in message news:<c90il2$a9$1@news5.svr.pol.co.uk>...

I had a vague thought along these lines but considered that it may be a
little over complicated. The include file idea on the other hand seems
promising although is this a generally accepted usage?

"A Verilog HDL Primer" by Jayaram Bhasker describes both the included
file and another top-level module as approaches to sharing tasks and
functions. So the idea is certainly in the mainstream. I don't know
to what extent these approaches are generally accepted usage.

I guess if it's
legal and if it works then fair enough, but is it akin to placing a function
definition in a 'C' header file?

A C header file generally just contains the function prototype. Here
you would be putting the entire function text into the include file and
pulling that in. It is equivalent to having typed the same text into
the different files manually, only with less typing and the ability
to change the definition later in only one place. In C, the different
callers are calling the same function, while here they would be calling
different functions that just happen to be textually equivalent.

Note that you can parameterize the included function differently in
the different includes by having it refer to a parameter name that
you define to an appropriate value in the including module. It isn't
the cleanest thing, since you are relying on the names matching, but
it should work. If you forgot to define a matching parameter name in
the module, you would get a compile error. Keep in mind that `include
just blindly includes the text from the file, which gets compiled as
if it had appeared verbatim in the including file.

 

[Jeremy Webb]

jeremy.webb@folsom.com (Jeremy Webb) wrote in message news:<a44fc25f.0405260756.499751ce@posting.google.com>...

TheCppMaster@aol.com (John) wrote in message news:<a25b4de5.0405241902.3bce10d@posting.google.com>...
Hello,

It seems that we were looking at two different things (although they
are probably just different versions of the same thing). I was
confused at first when your instantiation didn't match up with the
module I was looking at. I Googled the module name and the only
legitimate result gave me the code to the module that I assume you
were referring me too. This looks much simpler than the one I was
looking at earlier (it made up of was about 8 files).

However I still can't get it to work. I really can't think of what
could be causing the problem. Is there any special way in which I need
to process the scan-codes or ascii-codes? This is pretty strange (it
seems as if everything is working but the design just won't read the
codes).

Thanks again (especially for inadvertently pointing me to the right
module!)

John,

Do you have pull ups on your clock and data lines of the PS/2
interface. If you read in the header of ps2_keyboard.v, there's some
information on the interface to the PS/2 keyboard. You should only
need one file and that's ps2_keyboard.v. I've posted it on my
personal website for you to grab:

http://webpages.charter.net/jeremywebb/ps2_keyboard.v

I'll leave it there for a couple of days before I remove it. When I
did the first spin of my board I forgot to add the pull ups on my
board, but was able to use the Spartan IIE's internal pull ups to fix
the mistake. I also found a neat part from ST Microelectronics. It's
part number is KBMF01SC6. It's an EMI FILTER AND LINE TERMINATION FOR
PS/2 MOUSE OR KEYBOARD PORTS. It's got the pull ups and emi filter all
in one chip.

As for any post processing of the scan codes or ascii codes, you are
not required to do anything. Just interpret them as normal ascii or
scan codes. The ps2_keyboard.v file has a big decoder that translates
a select portion of the keyboard mapping scan codes to ascii codes.

Hope this helps,

Jeremy

John,

You'll also notice that I had to customize some of the parameters for
the ps2_keyboard.v module. These are design dependent, and will
change depending on what clock you feed it. The actual clock rate
that I fed the module was 44.4MHz.

Hope this helps,

Jeremy

 

[me tew!]

how about some jobs for the United States!?!