need a cheap student edition FPGA

[Jason Hu]

SRAM is much smaller than FF.

SRAM has 4 or 6 transistors per bit.
FF usually has 15-20 transistors.


wtx@umem.com (Weng Tianxiang) wrote in message news:<511e4538.0405190726.9399ff7@posting.google.com>...

Hi,
I want to know which has larger IC area, flip-flop and SRAM. Why? and
how many transistors are there for flip-flop or SRAM?

Weng

 

[Petter Gustad]

"me tew!" <suckers@aol.com> writes:

how about some jobs for the United States!?!

There has been many posts for jobs in the US here previously. This
newsgroup is worldwide.

Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

 

[David Wooff]

--
Dave Wooff
dave@dmwooff.freeserve.co.uk
Steven Sharp <sharp@cadence.com> wrote in message
news:3a8e124e.0405270920.3eb66939@posting.google.com...

sharp@cadence.com (Steven Sharp) wrote in message
news:<3a8e124e.0405261312.52f988bb@posting.google.com>...

Note that you can parameterize the included function differently in
the different includes by having it refer to a parameter name that
you define to an appropriate value in the including module. It isn't
the cleanest thing, since you are relying on the names matching, but
it should work. If you forgot to define a matching parameter name in
the module, you would get a compile error.

Shalom Bresticker has pointed out to me that you could declare a
parameter inside the function body, and override it to a different
value using a defparam. This would avoid the uncleanness I mentioned.

So, is the parameter scope limited to the function or the whole module? How
is this different to the 'include method? Could you provide a simple
example? (if its not too much trouble).
Many thanks,
DW

 

[davidbarby]

thanks a lot for your reply, but I think I don't catch your meaning.
Frankly, I lack experience about it and looking for some helps. Could you
please advise me something? I need some completed code for reference.
//

 

[Andy Peters]

bluedoze@yahoo.com (BlueDoze) wrote in message news:<a53ecee3.0406010651.54bacd2d@posting.google.com>...

Hi,

I want to know the always statement that's corresponding to this VHDL
process statement.

process ( reset, async_set, clock )
begin

if ( reset = '1' ) then
output <= input1 ;
elsif ( async_set = '1' ) then
output <= input2 ;
elsif ( clock = '1' and clock'event) then
if sync_set = '1' then
output <= input3 ;
else
output <= input;
end if;
end if;

end process;


I have tried
always @(posedge clock or posedge reset or posedge async_set)

but I had problems with the negative edge of the clock so I added.

What problems? Your VHDL is not sensitive to the falling edge of the
clock, so your Verilog sensitivity list is correct.

always @(posedge clock or negedge clock or posedge reset or posedge
async_set)

but again I found problems with other negative edges.

Again, what are your problems?

--a

 

[David Wooff]

DW <dave_wooff@hotmail.com> wrote in message
news:c9ie8n$78a$1$8302bc10@news.demon.co.uk...

"BlueDoze" <bluedoze@yahoo.com> wrote in message
news:a53ecee3.0406010651.54bacd2d@posting.google.com...
Hi,

I want to know the always statement that's corresponding to this VHDL
process statement.



process ( reset, async_set, clock )
begin

if ( reset = '1' ) then
output <= input1 ;
elsif ( async_set = '1' ) then
output <= input2 ;
elsif ( clock = '1' and clock'event) then
if sync_set = '1' then
output <= input3 ;
else
output <= input;
end if;
end if;

end process;


I have tried
always @(posedge clock or posedge reset or posedge async_set)

but I had problems with the negative edge of the clock so I added.
always @(posedge clock or negedge clock or posedge reset or posedge
async_set)

but again I found problems with other negative edges.

Appreciate your help.
Bluedoze

Not being over-familiar with VHDL, I assume in the following that you are
interested in the negative going edge of the clock
i.e. "elsif ( clock = '1' and clock'event) then"
in this case, you should only have a negedge clock statement in the
procedural code.

You have both combinatorial logic and synchronous logic. i.e. reset and
async_set are purely asynchronous so why not try this:

// register required to hold required state when clock occurs
reg sync_input;

// continuous assignment code
reset ? output = input1 : ( async_set ? output = input2 : sync_input );

// procedural code
always @( negedge clock )
if sync_set
sync_input <= input3;
else
sync_input <= input;

I have not tried to compile this so please accept my apologies if I have
got
it wrong.

DW

I knew I'd get something wrong (still haven't compiled it though)

// register required to hold required state when clock occurs
reg sync_input;

// continuous assignment code
output = reset ? input1 : ( async_set ? input2 : sync_input );

// procedural code
always @( negedge clock )
if ( sync_set )
sync_input <= input3;
else
sync_input <= input;

 

[davidbarby]

many thanks wooff.
it is very useful....

 

[Hendra Gunawan]

"UJMi" <iujmi@hotpop.com> wrote in message
news:8cb34c9d.0405301315.6c9a4d3f@posting.google.com...

hello everyone,
I was wondering if you people can help me with this, If you needed
a book on verilog, what would you like to have in it and discussed in
a major way? Like if say that book is supposed to be for undergraduate
level student reference book. Please let me know if possible by giving
a list of topics you would like to see in there. Actually im tryin to
write one

1. First of all, I don't want to see another Verilog book that try to teach
digital design. The two should be written seperately.
2. Explain from the very beginning and gradually add more detail as the
chapters progress.
For example: Explain what a module is by writing its IO ports without
writing the detail implementation of the module.
3. For each example, give the schematic equivalent of the code. For example:
if you write a code for a D Flip Flop, draw a picture of D flip flop
underneath the code.
4. Teach how to write a testbench from the very beginning. For example: Once
you write a complete code for a Full Adder, write the testbench for the Full
Adder.
5. Please don't try to mislead the reader by making an impression that
Verilog is just like C. I hate to see people teaching Verilog by giving
example of how to print "Hello World" with Verilog.
6. Explain which one of the language constructs are synthesizable.
7. I have read several Verilog books when trying to learn the language. You
probably should look over other Verilog books before write your own. The
best of the best for a beginner is Verilog HDL by Samir Palnitkar. The book
is very easy to understand and it gives very detail explanation of important
language constructs. This is the only book that clearly explain blocking and
non blocking assignment, along with the mechanism of always and intial
block, and when to define a signal as reg or wire. See if you can write
better book than his!

Hendra

 

[UJMi]

Thanx Hendra,
Your help is very much appreciated...btw as for the book Verilog
HDL by Samir Palnitkar is the same book from which I learnt Verilog
myself. Thanx a bunch to my teacher who didnt recommended any other
book, but actually I havent been a real big fan of it either...infect
I dont like any book on the DHD much...all im thinking is a very
simple book which any newbie or intermediate level person can keep on
his/her side with view to be used as a reference book.
Thanx again,
Salaamz
UJMi

"Hendra Gunawan" <u1000393@email.sjsu.edu> wrote in message news:<c9mbnn$7a26s$1@hades.csu.net>...

"UJMi" <iujmi@hotpop.com> wrote in message
news:8cb34c9d.0405301315.6c9a4d3f@posting.google.com...
hello everyone,
I was wondering if you people can help me with this, If you needed
a book on verilog, what would you like to have in it and discussed in
a major way? Like if say that book is supposed to be for undergraduate
level student reference book. Please let me know if possible by giving
a list of topics you would like to see in there. Actually im tryin to
write one

1. First of all, I don't want to see another Verilog book that try to teach
digital design. The two should be written seperately.
2. Explain from the very beginning and gradually add more detail as the
chapters progress.
For example: Explain what a module is by writing its IO ports without
writing the detail implementation of the module.
3. For each example, give the schematic equivalent of the code. For example:
if you write a code for a D Flip Flop, draw a picture of D flip flop
underneath the code.
4. Teach how to write a testbench from the very beginning. For example: Once
you write a complete code for a Full Adder, write the testbench for the Full
Adder.
5. Please don't try to mislead the reader by making an impression that
Verilog is just like C. I hate to see people teaching Verilog by giving
example of how to print "Hello World" with Verilog.
6. Explain which one of the language constructs are synthesizable.
7. I have read several Verilog books when trying to learn the language. You
probably should look over other Verilog books before write your own. The
best of the best for a beginner is Verilog HDL by Samir Palnitkar. The book
is very easy to understand and it gives very detail explanation of important
language constructs. This is the only book that clearly explain blocking and
non blocking assignment, along with the mechanism of always and intial
block, and when to define a signal as reg or wire. See if you can write
better book than his!

Hendra

 

[David]

Hello:
Have a look at this book "HDL chip design by Douglas J smith"..
Hendra, whatever you were suggesting is already in this book.
UJMI, in my opinion you are just trying to reinvent the wheel.

myself. Thanx a bunch to my teacher who didnt recommended any other
book, but actually I havent been a real big fan of it either...infect
I dont like any book on the DHD much...all im thinking is a very
simple book which any newbie or intermediate level person can keep on
his/her side with view to be used as a reference book.

That is your prerogative. But my best guess is that you haven't looked
at the course outline.

Hope that will help..

with regards
DAK

 

[Steven Sharp]

bluedoze@yahoo.com (BlueDoze) wrote in message news:<a53ecee3.0406030106.3470b361@posting.google.com>...

sharp@cadence.com (Steven Sharp) wrote in message news:<3a8e124e.0406021525.649c6348@posting.google.com>...

always @(reset or async_set or input1 or input2)
if (reset)
output0 = input1;
else if (async_set)
output0 = input2;




This block should be sensitive to the clk, to take care of the
negative edge of the clock.

The block doesn't need to "take care" of the negative edge of
the clock. The device doesn't do anything on the negative edge
of the clock. If the block is executed because of a change on
the clock, it will execute the exact same way it did the last
time it executed, and assign the exact same value to output0
that it already holds. This has no effect, so there is no need
to execute it. It is just a waste of simulation time.

Yes, the original VHDL would execute these assignments on the
negative edge of the clock. But we don't have to replicate
the execution of the same assignments as the VHDL; we only
have to replicate the resulting output behavior. If the VHDL
executed assignments that had no effect, we don't have to
perform those useless assignments. They were executed in VHDL
because VHDL apparently doesn't provide a way to make a process
sensitive to only one edge of a signal.

If you still disagree, please describe a sequence of input
transitions which would result in a different output value
depending on whether the clock is included in that block's
event control.

 

[Holger Baxmann]

the standard USB-to-IDE or direct
IDE interface way.

I've never seen the VHDL for a device-side IDE interface, but it
shouldn't be too hard to do at least a PIO-mode interface. All you need
to do is respond to reads and writes to two banks of eight registers each
and generate the appropriate actions (maybe just read and write sector
commands). I recommend looking at an early version of the ATA spec
(before they got to several hundred pages) to see how the interface
works. The one I've used is "ATA Interface Reference Manual" published
by Seagate back in 1993 (stored at
http://www1.vobis.de/bbs/firmen/seagate/manual/atarevc.pdf)

Thank you, Dave

I will do my very best, but I need a harddisk either so the alternative is
to be the real 'man-in-the-middle'.

Once you get a design roughed out, you could combine it in an FPGA or
simulator with the IDE interface core we have at www.xess.com. That
would show you if your device-side interface is alive before subjecting
it to a real-world command stream from a PC IDE port.

Hopefully my board is arriving soon, there it could be on CD, does it?

bax
PS: And thanks, Vobis ;-)

 

[Nahum Barnea]

csus01-123@ibadat.edu.pk (malik tj) wrote in message news:<33f63786.0405312139.6aa74d4d@posting.google.com>...

I wanna implement MULTILPIER using BOOTH algorightm...I tried find out
the algo but i couldnot understand the logic for that...Thereofre if
any one has the LOGIC diagram then plz mail me at
(csus01-123@ibadat.edu.pk)

1. http://www.geoffknagge.com/fyp/booth.shtml
2. http://arith.stanford.edu/phds.html download:
Fast Multiplication: Algorithms and Implementation.
Gary W. Bewick, March 1994. (1.8 MB)

Enjoy.

 

[DW]

"Steven Sharp" <sharp@cadence.com> wrote in message
news:3a8e124e.0406041216.68278aeb@posting.google.com...

"DW" <dave_wooff@hotmail.com> wrote in message
news:<c9n7ta$s70$1$830fa79d@news.demon.co.uk>...

Is the following of any help (using Quasi-continuous assignment)? :

always @(reset or async_set)
if (reset)
assign output = input1;
else if (async_set)
assign output = input2;
else
deassign output;

always @(posedge clock)
if (sync_set)
output = input3
else
output = input;

This approach should work for simulation, but still has problems
with synthesis. I think the old Cadence Synergy synthesis tool
handled this particular coding style for asynchronous set and
reset. I don't think other tools accept quasi-continuous assigns.

Its probably a stupid question, but why is it that synthesizers/simulators
appear to be so inconsistent with the interpretation of Verilog - and if a
feature is in the language, why isn't it naturally supported? Is it due to
the changes to Verilog over time i.e. some tools haven't caught up with the
latest standard?

 

[DW]

"Andy" <muellbude@gmx.de> wrote in message
news:9254872c.0406070205.71ed31c1@posting.google.com...

In a top level file I would like to instantiate a module several
times. Each of the implementations can have a different function
depending on a `define in the top level document. That does not work
with synplify 7.1.1, but I would like to keep the module as a single
file.

Example:
------------------------------------
toplevel.v:

...
`define DoImplementation1
module2implement moduleimplementation1 (....);
`undef DoImplementation1

`define DoImplementation2
module2implement moduleimplementation2 (....);
`undef DoImplementation2
...

------------------------------------
module.v:

module module2implement (...);
...
`ifdef DoImplementation1
...Implementation1...
`endif
`ifdef DoImplementation1
...Implementation2...
`endif
...
endmodule
------------------------------------

Parameters can not be used here, because the define decides between
different ram implementation in the submodule. Any suggestions on a
solution or a workaround? Thanks very much in advance...

Andreas

I don't know the complete solution to this problem, but it is of interest to
me also. The first problem here though is that the 'define
DoImplementation1 only has an effect in 1 line of toplevel.v. Module.v is
pre-processed separately. You can only make DoImplementation1 have an
effect in module.v if it is defined in module.v or in an 'include file or
passed in by the compiler.

Given that you know when in toplevel.v to instantiate which "flavour" of
module, why not simply define two different types of module to do the job in
two different ways. I know that in the Altera design tools you can leave
certain choices to the synthesizer like, for instance, which memory block
size to use to implement a RAM. Could you use this approach?

 

[BlueDoze]

sharp@cadence.com (Steven Sharp) wrote in message news:<3a8e124e.0406041248.4c737ef6@posting.google.com>...

bluedoze@yahoo.com (BlueDoze) wrote in message news:<a53ecee3.0406030106.3470b361@posting.google.com>...
sharp@cadence.com (Steven Sharp) wrote in message news:<3a8e124e.0406021525.649c6348@posting.google.com>...

always @(reset or async_set or input1 or input2)
if (reset)
output0 = input1;
else if (async_set)
output0 = input2;




This block should be sensitive to the clk, to take care of the
negative edge of the clock.

The block doesn't need to "take care" of the negative edge of
the clock. The device doesn't do anything on the negative edge
of the clock. If the block is executed because of a change on
the clock, it will execute the exact same way it did the last
time it executed, and assign the exact same value to output0
that it already holds. This has no effect, so there is no need
to execute it. It is just a waste of simulation time.

Yes, the original VHDL would execute these assignments on the
negative edge of the clock. But we don't have to replicate
the execution of the same assignments as the VHDL; we only
have to replicate the resulting output behavior. If the VHDL
executed assignments that had no effect, we don't have to
perform those useless assignments. They were executed in VHDL
because VHDL apparently doesn't provide a way to make a process
sensitive to only one edge of a signal.

If you still disagree, please describe a sequence of input
transitions which would result in a different output value
depending on whether the clock is included in that block's
event control.

You are absolutly right, I agree with you.

Thanks for the answers.

 

[Nahum Barnea]

shihhsin_hu@yahoo.com (Jason Hu) wrote in message news:<6deb0c1b.0405312355.3121000b@posting.google.com>...

SRAM is much smaller than FF.

SRAM has 4 or 6 transistors per bit.
FF usually has 15-20 transistors.


wtx@umem.com (Weng Tianxiang) wrote in message news:<511e4538.0405190726.9399ff7@posting.google.com>...
Hi,
I want to know which has larger IC area, flip-flop and SRAM. Why? and
how many transistors are there for flip-flop or SRAM?

Weng

for example - in xilinx fpga you can configure a slice as a sram with
32 addresses of 1 bit.
If you migrate to asic you probably prefer 32 FF instead of 32x1 sram.

 

[Chris F Clark]

Dave Wooff asked:

Its probably a stupid question, but why is it that synthesizers/simulators
appear to be so inconsistent with the interpretation of Verilog - and if a
feature is in the language, why isn't it naturally supported? Is it due to
the changes to Verilog over time i.e. some tools haven't caught up with the
latest standard?

The answer to your question is that sometimes it *is* due to changes
in Verilog over time. However, especially with regard to
synthesizers, the answer is that Verilog wasn't deigned for synthesis,
only for simulation. Verilog does not describe hardware in hardware
terms, Verilog has statements that can be used to model hardware to
simulate the hardware (and presumably debug the hardware or do
something else with the simulation results, such as determine whether
timing constraints were met or how many items were in fifo queues in
the given simulation).

Now, since a model of hardware presumably matches some specific
hardware, the clever folks who invented synthesis, founds some
algorithms that for certain verilog models can infer what the hardware
being modelled probably is. However, there are models that the
synthesis folks cannot figure out what hardware is being modelled.
Thus, the concept of synthesizable Verilog--that Verilog that the
synthesizer can figure out.

That doesn't mean that non-synthesizable Verilog doesn't have a
perfectly good simulation interpretation, and may even be correspond
to some specific hardware. It's just that the Verilog isn't mappable
by a synthesizer back into that hardware. Thus, the mismatch.

Next, circuit designers are not the only users of Verilog and the
other parts of Verilog that are not synthesizable often play important
roles in validating and verifying that the circuit designed is
correct. In fact, the circuit designer may write Verilog that is not
intended to be snythesized (e.g. assertions) in with the synthesizable
code to facilitate its testing or other uses. Similarly, Verilog
non-code (i.e. comments) may be used to indicate synthesizable
properties that do not effect simulation (e.g. synopsys full_case).
Other annotations, such as sdf, can facilitate other uses of Verilog,
such as for timing analysis. More mismatches due to these effcets.


Hope this helps,
-Chris

*****************************************************************************
Chris Clark Internet : compres@world.std.com
Compiler Resources, Inc. Web Site : http://world.std.com/~compres
23 Bailey Rd voice : (508) 435-5016
Berlin, MA 01503 USA fax : (978) 838-0263 (24 hours)
------------------------------------------------------------------------------

 

[UJMi]

I knew u wouldnt be able to keep ur self out of this thread for long
DAK thanx for the reply anyway!

hiteccat@yahoo.com (David) wrote in message news:<5625df18.0406062311.71e66797@posting.google.com>...

Hello:
Have a look at this book "HDL chip design by Douglas J smith"..
Hendra, whatever you were suggesting is already in this book.
UJMI, in my opinion you are just trying to reinvent the wheel.

myself. Thanx a bunch to my teacher who didnt recommended any other
book, but actually I havent been a real big fan of it either...infect
I dont like any book on the DHD much...all im thinking is a very
simple book which any newbie or intermediate level person can keep on
his/her side with view to be used as a reference book.

That is your prerogative. But my best guess is that you haven't looked
at the course outline.

Hope that will help..

with regards
DAK

 

[glen herrmannsfeldt]

DW wrote:

(snip)

assign a_and_b = a & b;
always @(posedge clk)
c <= a_and_b;

(snip)

always @(posedge clk)
c <= a & b;

I dont see any reason why these 2 codes should not be equivalent.
If you have found it to be otherwise, please elaborate.

Thanks, no I have not found this to be the case.
I was just testing my understanding.

I tend to think of continuous assignment (the assign command)
just like wiring parts together on a circuit board.

I believe it is possible that they will simulate differently,
as they might depend on the order of things that happen on the
same time step, but they should synthesize the same.

-- glen