need a cheap student edition FPGA

[Brian Philofsky]

Kevin Neilson wrote:

"Chris Carlen" <crcarle@BOGUS.sandia.gov> wrote in message
news:cbt2af01rlh@news3.newsguy.com...

Where can I learn about these Verilog 2001 IO commands? Are they
implemented in Modelsim? I have read the documentation a little bit.
I'll have to look in there some more.

Good day!


I don't know if you'll have luck finding help in the Modelsim documentation.
That will tell you what commands are implemented, but not how to use them.
I think the best bet may be to get out a C book and look up 'fscanf' and
'getc' and such. I think the Verilog commands are supposed to operate just
like the C ones. -Kevin

If all you are planning to do is read in binary or hex data from an
external file, I find the $readmemb and $readmemh command much easier to
use. Since they are Verilog95, most simulators support it and the
reading of the data for these commands can be done in a couple of lines
in the testbench without too much thought. The newer Verilog 2001 file
commands take a bit more thought and more typing to get to work but do
give added flexibility, especially if you want to read something other
than binary/hex, need to parse the file, need to write/update the file
or do anything more advanced than simply reading data and storing in an
array. Also, if you are reading in a lot of data, the new commands can
be more memory efficient since you can read in pieces at a time however
doing so can also slow down simulation since every time you go to the
disk to get or write information can stall the simulation from operating
at full speed (similar to going to swap/paging when you run low on
memory). In general though, anytime you read/write to a file, you can
slow down simulation so I generally try to use sparingly.

In terms of ModelSim support, it depends on which version of simulator
you are using. From the original post, it looks like Chris is using
5.7c which I am fairly sure supports most of the Verilog 2001 file I/O
commands. There is is a section in the new 6.2i Language Templates that
also explains the use of these new commands at: Verilog --> Simulation
Constructs --> System Tasks and Functions --> File I/O --> Read/Write to
a File. There should be enough information to get someone started with
this but may take a little trial and error to get fully working the way
you intend to use it (at least that is how it usually works for me).

On a related but slightly off-topic note, Chris mentions that he is
using 5.2i but using 5.7c of ModelSim-XE. If memory serves, 5.7c was
the version of ModelSim-XE designed to be used with 6.1i. It is
important to keep the MTI-XE release in sync with the ISE version used
because MTI-XE comes with pre-compiled libraries for the version of ISE
it is released with. It is possible problems can arise later when
post-translate, post-map or post-par (timing) simulation is performed as
the simulation netlist will be created by 5.2i but the pre-compiled
libraries are for 6.1i if MTI-XE 5.7c is used. Since updates are
periodically necessary in the timing parameters and interfaces to the
models, it is never suggested to mix netlists generated with one version
of ISE with libraries from another.

Good luck,

-- Brian

 

[Sarah Robertson]

Hi, I'm trying to get in touch with Marko about an invisalign post
from a few years ago. I am a freelance reporter working on a story
about orthodonitcs. Marko, if you read this, I'd be interested in
interviewing you. My e-mail is SarahCRobertson@yahoo.com

Thanks so much,
Sarah

 

[Chris Carlen]

Brian Philofsky wrote:

On a related but slightly off-topic note, Chris mentions that he is
using 5.2i but using 5.7c of ModelSim-XE. If memory serves, 5.7c was
the version of ModelSim-XE designed to be used with 6.1i. It is
important to keep the MTI-XE release in sync with the ISE version used
because MTI-XE comes with pre-compiled libraries for the version of ISE
it is released with. It is possible problems can arise later when
post-translate, post-map or post-par (timing) simulation is performed as
the simulation netlist will be created by 5.2i but the pre-compiled
libraries are for 6.1i if MTI-XE 5.7c is used. Since updates are
periodically necessary in the timing parameters and interfaces to the
models, it is never suggested to mix netlists generated with one version
of ISE with libraries from another.

Maybe that's why I can't seem to do a post-timing simulation. But I
haven't needed to yet since I'm only doing CPLD stuff at relatively slow
clock rates. I had terrible problems with 6.1i, so I downgraded.

Thanks for the input.


Good day!


--
____________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarle@sandia.gov

 

[B. Joshua Rosen]

On Tue, 06 Jul 2004 20:48:58 +0000, A wrote:

Does anyone know of a good low cost (free or less than $50) text editor
(native Windoze executable) that can be used with Verilog? I have looked at:
(1) EditPlus (errors with {} in a PERL program; no BEGIN/END support)
(2) NEdit (not native windows; no BEGIN/END support)
(3) e93 (based on Tcl/Tk 8.4 from Active State; no BEGIN/END support)
(4) jEdit (Java is slow and awkward; no BEGIN/END support)
(5) TextPad (no BEGIN/END support)

But none of these will deal with BEGIN/END syntax (i.e., {} blocks are good
for "C", PERL, etc., but not for Verilog).

Any suggestions?

Thanks,
EigenFunctionsNOSPAM@YahooNOSPAM.com

Xemacs has Verilog and VHDL modes that do every thing you want. Get it
from http://www.xemacs.org.

 

[Chenbo Liu]

Ultraedit with verilog wordfile and gvim are your choices.

Personally I'm in favour of gvim coz it's free.


Best,

Chenbo

"A" <A@B.com> 写入邮件 news:_eEGc.29756$MT5.1007@nwrdny01.gnilink.net...
: Does anyone know of a good low cost (free or less than $50) text editor
: (native Windoze executable) that can be used with Verilog? I have looked
at:
: (1) EditPlus (errors with {} in a PERL program; no BEGIN/END support)
: (2) NEdit (not native windows; no BEGIN/END support)
: (3) e93 (based on Tcl/Tk 8.4 from Active State; no BEGIN/END support)
: (4) jEdit (Java is slow and awkward; no BEGIN/END support)
: (5) TextPad (no BEGIN/END support)
:
: But none of these will deal with BEGIN/END syntax (i.e., {} blocks are
good
: for "C", PERL, etc., but not for Verilog).
:
: Any suggestions?
:
: Thanks,
: EigenFunctionsNOSPAM@YahooNOSPAM.com
:
:

 

[Stephen Williams]

ABW wrote:

"Stephen Williams" <spamtrap@icarus.com> wrote in message
news:491e2$40edb595$40695902$2628@msgid.meganewsservers.com...

I'm one of those compiler writers who had a run in with the syntax,
but unlike some other things in Verilog, it is not ambiguous. I had
to detect "(*)" in the lexical analyzer, and if matched, convert it
to a single '*' token. This prevents "(*" from being interpreted as
the start-of-attribute token. It's a little quirky, but not difficult.


Unfortunately it is ambiguous. Since it is not literally defined as a single
token it can and is treated differently by different tools.
Some tools allow @ ( * ) but complain on @ ( /*Alice has */ * /*a cat*/ )
which suggests that they treat whole sequence ( * ) including optional
whitespace as one token. Other tools can deal with whitespace, comments,
macros etc. between (, * and ) which suggests they deal with it on the
syntax level - (, * and ) are separate tokens and (* and *) attribute tokens
are treated in the grammar as a valid replacement for pairs of tokens ( with
* and * with ) accordingly.

Actually, the description in the standard is ambiguous, but I
believe the intent is clear, and not hard to cope with. The
parser needs to support '@' '*' as well as '@' '(' '*' ')' and
with the simple lexor trick above, combined with a reasonable
parser, all is well. If a tool has a problem with your example,
then that tool, in my humble opinion, deserves a bug report.

The problem is describing in the standard, unambiguously, a
syntax that in itself is simple and unambiguous. I've got it
licked with 2 extra lines of code.

Your further rant about lexical quirkiness of the language in
other aspects is granted knowingly:-/

--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."

 

[Stephen Williams]

Pablo Bleyer Kocik wrote:

Hello people.

I will be maintaining recent snapshots of the Icarus Verilog compiler
for the Windows platform in easy to use installers at
http://armoid.com/icarus/. I have been doing this for more than a year
now for the people in my company so I thought, what the heck, for the
same effort I can benefit other users out there.

If you have other free related goodies that can be posted there
--like Verilog test files, utility scripts, etc.-- please email me at
mailtobleyer2004N@SPAMembedded.cl [N@SPAM->@]

Thanks for Stephen Williams for putting together such a nice Verilog
compiler for the community.

Regards.

I should add that Pablo has been sending me copies of his installer
that I keep in the "precompiled" directory where snapshots are
normally found. I should have a link to his site as well, unless
I forgot.

I still haven't booted Windows recently enough to try his installer
(lucky me!) so ride reports to comp.lang.verilog are welcome.

--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."

 

[Jason Zheng]

Pablo Bleyer Kocik wrote:

Hello people.

I will be maintaining recent snapshots of the Icarus Verilog compiler
for the Windows platform in easy to use installers at
http://armoid.com/icarus/. I have been doing this for more than a year
now for the people in my company so I thought, what the heck, for the
same effort I can benefit other users out there.

If you have other free related goodies that can be posted there
--like Verilog test files, utility scripts, etc.-- please email me at
mailtobleyer2004N@SPAMembedded.cl [N@SPAM->@]

Thanks for Stephen Williams for putting together such a nice Verilog
compiler for the community.

Regards.

--
PabloBleyerKocik /"...I didn't want to be kissing Kevin Spacey.
pbleyer2004 / Come on! Lying there naked with rose petals?"
@embedded.cl /- Kirsten Dunst on turning down American Beauty

How does the icarus compiler compare with the commercial ones, e.g.
modelsim, ncverilog, etc.?

 

[Swapnajit Mittra]

"botao" <blee@qualcomm.com> wrote in message news:<cch877$n40$1@fair.qualcomm.com>...

Have a tough problem ...

I need to compare 2 components with the same interface, one component is
implemented in VHDL, the other is in Verilog.
I compiled (using modelsim if it matters) the VHDL one into VHDL_LIB, and
the Verilog one into VERILOG_LIB, then I am planning to code up a top level
testbench in Verilog, something like

comp u_vhdl (clk, ...); // want to use the comp in VHDL_LIB
comp u_verilog (clk, ...); // want to use the comp in VERILOG_LIB


how do I exactly do this in Verilog? I know in VHDL one can do this as

u_vhdl: ENTITY VHDL_LIB.comp ...

but I have to use Verilog this time.

thanks,

---Lee

If you have a logic equivalency checker (Verplex Tuxedo, Cadence
Chrysalis etc.), read in both the modules and do an equivalency
check. This is the *only* practical way to make sure they are
100% equivalent for two real life designs.

- Swapnajit.
--
Project VeriPage::: http://www.project-veripage.com

 

[Triste]

Just an Illusion <illusion_to_net@yahoo.fr> wrote in message news:<40ED4764.2090900@yahoo.fr>...

Hi Triste,

You have certainly some other features, but one of the first is
certainly a problem of clock race.
In case of cascaded divide-by-2, your output clock signal take each time
some little transmission delay; above a certain limit the output clock
is no more synchronized with input one.
With the single long divider (based on counter I think) you can reduce
this clock slide. And it is certainly more simple to resynchronize the
out clock.

JaI

Hi JaI, thanks for the comments.

Actually my question is, to derive 1 Hz from 32.768 KHz, is there any
difference between using cascading D-type flip flops built with
primitive gates and using divide-by-n counter (software-like) in terms
of synthesis?

Thank you in advance for any input.

 

[botao]

"ALuPin" <ALuPin@web.de> wrote in message
news:b8a9a7b0.0407080623.57e0d6b1@posting.google.com...

I believe that if you use Verilog 2001 configurations, ModelSim
supports referencing components from both Verilog and VHDL libraries.

As far as you do not use OEM versions of Modelsim ... isn't it?

I do have the full featured version ... Not using Verilog 2001 yet, can you
guys poing me to any webpage which explains the configuration thing?

---Lee

 

[Cody]

nope...i have never seen any open source codes for RC4.

Kelvin



"ERJS" <erjs@hotmail.com> wrote in message
news:30714d8d.0406281948.588aa664@posting.google.com...
> does someone have a verilog code for RC4?

 

[Swapnajit Mittra]

Howard Le <leh@alum.rpi.edu> wrote in message news:<GK8Kc.15574$Kz3.1260665@news4.srv.hcvlny.cv.net>...

Hi,
Would anyone know of a verilog simulator ported on pocketpc?
Thanks,
Howard

Given the memory size of a pocketPC type device, it
is hard to foresee its usefulness as a simulation
machine, don't you think?

- Swapnajit.
--
SystemVerilog, Verilog, PLI and all the good stuffs
Project VeriPage::: http://www.project-veripage.com

 

[Jason Zheng]

glen herrmannsfeldt wrote:

DW wrote:

Hi,
suppose I have two events which can occur and I want to control a common
register which depends on the event ordering, (so a single always
block is
used). How can I decode the two events after they have occurred, so I
know
which course of action to take. I have considered using two always
blocks
but I'm not sure whether or not this would lead to unexpected behaviour.


Assuming you are planning to synthesize this, consider some
what kind of logic you expect it to synthesize.

always @(negedge a)

likely synthesizes an edge triggered D type FF.

what does always @(negedge a or negedge b)

synthesize? Two DFF's? One DFF with an or gate on its input?

-- glen

No, it's a DFF with asynchronous reset

 

[Hans]

The solution is simple, just call the annotate from the test module as in:

module test;
wire w;
block b1 ();
annotate annotate();
endmodule


No were is that beginners guide to verilog.....

Hans.

"Hans" <hansydelm@no-spam-ntlworld.com> wrote in message
news:ezpNc.186$ld7.154@newsfe6-gui.ntli.net...
Hi,

Can anybody tell me how to instantiate a verilog netlist + annotate
module
(defparam) in a VHDL testbench?

I have created a simple testcase:

-- VHDL TestBench instantiating Verilog Module
use ieee.std_logic_1164.all;
entity tb is
end tb;
architecture arch of tb is
component test
end component;
begin
uut: test;
end arch;

-- Verilog Module and Annotate Module
module test;
wire w;
block b1 ();
endmodule

module block;
parameter p=1;
endmodule

module annotate;
defparam test.b1.p=2; // works for Verilog only
//defparam tb.uut.test.b1.p=2; //fails
//defparam /tb/uut.test.b1.p=2; //fails
//defparam /tb/uut/test.b1.p=2; //fails
endmodule


If I just load the verilog module it works fine (using Modelsim):

vlog test.v
vsim -c test annotate
examine sim:/test/b1/p -> p=2!

Instantiating the Verilog test module in a VHDL testbench is no problem,
however, how to update the parameter 'p'?

If I use:

vlog test.v
vcom tb.vhd
vsim -c tb annotate

I get: * Error: (vsim-3043) test.v(12): Unresolved reference to 'test'
in
test.b1.p.


I then tried several defparam permutations all without any luck. If you
take
out the annotate module the simulation runs fine but with p=1.

I suspect that you can not reference a parameter through a VHDL entity
but
I
just want to make sure that is the case,

Thanks,
Hans.

 

[Jason Zheng]

Steven Sharp wrote:

Jason Zheng <jzheng@jpl.nasa.gov> wrote in message news:<celuoh$lqk$1@nntp1.jpl.nasa.gov>...

Is there a quick way to express that we want certain bits of an
expression but not all of them?

e.g., I want the last 2 bits of A[1:0] + 1

Or do I have to declare another wire and assign the result to it?


There is no way to part-select the result of an expression. A
part-select can only be applied to an object, such as a wire,
reg or parameter. This is partly because the range from the
declaration is needed in order to determine what bits a particular
index value refers to.
negative, try this:

reg [3:1] a;
reg [6:4] b;
wire [3:0] c;

assign c[3:0] <= a[3:1] + b[6:4].

It's perfectly legitimate, however the final result is just a 4 bit
value, regardless of the range definition of a and b. What really
matters is what you assign that value to.

 

[Andy]

Best way would be to use a CPU model for writing and reading your PLD.
Another possibility would be to set up a write and a read task and
define the CPU access timing yourself:

(CS,WR,RD, Data, Address are the stimulus signals)

//--- WRITE To FPGA/CPLD--------------------------------
task CPUwrite;
input [10:0] Addr;
input [15:0] D;
begin #(10) CS = 0;
Address = Addr;
#(10) WR = 0;
#(10) force Data = D;
#(10) WR = 1;
#(10) CS = 1;
Address = 11'hZZZ;
release Data;
end endtask

//--- READ From FPGA/CPLD --------------------------------
task CPUread;
input [10:0] Addr;
begin #(10) CS = 0;
Address = Addr;
#(10) RD = 0;
#(10) RD = 1;
CS = 1;
#(10) Address = 11'hZZZ;
#(10) ;
end endtask

Now call the tasks as often you like in your testbench by using:

CPUwrite (Addr, D);
CPUread (Addr);

Regards,
Andy



thopman@uoguelph.ca (Theo Hopman) wrote in message news:<ad6737ea.0408091803.7add8125@posting.google.com>...

Hi all. I'm learning (or trying to learn!) Verilog as part of a
project I'm working on. The project requires a CPLD (Xilinx XC9500
series, FWIW), and I figure I may as well take the opportunity to
learn a language with broader applicability than Abel, which I've used
in the past.

My problem is this: The CPLD is going to be a peripheral on a 16-bit
data bus, with standard control bus signals (i.e., RD\ and WR\ and a
CS\). For now, let's assume it's a very small memory: it should store
the data on the data bus when WR\ is asserted, and put the stored data
on the data bus when RD\ is asserted, and be tristated otherwise. I
think I've got a module which does this, but I need to test it, and
that's where the heart of the problem is. I'm not sure how to set up a
testbench to verify that my "memory" module is working the way it
should. Ideally, the testbench should write a sequence of data to the
"memory" and read it back for verification, but I must be running into
some kind of mental block here. I've got the data bus set up as
'inout', but ModelSim (XE II Starter) complains if I try to assign a
value to it, which makes it a bit difficult to do writes .

I would be most grateful for a small (even 1 bit wide) example of a
memory, with a testbench to verify writes and reads.

Thanks in advance!

THeo

 

[john jakson]

Jim Lewis <Jim@SynthWorks.com> wrote in message news:<10hi4hg3qre558e@corp.supernews.com>...
snipping

Verilog is dominant in the US ASIC market.


VHDL is dominant in the US FPGA market.
VHDL owns the US defense sector.
VHDL is dominant in all markets outside of US.
Good thing for VHDL that FPGAs are taking over .

While all the above maybe true ( I'd dispute some but heck), things
are not as bleak for Verilog as you might be suggesting.

A trip to any DAC show paints a different picture.

While FPGAs design starts are indeed taking over, guess what, the
projects are getting quite large, nothing like the look of old time
FPGA 1 person projects.

What happens to all the Verilog experts out there in the ASIC market
who aren't doing much ASIC design anymore?

They turn to FPGA design and bring their favourite tools, languages,
prejudices, flows with them. It would be wishfull thinking to assume
that they will dump their fav language and just become VHDL users when
they likely will also determine the tool chain. Theres more to it than
language preference, it also has to do with what other tools available
to do the job.

Remember very high end design doesn't get done with free tools, ASIC
guys are used to spending something for that. Note Synplify and other
FPGA EDA vendors will move to the middle ground for both ASIC & FPGA
work.

One should also bear in mind despite what Xilinx says, that high vol
FPGAs will get turned into ASICs and its back to Verilog again for
verification.

I expect most of the FPGA projects I will work on will continue to be
Verilog/C.

One other tiny advantage. Despite what people say about the C like
syntax, it really only applies to expression syntax where the
precedence rules & operators are very similar. Since most of the code
that needs to be written is mostly expressions of the always or assign
type nested within non C block structure, it helps me alot that
similar models can be written in C and translated line for line into
Verilog. Indeed some C code can be literally processed into Verilog
with some effort upfront, but thats not to say C is a HDL, it isn't.

Indeed one could also use Verilog/VHDL/Confluence/C <->xxx translation
and etc too.

my 2c

regards

johnjakson_usa_com

 

[Jonathan Bromley]

On Wed, 11 Aug 2004 13:29:41 +0300, Weaam Attallah
<weaam_attallah@mentor.com> wrote:

Is there anything in verilog that supports inertial delays.
if a pulse width is less than the inertial delay stated , it is
neglected.
The only case when the it senes transition when the pulse is greater
than the delay specified.

Continuous assignment to a net provides inertial delay.
You can affect the delay value in various different ways.

(1) Net delay
~~~~~~~~~~~~~
wire #5 W;

The value seen on wire W will update 5 time units after a
change on the output of its driver (or drivers, since it's
OK to have multiple drivers on a wire).

(2) Driver delay
~~~~~~~~~~~~~~~~
assign #3 W = ~a;

The driver's output updates 3 time units after a change in the
right-hand-side expression. This can, if you wish, be combined
with net delay. Since I have a delay of #5 on wire W, the
total delay from A to W is now #8: when A changes, the driver
updates #3 later; but the value seen on net W doesn't update
for yet another #5.

(3) Primitive delay
~~~~~~~~~~~~~~~~~~~
not #4(W, B);

Gate primitives can be given a propagation delay.
The inverter's output updates 4 time units after a change on B.
Consequently, the value seen on W will update #9 after a change
on B.

(4) Wire assignment
~~~~~~~~~~~~~~~~~~~
wire #7 Y = B;

Equivalent to
wire Y;
assign #7 Y = B;

(5) Specify blocks
~~~~~~~~~~~~~~~~~~
You can also do complicated things with propagation delays
through a module by creating a specify block. There are
features for controlling pulse rejection independently of
the delay, and lots of other good stuff. Look in the LRM,
or ask a gate-level Verilog guru.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Jason Zheng]

Jason Zheng wrote:

Anyone know how to use $shm_probe for ncverilog?
I tried this:

initial begin
$shm_open("waves.shm");
$shem_probe("AS");
end

After the simulation, I used signalscan to look at the waveforms, but i
could only see the module names, no signals. Any clue why that happened?

thanks
nm, I figured it out. It turns out that you have to use +access+r option

with ncverilog