I hate VHDL!!!

[Jonathan Bromley]

On 26 Aug 2004 05:24:19 -0700, patrick.melet@dmradiocom.fr
(Patrick) wrote:

I've to read a signal (data rate : 4Mbps) and his clock (4MHz) with a
sampling clock of 88 MHz.

But when I visualize these signals they are not synchronous !!

I use this code :

[snip]

If you are using an oversampling clock, why is it
appropriate to resynchronise your input data to
the input clock before sampling it?

Please describe:
- the timing specification of the input data and clock,
- what you are trying to achieve
and we will try to help.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Mike Treseler]

Jonathan Bromley wrote:

On 26 Aug 2004 04:48:49 -0700, niko@mtl.t.u-tokyo.ac.jp
(Niko D. Barli) wrote:

I am trying to use VHDL's RAND function in my test benches.
In Synopsys VCS the function is defined in IEEE.math_real.
However, I couldn't find it in Modelsim 5.7c. Is the function
defined in other package ? Or, is it because Modelsim doesn't
support random generation ?

No, it's because there is no RAND function in the standard
IEEE.math_real package. I guess it was invented by
Synopsys for users' convenience.

Here's a math_real compatible source to look at:
http://tech-www.informatik.uni-hamburg.de/vhdl/packages/P1076.2/mathpack.vhd

-- Mike Treseler

 

[Pieter Hulshoff]

ALuPin wrote:

I have written some little code for a FIFO and I want
to know whether the signals "l_fifo_full" / "l_fifo_empty" are
correct generated.

If I understand your code correctly, then I'd say: no. From what I
understand you have a FIFO with one clock, and a read/write enable. You use
the FIFO as an elastic store, running the read/write addresses from 0 to
ROW-1, and round.

Ok, before I dive into your code: please, please, please, please don't use
asynchronous resets. Ok, now that I got that off my chest I can comment on
your code without hurting myself.

process(Reset, Clk)
begin
snip
if (l_fifo_full='1')) then
l_write_pointer <= 0;
end if;

Ok, I don't understand why you'd want to put your write pointer to 0 when
your fifo is full. Do you just want a reset situation whenever your fifo is
full? Or do you want to do this when you cause an overflow, which would
mean writing into the FIFO when it is full. In that case it should be moved
inside the write if.

process(Reset, Clk)
begin
snip
if (l_fifo_full='1')) then
l_read_pointer <= 0;
end if;

Something similar here, though I'd expect you to reset the FIFO if you try
to read from an empty FIFO. In this case you should be checking for empty,
and place it within the read if construction.

process(Reset, Clk)
begin
snip
elsif rising_edge(Clk) then
l_fifo_full <= next_l_fifo_full;
l_fifo_empty <= next_l_fifo_empty;

Why do you wish to delay these indications for 1 clock cycle? Wouldn't you
want to use this information as soon as it is available? The next signals
are already clocked as far as I could see.

process(l_fifo_full, l_fifo_empty, l_wp_turn_around, l_write_pointer,
l_read_pointer, l_rp_reg)
begin
snip
if ((l_wp_turn_around='1') and (l_write_pointer=l_read_pointer) and
(l_read_pointer=l_rp_reg)) then
next_l_fifo_full <= '1';
end if;

You define the FIFO as full if you have a wrap around (why is this a
prerequisite?), your write pointer equals your read pointer, and you didn't
do a read action this time. What if you didn't have a read action nor a
write action? It could be that the FIFO was and still is empty?

if ((l_read_pointer=l_write_pointer) and (l_read_pointer>0)) then
next_l_fifo_empty <= '1';
end if;

Why would the read pointer have to be > 0?

process(Reset, Clk)
begin
snip
elsif (Erase='1') then
l_wp_turn_around <= '0';
end if;

This is the first time I see the erase used. Wouldn't you want to reset the
read and write pointers at such a time as well?

Regards,

Pieter Hulshoff

 

[Mike Treseler]

ALuPin wrote:

I have written some little code for a FIFO and I want
to know whether the signals "l_fifo_full" / "l_fifo_empty" are
correct generated.
I would appreciate your opinion.

It's not a matter of opinion,
it's a matter of simulation.
Consider writing a testbench, and your
question will be answered.

-- Mike Treseler

 

[Kai Harrekilde-Petersen]

Mike Treseler <mike_treseler@comcast.net> writes:

Jonathan Bromley wrote:

On 26 Aug 2004 04:48:49 -0700, niko@mtl.t.u-tokyo.ac.jp
(Niko D. Barli) wrote:

I am trying to use VHDL's RAND function in my test benches.
In Synopsys VCS the function is defined in IEEE.math_real.
However, I couldn't find it in Modelsim 5.7c. Is the function
defined in other package ? Or, is it because Modelsim doesn't
support random generation ?

No, it's because there is no RAND function in the standard
IEEE.math_real package. I guess it was invented by
Synopsys for users' convenience.

Here's a math_real compatible source to look at:
http://tech-www.informatik.uni-hamburg.de/vhdl/packages/P1076.2/mathpack.vhd

You should always, I repeat, *ALWAYS* implement your own random number
generator functions.

Why? Because then you are able to control which exact random sequence
across platform, OS, libc, tools, date, time, phase of the moon, etc.
Part of this is to remember to ensure that the order that you pick
elements out of a hash (in Perl) are the same every time.

Having the pattern generator run at 23:50 and the pattern checker at
00:05 (because the simulation took 15 minutes) and therefore having
the check fail because you just relied on the output of the date for
the two separate commands is another nice gotcha.

We don't _want_ true randomness. We want something this >< close to
real randomness, but which we can reproduce at our whim, regardless of
where and when we encountered the problem originally.


Kai
--
Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>

 

[Kai Harrekilde-Petersen]

Mike Treseler <mike_treseler@comcast.net> writes:

Jonathan Bromley wrote:

On 26 Aug 2004 04:48:49 -0700, niko@mtl.t.u-tokyo.ac.jp
(Niko D. Barli) wrote:

I am trying to use VHDL's RAND function in my test benches.
In Synopsys VCS the function is defined in IEEE.math_real.
However, I couldn't find it in Modelsim 5.7c. Is the function
defined in other package ? Or, is it because Modelsim doesn't
support random generation ?

No, it's because there is no RAND function in the standard
IEEE.math_real package. I guess it was invented by
Synopsys for users' convenience.

Here's a math_real compatible source to look at:
http://tech-www.informatik.uni-hamburg.de/vhdl/packages/P1076.2/mathpack.vhd

You should always, I repeat, *ALWAYS* implement your own random number
generator functions.

Why? Because then you are able to control which exact random sequence
across platform, OS, libc, tools, date, time, phase of the moon, etc.
Part of this is to remember to ensure that the order that you pick
elements out of a hash (in Perl) are the same every time.

Having the pattern generator run at 23:50 and the pattern checker at
00:05 (because the simulation took 15 minutes) and therefore having
the check fail because you just relied on the output of the date for
the two separate commands is another nice gotcha.

We don't _want_ true randomness. We want something this >< close to
real randomness, but which we can reproduce at our whim, regardless of
where and when we encountered the problem originally.


Kai
--
Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>

 

[Kai Harrekilde-Petersen]

Mike Treseler <mike_treseler@comcast.net> writes:

Jonathan Bromley wrote:

On 26 Aug 2004 04:48:49 -0700, niko@mtl.t.u-tokyo.ac.jp
(Niko D. Barli) wrote:

I am trying to use VHDL's RAND function in my test benches.
In Synopsys VCS the function is defined in IEEE.math_real.
However, I couldn't find it in Modelsim 5.7c. Is the function
defined in other package ? Or, is it because Modelsim doesn't
support random generation ?

No, it's because there is no RAND function in the standard
IEEE.math_real package. I guess it was invented by
Synopsys for users' convenience.

Here's a math_real compatible source to look at:
http://tech-www.informatik.uni-hamburg.de/vhdl/packages/P1076.2/mathpack.vhd

You should always, I repeat, *ALWAYS* implement your own random number
generator functions.

Why? Because then you are able to control which exact random sequence
across platform, OS, libc, tools, date, time, phase of the moon, etc.
Part of this is to remember to ensure that the order that you pick
elements out of a hash (in Perl) are the same every time.

Having the pattern generator run at 23:50 and the pattern checker at
00:05 (because the simulation took 15 minutes) and therefore having
the check fail because you just relied on the output of the date for
the two separate commands is another nice gotcha.

We don't _want_ true randomness. We want something this >< close to
real randomness, but which we can reproduce at our whim, regardless of
where and when we encountered the problem originally.


Kai
--
Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>

 

[ivailokroumov]

Hi ALuPin, I saw your code and i guess that its can be writen more compact.
I'm not sure that your logic is totaly corectly. Do you really to specify
RESET in different process? If you'd put this signal in sample process and
make code more readable you will fine the answer of your question. My
opinion is that these signals are incorrectly defined. I can't understand
what actually you do when comein ERASE comand. Would you tell me, what is
going to happen if your FIFO is half fill in and ERASE going to be "1"?
Are you going to erase all cells of your FIFO.?
On the end rearange your cade and do it more readable and simple. But
) I'm agree withMike Treseler, going to simulate and you will see youg
correctnes ir incorrectness
Best Regards:
Ivaylo Krumov

 

[Lukasz Salwinski]

Jonathan Bromley wrote:

On Thu, 26 Aug 2004 11:05:18 +0200, Niels Bakker
Niels.Bakker@zonnet.nl> wrote:


LFSRs are used to create pseudo random sequences.


But be careful...

LFSRs are quite good for creating random streams of
*bits*. They are rubbish for creating random
streams of *numbers*, because the LFSR register
value is highly correlated from one sample to the
next. If you want a new random *number* from an
LFSR, you must clock it as many times as there
are bits in your desired number.

well... If you search hard enough you'll actually
find a variation on the theme that actually
generates uniform distribution of *numbers*

lukasz

 

[Marcus Harnisch]

Hi Andre,

Don't get me wrong, but if you are trying to decypher the waves at the
SDRAM interface it would help if you'd know about some of the basics
of DDR SDRAMs. The "usual suspects" (Micron, Samsung, etc.) provide
good datasheets for download. JEDEC79x (x >= C) might be a little
dry but is certainly the most comprehensive source of information in
that respect.

Good luck,
Marcus

 

[Jonathan Bromley]

On 27 Aug 2004 03:24:25 -0700, ALuPin@web.de (ALuPin) wrote:

What library do I need to declare the following signal:

constant L: integer:=log2(N); --ceiling log2(N)

Sadly, that one is missing... but this will work
in both synthesis and simulation:


package usefuls is
--- find minimum number of bits required to
--- represent N as an unsigned binary number
---
function log2_ceil(N: natural) return positive;
end;

package body usefuls is
--- find minimum number of bits required to
--- represent N as an unsigned binary number
---
function log2_ceil(N: natural) return positive is
begin
if N < 2 then
return 1;
else
return 1 + log2_ceil(N/2);
end if;
end;
end;

Converting my tail-recursive function into
an iterative implementation is left as an exercise
for the student
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Marcus Harnisch]

Umm, might not be that obvious, but how about checking out
http://www.jedec.org/ ?

-- Marcus

 

[valentin tihomirov]

Here is code I've written about a year ago. It looks much simpler.

entity FIFO_CELL is
generic (
WIDTH : Integer := 8
);
port (
CLK : in std_logic;
RST : in std_logic;
EN : in std_logic;
Write: in std_logic; -- Writing puse from provider
Ack: out std_logic; -- signal to provider on Write, '1' set when not Avail
Read: in std_logic; -- Cleaning pulse from consumer
Avail: out std_logic; -- not full flag
DIN: in std_logic_vector(WIDTH-1 downto 0);
DOUT: out std_logic_vector(WIDTH-1 downto 0)
);
end FIFO_CELL;


-- signal passes through the cell if next cell in the chain is empty
architecture ADVANCED of FIFO_CELL is
--signal AvailReg: std_logic;
signal Data: std_logic_vector(WIDTH-1 downto 0);
signal Empty, Cleaning: std_logic;
begin

Cleaning <= Empty or Read; -- empty next cycle

CLOCK : process(Clk, RST)
begin

if RST = '1' then
Empty <= '1';
elsif Rising_Edge(Clk) and EN = '1' then

Empty <= ((not Write) and Cleaning) or (Empty and Read);

if Cleaning = '1' then
Data <= DIN;
end if;

end if; -- CLK

end process;

Ack <= Write and Cleaning;
Avail <= not Empty or Write;
DOUT <= DIN when (Write and Empty) = '1' else Data;


end ADVANCED;






--cascade FIFO_CELLs into a n-DEPTH chain.
-- data consumed from the first cell and written into the first free cell.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FIFO is
generic (
WIDTH : Integer := 8;
DEPTH : Integer := 4
);
port (
CLK : in std_logic;
RST : in std_logic;
EN : in std_logic;
Write: in std_logic; -- Writeing puse
Ack: out std_logic; -- '1' set on Write (if not Avail), Readed on accept
Read: in std_logic; -- Cleaning pulse
Avail: out std_logic; -- flag
DIN: in std_logic_vector(WIDTH-1 downto 0);
DOUT: out std_logic_vector(WIDTH-1 downto 0)
);
end FIFO;


architecture RTL of FIFO is
type TARRAY is array (0 to DEPTH) of std_logic_vector (WIDTH-1 downto 0);
signal WR : STD_LOGIC_VECTOR(0 to DEPTH);
signal RD : STD_LOGIC_VECTOR(0 to DEPTH);
signal DATA : TARRAY;
begin

VECTOR: for I in 0 to DEPTH-1 generate

FIFO_CELL : entity work.FIFO_CELL(ADVANCED)
generic map (
WIDTH => WIDTH
)
port map (
Clk => Clk,
RST => RST,
EN => EN,
Write => WR(I),
Ack => RD(I),
Read => RD(I+1),
Avail => WR(I+1),

--todo: replace this
DIN => DATA(I),
DOUT => DATA(I+1)
);

end generate;

WR(0) <= Write;
Ack <= RD(0);
Avail <= WR(DEPTH);
RD(DEPTH) <= Read;
Data(0) <= DIN;
DOUT <= Data(DEPTH);

end RTL;

 

[David Bishop]

This code is from the proposed floating point packages.

-- Integer version of the "log2" command
-- Synthisable
function log2(A : natural) return natural is
begin
for I in 1 to 30 loop -- Works for up to 32 bit integers
if(2**I > A) then return(I-1);
end if;
end loop;
return(30);
end function log2;

ALuPin wrote:

What library do I need to declare the following signal:

constant L: integer:=log2(N); --ceiling log2(N)


Thank you for your help.

Kind regards

--
NAME: David W. Bishop INTERNET: dbishop@vhdl.org

 

[Mike Treseler]

M.A.Khader wrote:

I prefer moore fsm in designing any state machine for synchornous
circuits. But I wonder where could be the use of asychronous mealy
outputs in a digital system.Is it only for asynchronous systems or
any where in synchronous sytems.

Once all inputs and outputs are synchronized,
there is not much difference between the two.

-- Mike Treseler

 

[Allan Herriman]

On 30 Aug 2004 17:13:14 -0700, dupont00@hotmail.com (Louis Dupont)
wrote:

Hi!

I'd like to instantiate a component with generic parameters within a
test bench. I would like one of the generic pameters to be defined
within a file. Unfortunately, I can't declare a variable within a
generate statement and I can't declare it as a signal neither. And I
can't instantiate a component within a process statement. Any thoughts
about it can be done? Thanks

The "generic parameters" must be known at elaboration time. This
happens before you can perform file I/O. Therefore this can't be done
directly in VHDL.

There are probably many ways to work around your problem though, one
of which would be using a scripting language to read the file and
write some VHDL (with the generic values read from the file). This
VHDL would then be compiled, elaborated and run (possibly by the same
script).

Regards,
Allan

 

[Mike Treseler]

Louis Dupont wrote:

Hi!

I'd like to instantiate a component with generic parameters within a
test bench. I would like one of the generic pameters to be defined
within a file.

A package body containing deferred constants could be
stored in a file.

Or a script file could supply the constants
via a command line option to the sim or synth program.

-- Mike Treseler

 

[Ken Smith]

In article <865ab498.0408301428.e2f0a12@posting.google.com>,
Mike Treseler <mike_treseler@comcast.net> wrote:
[...]

Quartus is probably concerned about

l_data <= l_data;

because this statement doesn't do anything.

Actually it does seem to do something in Quartus and Quartus seems to like
it just fine. Quartus takes it to mean that l_data keeps its value
through here.

--
--
kensmith@rahul.net forging knowledge

 

[Michael]

Dave,

When do you think the VHDL-200X effort will be finalized? Are we going
to have a VHDL 2004 standard? 2005?

Just curious

David Bishop wrote:

This code is from the proposed floating point packages.

-- Integer version of the "log2" command
-- Synthisable
function log2(A : natural) return natural is
begin
for I in 1 to 30 loop -- Works for up to 32 bit integers
if(2**I > A) then return(I-1);
end if;
end loop;
return(30);
end function log2;

ALuPin wrote:

What library do I need to declare the following signal:

constant L: integer:=log2(N); --ceiling log2(N)


Thank you for your help.

Kind regards

 

[anupam]

Hi Rajan,
Pl add the "sel" in sensitivity list and assign the value to
out_5,....,out_8 at sel = '1' and value to out_1,....,out_4 at sel = '0'