I hate VHDL!!!

[Just an Illusion]

Hi Weng,

Weng Tianxiang wrote:

snip
No any langauge I have known in the world uses keywords that contain
'_'. I really don't know why you want ot invent new wheels. process(*)
is introduced by Verilog, it is a very good idea!


*joke* So you know a very small of them ;-) *end of joke*

For your information ansi C have reserved keyword with '_', they are
macro as __DATE__, __TIME__, __FILE__, __LINE__, __STDC__ and specific
function as __stdcall, __inline, etc.
You have Verilog with some compiler directive and PLI functions.
In VHDL throught use of VITAL library (ieee 1076.4)

You ceratinly can find some other examples, but the three languages are
the must common used be us.

Weng


JaI

 

[Just an Illusion]

Hi Wallclimber,

Wallclimber wrote:

Take codes:

NotLatch : process (g)
begin
if (g='1') then
q<=d;
end if;
end process;

IsLatch : process (*)
begin
if (g='1') then
q<=d;
end if;
end process;

The both are similar, but according to section 12.6 of the lrm, the
first process is a flip-flop and the second (according to verilog
sensitivity notation) must be a d-latch.



You either have a very creative way of reading the specification or
you're reading a different document. Section 12.6 is called "Execution
of a model". Except for some instance names in code examples in the
first 22 pages, the LRM doesn't even use the word 'latch'.


You are right, okay I change my words:

First is a register that is wake up by any event on 'g' that make change
it's value from 1 to another (that is not 1), that is a 'flip-flop'
Second is a register that is wake up by any event on 'g' or 'd', that is
a register which is drive by state (not edge).

Jim,
I have to side with Weng here. Simply define the '*' in process(*) as
an expansion of all signals that are read in the process. If this is
not what the writer want, just use the old method... This is most in
line with the original intention of VHDL where you describe a
simulation behavior without targetting specific synthesis behavior.


The semantic (I dislike this word, because lot of people use this term

only to justify their opposition) of * is not what you proposed, the *
semantic is equivalent to include any signals of the design, not only
signals of the process.

To me, I think than (*) is very dangerous.

I'll take a (real) example, I have the following code:

clk_inv <= not clk;

process (clk, resetn)
begin
if (resetn='0') then
q <= '0';
elsif (clk_inv'event and clk_inv='1') then
q <= d;
end if;
end process;

This code don't give specific error in simulation, except than
compilation, linting tool or rule-checker must generate a warning at least.

This error, on sensitivity list, come from a copy-paste without refresh
of sensitivity list; in that case the modification from clk to clk_inv
is normal (and the sensitivity list must be updated accordingly).
Now take the example and imagine the same case but with a typo error on
clk name, which is an other existing signal of the design.
If the sensitivity list is (*), I have no way to flag the typo error.
And possibly no tests fail, except perhaps in very hard to find corner
case (if both signal have similar behavior, except under very specific
cases).
After ASIC synthesis, you can have some timing problem due to not well
balanced clock tree.
Discovering error at this stage, it is very consuming of time and money;
all of this because you have don't put explicite sensitivity list, than
a linting tool, a rule-checker or the compiler can flag you in few minutes.

You have similar remark for Jim proposal, but in that case you use an
explicite structure which must be intrepreted as edge or state register.

Tom


JaI

 

[Just an Illusion]

Hi,

I have change the subject line, because I think it is no more link with
initial message.

Tom Verbeure wrote:

Now take the example and imagine the same case but with a typo error


on


clk name, which is an other existing signal of the design.
If the sensitivity list is (*), I have no way to flag the typo error.





And possibly no tests fail, except perhaps in very hard to find


corner


case (if both signal have similar behavior, except under very


specific


cases).



Basically you're saying that you want to (ab?)use the sensititivity
list as a redundancy mechanism against ordinary typos.


Not exactly, the aspect that you put into the sensitivity list are the

control part of a process.
You can have some mechanism that use content of sensitivity list to make
some check, or some assertion.

When you introduce a new element, you need extend the feature of the
language. In that case I think that is a reduction, because you can't no
more use the sensitivity list.
To me, have no sensitivity list or have (*) in sensitivity list are
equivalent.

At what point do you have to stop holding the hand of a designer and
trust that he will fix typos, run simulations to verify a design and
read the error reports of his synthesis and/or linting tool?

Say a designer writes:
a <= b;
instead of:
a <= c;
How can we protect a designer against such a potentially disastrous
typo?


In that case, that is not a real typo problem, but more a logic problem.

In my example, the typo error is in the sensitivity list content.

To check your case, formal verification, simulation...

Tom



JaI

 

[Jonathan Bromley]

On 29 Jul 2004 03:18:09 -0700, patrick.melet@dmradiocom.fr (Patrick)
wrote:

i have a vhdl algorithm for compute the min and max of a signal, but
it is not synthesizable.

This is not surprising. You are trying to bubble-sort the whole
contents of a RAM in only one clock cycle.

i have two loops with a IF..THEN statement inside
is it possible to have a if inside a loop ?

Yes. The problem is that your next-state logic makes multiple
assignments to various different locations in the memories, all
at the same moment of simulation time.

Try to decide what should happen on each clock cycle. A simple
state machine with only three states will not solve your problem.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[rickman]

Derek Simmons wrote:

Over the last couple of weeks I have tried accessing the web site
www.free-ip.com and gotten an error message. Am I the only one having
this problem or are other people having this problem?

Did something happen to this website?

Is it mirrored someplace else on the web?

I am not able to connect either. The domain name is still registered.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Patrice]

Helo
I use quartus web edition, and made me some routines but
sundely a saw that there is no math_real library in quarus !
Does it mean what mathematical operation on real cannot be made
with this board ?? (i'm interrested in sqrt function)

Thanks for reply

 

[Allan Herriman]

On Sat, 31 Jul 2004 12:41:03 +0200, "Patrice" <patrice.ulrich@evc.net>
wrote:

Helo
I use quartus web edition, and made me some routines but
sundely a saw that there is no math_real library in quarus !
Does it mean what mathematical operation on real cannot be made
with this board ?? (i'm interrested in sqrt function)

Synthesisers don't support real numbers for general use (AFAIK), so
this will be a problem with any board.

You have several options:
- recode your design to use fixed point
- implement your own floating point
- use some sort of hybrid approach, e.g. block floating point.

Also reconsider your "need" for a square root. Are you performing a
cartesian to polar conversion? There are several ways of doing that
which are more efficient that the canonical schemes.

Regards,
Allan.

 

[Jim Lewis]

Weng,

... process(*)
is introduced by Verilog, it is a very good idea!

Ironically SystemVerilog is moving on to:
always_comb, always_latch, and always_ff

So here for once we get to copy from Verilog and
take advantage of their lessons learned.

For RTL design, the added keywords carry the intent of the
sensitivity list without making you type it. You will not
get this with "(*)".

For example, in addition to meaning "(*)" _comb indicates
the process only creates combinational logic. If you
inadvertently create latches (the #1 or #2 problem in a
statemachines), then the synthesis tool is to produce and
error and not create any hardware.

Regards,
Jim

Modify process_statement definition in clause 9.2 to:
process_statement ::=
[ process_label : ]
[ postponed ] process_kind [ is ]
process_declarative_part
begin
process_statement_part
end [ postponed ] process [ process_label ] ;


Add definition for process_sensitivity in clause 9.2:
process_kind ::=
process [ ( sensitivity_list ) ]
| process_comb
| process_latch
| process_ff

It should be better like this way:
Add definition for process_sensitivity in clause 9.2:
process_kind ::=
process [ ( sensitivity_list ) ]
| process [ ( * ) ]

No any langauge I have known in the world uses keywords that contain
'_'. I really don't know why you want ot invent new wheels. process(*)
is introduced by Verilog, it is a very good idea!

Weng

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[Ken Smith]

In article <cefsvq$2cbb$1@feed.teaser.net>,
Patrice <patrice.ulrich@evc.net> wrote:

Helo
I use quartus web edition, and made me some routines but
sundely a saw that there is no math_real library in quarus !
Does it mean what mathematical operation on real cannot be made
with this board ?? (i'm interrested in sqrt function)

real=sqrt(real) Forget it

integer=sqrt(integer) Yes in more than one clock

fixedpoint=sqrt(fixedpoint) same as integer

If you can take more than one clock cycle to do it, you can make an
integer or fixedpoint SQRT. The trick is to use Booths[1] method.

[1] At least I think it was Booth, Gauss may be the real father of this.


Basic rule:

N^2 = the sum of the first N odd numbers.

Stupid method = subtract 1,3,5,7.. until it crosses zero.

Optimization:
If you multiply N by 2, you multiply N^2 by 4. As a result, you can get
there quicker if you include some shifting.




--
--
kensmith@rahul.net forging knowledge

 

[Jim Lewis]

For a beginner book that you can read cover to cover,
I like:
J. Bhasker's VHDL Primer

Cheers,
Jim

I am re-taking my VHDL class because I ended up with a "D". Mostly my
fault but also Professor was not very good at explaining. She pretty
much gave us a sheet of paper and told us the first project was due
within 2 weeks. The projects I do not think were that hard if you knew
what you are doing except the final project works up to building a
CPU.

Does anyone know of a good EASY to read and UNDERSTAND book I could
get? I googled my computer to death last semester. I got some info but
nothing that really explained, just examples and I did not know why
they did stuff.

Any help would be great, not to mention it is my last semester so I
got to get this class up to at least a "C" or I might spending an
extra semester here at school.

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[Duane Clark]

Charles M. Elias wrote:

You are sure to get diverse opinions on this, but my favorite VHDL
book is "The Designer's Guide to VHDL" by Peter Ashenden. He does
have some chapters on the design of a CPU. I have both the first and
second editions of this book as well as a number of other VHDL books,
and I think "The Designer's Guide to VHDL" is excellent. I wish you
the best of luck in your second try at the VHDL course.

Yep, I completely agree. Not only was it very readable and useful to me
when starting out, but even after several years of using VHDL, I still
refer to it.

--
My real email is akamail.com@dclark (or something like that).

 

[Egbert Molenkamp]

entity test is
port (A : in bit_vector(31 downto 0);
p : in integer;
B : out bit_vector(31 downto 0));
end test;

architecture behavior of test is

begin
B <= A Rol p;
end behavior;

Egbert Molenkamp

"Chris Connelly" <chris.connelly@blueyonder.co.uk> wrote in message
news:bf627d86.0408030129.412e6b8e@posting.google.com...

Please excuse the probable simplicity of this question.

I'm trying to use ROL and SRL logical operators and I can't seem to
find the correct syntax.

I have a bit_vector(31 downto 0) called 'tx' , now all I want to do is
rotate the vector to the left and pick of bit(0).
As I said I've tried a few arrangements ie. tx ROL 1 and ROL tx but
nothing seems to work.

Can someone let me know what the syntax is to do this simple task.

TIA

Chris

 

[Ralf Hildebrandt]

Chris Connelly wrote:

I'm trying to use ROL and SRL logical operators and I can't seem to
find the correct syntax.

I have a bit_vector(31 downto 0) called 'tx' , now all I want to do is
rotate the vector to the left and pick of bit(0).
As I said I've tried a few arrangements ie. tx ROL 1 and ROL tx but
nothing seems to work.

tx_rolled(31 downto 0) <= tx(0) & tx (31 downto 1);

works indipendent from used libraries, but is fixed as can bee seen.


Ralf

 

[e7]

mugz wrote:

I am re-taking my VHDL class because I ended up with a "D". Mostly my
fault but also Professor was not very good at explaining. She pretty
much gave us a sheet of paper and told us the first project was due
within 2 weeks. The projects I do not think were that hard if you knew
what you are doing except the final project works up to building a
CPU.

Does anyone know of a good EASY to read and UNDERSTAND book I could
get? I googled my computer to death last semester. I got some info but
nothing that really explained, just examples and I did not know why
they did stuff.

Any help would be great, not to mention it is my last semester so I
got to get this class up to at least a "C" or I might spending an
extra semester here at school.

Hi,

I'm new and trying to learn also. What systems do they teach you to use
to program up a chip? Does the software run on PC - may be Linux?
Which chips are easy to learn and use?

 

[srivaths]

i guess u can try out VHDL book by "douglas perry" i guess i got the
spelling right....thats a neat book which covers everything u need...


"Jim Lewis" <Jim@SynthWorks.com> wrote in message
news:10gv8p5mp27m183@corp.supernews.com...

Peter's book is great. It has 30 pages on everything.
I consider it a selected topics book. For beginners,
there is too much information. So I recommend that a
beginner read Bhasker's book or take a good training
class first.

For intermediate/advanced VHDL coders, Peter's book is
my number one recommended book.

Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


Third vote - very comprehensive, complete and covers the whole language.

"Duane Clark" <junkmail@junkmail.com> wrote in message
news:celq3v02fp8@news3.newsguy.com...

Charles M. Elias wrote:

You are sure to get diverse opinions on this, but my favorite VHDL
book is "The Designer's Guide to VHDL" by Peter Ashenden. He does
have some chapters on the design of a CPU. I have both the first and
second editions of this book as well as a number of other VHDL books,
and I think "The Designer's Guide to VHDL" is excellent. I wish you
the best of luck in your second try at the VHDL course.


Yep, I completely agree. Not only was it very readable and useful to me
when starting out, but even after several years of using VHDL, I still
refer to it.

--
My real email is akamail.com@dclark (or something like that).

 

[Brian Drummond]

On 2 Aug 2004 04:46:32 -0700, charles.elias@wpafb.af.mil (Charles M.
Elias) wrote:

muggzz69@yahoo.com (mugz) wrote in message news:<516afb5e.0408011735.3f5cdc94@posting.google.com>...
I am re-taking my VHDL class because I ended up with a "D".
Does anyone know of a good EASY to read and UNDERSTAND book

You are sure to get diverse opinions on this, but my favorite VHDL
book is "The Designer's Guide to VHDL" by Peter Ashenden.

Another vote for Ashenden here. But I suggest also googling for
Ashenden's "VHDL Cookbook". It is (was?) a free download covering the
basics (including a very simple CPU) clearly and concisely.

- Brian

 

[Martin Maurer]

A student of my university has created a USB 1.1 IP in VHDL.

Possible to get this code ?

Regards,

Martin

 

[Don Golding]

I would like to see the code too...

Thanks,
Don

"Martin Maurer" <capiman@clibb.de> wrote in message
news:cf0e8t$3jj$04$1@news.t-online.com...

A student of my university has created a USB 1.1 IP in VHDL.

Possible to get this code ?

Regards,

Martin

 

[Alex Gibson]

"Rob Maris" <maris@fh-aachen.de> wrote in message
news:dced596e.0408060129.6cdbf414@posting.google.com...

Since no followups of elder messages seems to be possible, I started
this as new message.

Opencores.org provides a USB 1.1 IP in verilog. Not in VHDL.

A student of my university has created a USB 1.1 IP in VHDL.

Rob

Are you guys going to add it to opencores.org ?

 

[John Williams]

Derek Simmons wrote:

I'm looking for something that supports triangles (or some other
primitives) with materials and light sources (would be nice). Or am I
wishing for too much?

It's done in Handel-C, not VHDL/Verilog, but the Celoxica folks have a
very pretty real-time 3D rendered demo that they take around to the
various FPGA / reconfigurable computing conferences. Texture maps,
lighting, bump mapping and all that sort of thing.

Might be worth getting in touch with them to find out more. Perhaps if
you get a Handel-C license and/or a Celoxica board they would be willing
to share...

Cheers,

John