I hate VHDL!!!

[valentin tihomirov]

VHDL never mentiones nested packages. As advanced HDL develper never heard
of it, I think it is not supported. Furthermore, most of VHDL code is not
compiled into packages. Nestig of libraries is not supported as well I
beleive.

 

[Allan Herriman]

On 16 Sep 2004 03:30:45 -0700, "Naimesh Thakkar"
<naimesh.thakkar@gmail.com> wrote:

Hello

I am getting following warning during simulation in ModelSim


* Warning: *DFE3C RECOVERY High VIOLATION ON CLR WITH RESPECT TO CLK;


# Expected := 1 ns; Observed := 0 ns; At : 61005 ns
# Time: 61005 ns Iteration: 1

Can any one tell what is RECOVERY High VIOLATION.
Thank for any help

Didn't you ask this same question in comp.arch.fpga recently?


Inputs to a ff must be stable just before until just after the active
edge of the clock for reliable operation.

You seem to have a transition on the async reset input at about the
same time as the active transition on the clock.

Moral: avoid using async reset inputs on ffs as a means of
implementing logic functions.

Regards,
Allan

 

[Martin Bishop]

Naimesh

You haven't specified your device or the details of your toolset (i.e.
simulation libraries).

However, I presume you're running a VITAL simulation.

If the documentation doesn't help, you should read the source for the VITAL
model to identify which timing check has been violated; enjoy the spaghetti
code.

A work-around approach to this issue is to control the relationship between
Reset and the active clock edge in the Testbench; e.g.
wait until falling_edge(Clk); -- sync to inactive clock edge
Reset_n <= '0'; -- release reset
Note that at 12" to the foot, you will get recovery time violations ...

If you read the following threads, in comp.lang.vhdl, you will be
enlightened as to how to fix this issue at 12" to the foot:
-11 1552 Sep04 : Stefan Oedenkoven : Statemachine working on Xilinx ...
-29 14:16 Jul 04 : The Weiss Famly : Asynchronous signal problem

The second thread concrens the general problem of asynchronous signals, of
which asynchronous resets are a subset. If metastability and synchronisers
are news to you read up on them in the VHDL FAQ and using Google, and apply
the techniques to your designs.

HTH

Martin


"Naimesh Thakkar" <naimesh.thakkar@gmail.com> wrote in message
news:cibq0l$55b@odak26.prod.google.com...

Hello

I am getting following warning during simulation in ModelSim


* Warning: *DFE3C RECOVERY High VIOLATION ON CLR WITH RESPECT TO CLK;


# Expected := 1 ns; Observed := 0 ns; At : 61005 ns
# Time: 61005 ns Iteration: 1

Can any one tell what is RECOVERY High VIOLATION.
Thank for any help


Naimesh

 

[Jeroen]

"David Brown" <david@no.westcontrol.spam.com> schreef in bericht
news:cic2p4$gct$1@news.netpower.no...

"ALuPin" <ALuPin@web.de> wrote in message
news:b8a9a7b0.0409160400.35fb5d1e@posting.google.com...
Hi FPGA folks,

I am trying to get started with the Twister+Lancelot evaluation board.

Has somebody played with that boards?
I'd like to have some reference so that I could ask questions.


I've got a Lancelot connected to my Nios (Cyclone) development kit board.
It works fine, although I ended up writing my own vga firmware which is a
lot nicer (IMHO, of course than the original demo code that came with
the board (my code is vaguely based on newer Nios II application notes and
examples). The hardware is not worth copying either, since the video dac
on
the card is now considered obselete by TI. However, the board does
exactly
what it says on the tin - it is an example card with example code to get
you
started, and worked fine for me in that sense.

Somebody started a mailing list for the Lancelot, but apart from a few
initial posts, it's been dead quiet. I can't even remember its address
offhand, although I'm sure a google groups search would reveal it.

I happen to know the designer of both boards, when he showed me the Lancelot
I was quite impressed with power of dedicated Nios instructions and hardware
acceleration for the Mandelbrot demo

Jeroen

 

[Mike Treseler]

Derek Graham wrote:

Hi Mike,
I meant how do you organise code from a file
point of view rather than designs from a structural view? I realise
now that VHDL doesn't use packages for that purpose. I just find
putting all the code in one directory to be messy. I suppose I can
just alter the compiler's and simulator's arguments, which will be
difficult as I use Actel's Libero (which is a quite rubbish).

Yes. Take a look at emacs vhdl-mode.
That gives you lots of options on defining projects.
One or more directories, file lists, exclude regexps, etc.

You will get lots of opinions on this one.
I like to keep all the project source files in one directory
and sort things out with CVS, scripts and emacs speedbar.
Others will make good arguments for hierarchical directories.
I don't think there is a single correct answer.

-- Mike Treseler

 

[ivailokroumov]

Dear Derek,
I guess that you can't total organize your project with packades. Of
course, you can write packages and can use them, however this should be
usede when you want to share some information betweeen different ones
computers.
Best Regards:
Ivaylo Krumov

 

[rickman]

rickman wrote:

What are you trying to do and why do you thing two processes are clearer
than one?

Oooops, that should be "why do you THINK"...

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[glen herrmannsfeldt]

Kumar Vijay Mishra wrote:

I am getting a continuous stream of 16-bit data. In every clock cyle I
have to sort 32-size array. When I have sorted the array in ascending
order, I want to choose 24th number only. In the next clock cycle, I
get a new no added to my array while the first number gets out of the
array. The new array that I get is to be sorted again and he 24th
position number is to be taken out.
So, in every clock cycle, I get a new data (in an array of 32 16-bit
numbers) (with the oldest data getting deleted from this array) and in
the same clock cycle, I need to have the 24th-position data available
to me for further processing.

If it really works that way there is just about only one way
to do it, because you must do everything in one clock cycle.

You need to compare the number coming in against all the others
in the list, except the one going out, and arrange the new data
ready to clock in on the next cycle. Startup is a little
complicated, as you must make sure that it fills up the right
way. 32 16 bit registers, appropriate comparators and such
should fit easily in a medium sized FPGA.

-- glen

 

[John_H]

Say, your clock cycles aren't something very slow like 4MHz, is it?
Your speed needs would help drive an "ideal" solution since you could
perform all the compares with one comparator over 32 cycles.

"Kumar Vijay Mishra" <vizziee@yahoo.com> wrote in message
news:889cd7c9.0409152205.35aeb3c@posting.google.com...

Hi.

I am working on inmplementation of order statistics CFAR, where
sorting of a continuous stream of data is required.

Exactly problem is as under:
I am getting a continuous stream of 16-bit data. In every clock cyle I
have to sort 32-size array. When I have sorted the array in ascending
order, I want to choose 24th number only. In the next clock cycle, I
get a new no added to my array while the first number gets out of the
array. The new array that I get is to be sorted again and he 24th
position number is to be taken out.
So, in every clock cycle, I get a new data (in an array of 32 16-bit
numbers) (with the oldest data getting deleted from this array) and in
the same clock cycle, I need to have the 24th-position data available
to me for further processing.

Can anybody help me in this? Plus if someone can direct me to any
useful link on VHDL designs of sorting, since I am new to FPGA and
VHDL.

Thanx in advance.

 

[Eric Crabill]

Hi,

You can use an odd-even transposition sort. This is
a parallel version of the bubble sort that works well
in hardware. I have a version of it written in Verilog
on my site, http://www.engr.sjsu.edu/crabill in Lecture
Module 6. You can adapt it to your application and then
remove the pipeline registers if you want to trade
frequency of operation for lower latency.

Eric

glen herrmannsfeldt wrote:

If it really works that way there is just about only one way
to do it, because you must do everything in one clock cycle.

You need to compare the number coming in against all the others
in the list, except the one going out, and arrange the new data
ready to clock in on the next cycle.

 

[roller]

"ALuPin" <ALuPin@web.de> escribió en el mensaje
news:b8a9a7b0.0409160507.2849ff41@posting.google.com...

Hi,

I am writing a VHDL testbench with the following structure:
For the purpose of clarity
I want to assign values to a signal in process A.
When reaching a certain value I want to continue assigning
values to the same signal in a different process B.

you cant, process are concurrent, which one will start?

Is this possible somehow?

yes, somehow

use a mux to select which "temporal" signal driven by each process is going
to drive the "final" one

though, i dont see why you want to do it that way...you could use a single
process, or a FSM...

 

[Jim Lewis]

Mohammed,
I too would prefer to have chosen an unresolved type
as our base - like std_ulogic, however, I cannot undo
what is already done (note this did not stop me from
proposing it).

Given that we are stuck with std_logic, what you really
want is for a simulator to warn you during compilation
that a signal that does not have a tristate is multiply
driven. I think I have seen this from some newer tools.
If your tool is not doing this, it would not be unreasonable
to ask them to.

Cheers,
Jim

Consider the code below……

ARCHITECTURE arch OF nothing IS

BEGIN

PROCESS(a,b,c)
BEGIN
…
z <= not b;
…
END PROCESS;

PROCESS(e,f,g)
BEGIN
…
z <= e and f;
…….
END PROCESS;

END ARCHITECTURE arch;


If the above signals are std_logic then above example WILL NOT
give any ERROR when simulated. Though my intention was not to make a
buffer (multiple source) there (Suppose it was mistakenly assigned 2
times to z).
Ok I accept the the advantages of detecting uninitialized signals etc
from the above discussion . std_logic type is a resolved type so use
it for that purpose. The function of detecting uninitized signals can
be done by using std_ulogic too.

Regards,
Mohammed Khader.

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[valentin tihomirov]

I just find putting all the code in one directory to be messy.
How do you organise your code/files??

You can put your files wherever you like on you disk. Just tell the correct
compilation order to the simulator and synthesier.

 

[ivailokroumov]

Dear ALuPin, I can't understand you, why do you want to use two processes
but it's your business. The nature of the processes is that they are
concurently each to other. It does mean that they are work at same time.
The operators whitin the process are sequential. O'K, It it is just as
information. The code that was posted from you, I guess won't produce the
result which you expect. It'll give you error, because you try to conduct
"l_signal" in different process. At first time,the signal would be shared
type. About my opinion , should be better to use code which represent
chain processing of this signal.

A: process
begin
while l_signal < 3 loop
l_signal := l_signal + 1;
end loop;
wait until rising_edge(clk);
end process A

B: process
begin
while l_signal <= 4 loop
l_signal := l_signal + 1;
end loop
wait until rising_edge(clk);
wait;
end process B

Keep in mind that all process are started just one every time when you
start your simulation.

 

[Nicolas Matringe]

Johnsy Joseph a écrit:

Hello Everybody,

I would be grateful if somebody helped me with this. I have the
following definitions.

type byte is array(7 downto 0) of std_logic;
type sarray is array(6 downto 1) of byte;

variable shift_register:sarray;
variable shftreg_data: std_logic_vector(7 downto 0);


I would like to do the something like this-

shift_register(0)(7 to 0) := shftreg_data(7 to 0);

I basically want to assign a vector to one of the elements of my array
of vectors but it isnt working. I am using VHDL'87 but it doesnt
compile. Any methods to do such a thing?

Hi
VHDL is a strongly typed language. You can not assign a value to a
signal/variable if their types don't match.
In your example, shftreg_data is std_logic_vector and shift_register(0)
is byte so you can't do it.
Luckily, their types are closely related: they are made of elements of
the same type. You can juste type cast your value:
shift_register(0)(7 to 0) := byte(shftreg_data(7 to 0));


--
____ _ __ ___
| _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
| | | | | (_| |_| | Invalid return address: remove the -
|_| |_|_|\__|\___/

 

[Egbert Molenkamp]

Some remarks:
1. You defined a new type byte. This is not the same type as
std_logic_vector and therefore the assignment
shift_register(0)(7 to 0) := shftreg_data(7 to 0); has problems with
incompatible types.
Suggestion: use a subtype for byte:
SUBTYPE byte IS std_logic_vector(7 downto 0);

2. shift_register(0)(7 to 0) notice that element 0 is not in the range om 6
downto 1 (see type declaration of sarray).

3. you mix up "downto" and "to". If your vector is declared as a "downto"
then a slice of that vector should also be a "downto".

So a corrected piece of code looks like:

subtype byte is std_logic_vector( 7 downto 0);
type sarray is array(6 downto 0) of byte;

variable shift_register:sarray;
variable shftreg_data: std_logic_vector(7 downto 0);

shift_register(0)(7 downto 0) := shftreg_data(7 downto 0);

Egbert Molenkamp

"Johnsy Joseph" <johnsy_podimala@hotmail.com> schreef in bericht
news:c1a0a9f2.0409200357.7101078c@posting.google.com...

Hello Everybody,

I would be grateful if somebody helped me with this. I have the
following definitions.

type byte is array(7 downto 0) of std_logic;
type sarray is array(6 downto 1) of byte;

variable shift_register:sarray;
variable shftreg_data: std_logic_vector(7 downto 0);


I would like to do the something like this-

shift_register(0)(7 to 0) := shftreg_data(7 to 0);

I basically want to assign a vector to one of the elements of my array
of vectors but it isnt working. I am using VHDL'87 but it doesnt
compile. Any methods to do such a thing?

Thanks for the help
Warm Regards
Johnsy

 

[Jim Lewis]

Going one step further from what Egbert wrote,
you can leave off the lower level of indicies:

shift_register(0) := shftreg_data;

Also if your are going to define the subtype byte,
then you ought to use it when you declare shftreg_data:
variable shftreg_data: byte;

Or alternately, don't use byte at all:
type sarray is array(6 downto 0) of std_logic_vector(7 downto 0);

Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Some remarks:
1. You defined a new type byte. This is not the same type as
std_logic_vector and therefore the assignment
shift_register(0)(7 to 0) := shftreg_data(7 to 0); has problems with
incompatible types.
Suggestion: use a subtype for byte:
SUBTYPE byte IS std_logic_vector(7 downto 0);

2. shift_register(0)(7 to 0) notice that element 0 is not in the range om 6
downto 1 (see type declaration of sarray).

3. you mix up "downto" and "to". If your vector is declared as a "downto"
then a slice of that vector should also be a "downto".

So a corrected piece of code looks like:

subtype byte is std_logic_vector( 7 downto 0);
type sarray is array(6 downto 0) of byte;

variable shift_register:sarray;
variable shftreg_data: std_logic_vector(7 downto 0);

shift_register(0)(7 downto 0) := shftreg_data(7 downto 0);

Egbert Molenkamp

"Johnsy Joseph" <johnsy_podimala@hotmail.com> schreef in bericht
news:c1a0a9f2.0409200357.7101078c@posting.google.com...

Hello Everybody,

I would be grateful if somebody helped me with this. I have the
following definitions.

type byte is array(7 downto 0) of std_logic;
type sarray is array(6 downto 1) of byte;

variable shift_register:sarray;
variable shftreg_data: std_logic_vector(7 downto 0);


I would like to do the something like this-

shift_register(0)(7 to 0) := shftreg_data(7 to 0);

I basically want to assign a vector to one of the elements of my array
of vectors but it isnt working. I am using VHDL'87 but it doesnt
compile. Any methods to do such a thing?

Thanks for the help
Warm Regards
Johnsy

 

[mike_treseler]

Just put the signal assignment

queueisfull <= 1 when queuetop = '100' else '0';

inside your process.

-- Mike Treseler

 

[Srinivasan Venkataramanan]

Hi,

"mike_treseler" <tres@fl_ke.com> wrote in message
news:b400ad4ed146a8538730135c08920c04@localhost.talkaboutprogramming.com...

Just put the signal assignment

queueisfull <= 1 when queuetop = '100' else '0';

inside your process.

Isn't when..else a concurrent statement?

-- Mike Treseler

P.S. Not sure if this is the same Mike Tressler as:
mike_treseler@comcast.net ?
--
Srinivasan Venkataramanan
Corp. Appl. Engineer
Synopsys India Pvt. Ltd.
Bangalore, India
email:synopsys.com@svenkat
I own my words and not my employer, unless specifically mentioned

 

[H. Peter Anvin]

Followup to: <cic2p4$gct$1@news.netpower.no>
By author: "David Brown" <david@no.westcontrol.spam.com>
In newsgroup: comp.arch.fpga

I've got a Lancelot connected to my Nios (Cyclone) development kit board.
It works fine, although I ended up writing my own vga firmware which is a
lot nicer (IMHO, of course than the original demo code that came with
the board (my code is vaguely based on newer Nios II application notes and
examples). The hardware is not worth copying either, since the video dac on
the card is now considered obselete by TI. However, the board does exactly
what it says on the tin - it is an example card with example code to get you
started, and worked fine for me in that sense.

Somebody started a mailing list for the Lancelot, but apart from a few
initial posts, it's been dead quiet. I can't even remember its address
offhand, although I'm sure a google groups search would reveal it.

http://www.zytor.com/mailman/listinfo/lancelot

Please join and liven up the place

-hpa