I hate VHDL!!!

[Jeroen]

"Khashishi" <spam@mailinator.com> wrote in message
news:f90f4bdc.0409211114.3fbf742b@posting.google.com...

If I have a signals a and b, how can I make another signal c === a &
b.
I want to be able to assign c, and automatically update a and b.
In addition, I want to be able to assign a, and update c. I want them
to physically refer to the same signal. This is for convenience and
maintainability reasons.

I can't use assigment, because vhdl assignment operators are
directional, which makes no real physical sense to me.
So if I do
c <= a & b;
I can't assign c to update a & b, because then it would be multiple
drivers.

Verilog has a wire command which does what I want. I'm constrained to
vhdl.
Aliases don't have the full flexibility of signals in vhdl. I can't
seem to build an alias like this:
alias c(1) is b;
alias c(0) is a;
(You'll tell me, it's not allowed in VHDL. Well, I can't see any
reason why it shouldn't be allowed.)
I could do:
alias a is c(0);
alias b is c(1);
; however, this method won't allow me to set a as a port out variable
which I want to define in an upper level.

I think it might be possible to instantiate some component and route
a, b, c through the port mapping somehow, but this just seems tortuous
and contra my goal of convenience and maintainability.

Is VHDL inadequate to provide a solution to this? Or am I just missing
something?

After reading this a few times I see what you want to do, but I fail to see
the why. In C you could use a union to do what you want, or do some wizardry
with pointers. But I think it cannot be classified as a good coding practise
to have 3 different names that are the same signal.

Jeroen

 

[Jim Lewis]

Srinivasan Venkataramanan wrote:

Just put the signal assignment

queueisfull <= 1 when queuetop = '100' else '0';

inside your process.



Isn't when..else a concurrent statement?

At least until the next language revision.
There is a proposal to address this.
See FT10B at:
http://www.eda.org/vhdl-200x/vhdl-200x-ft/proposals/proposals.html

Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[Mike Treseler]

Srinivasan Venkataramanan wrote:

Just put the signal assignment
queueisfull <= 1 when queuetop = '100' else '0';
inside your process.

Isn't when..else a concurrent statement?

You're right, better make that:
"Just put a signal assignment inside your process."

-- Mike Treseler

 

[Nicolas Matringe]

Vince a écrit:

Try to change this
----------------------------
if wr = '0' then
temp_w <= "0010"
elsif rd = '0' then
temp_w <= "0000";
else temp_w <= "0001";
end if;
---------------------------------------
****(if+ elsif + else) i hate this code....
by this:
---------------------------------
temp_w <= "0001";
if wr = '0' then
temp_w <= "0010"
elsif rd = '0' then
temp_w <= "0000";
end if;
---------------------------------

Strictly equivalent, this won't change anything.
I think the problem comes from wr which is probably asynchronous, or
badly resynchronized.


--
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[Mike Treseler]

Nicolas Matringe wrote:

I think the problem comes from wr which is probably asynchronous, or
badly resynchronized.

I agree. Find all the inputs not synchronous with extclk,
and fix them something like this:

http://groups.google.com/groups?q=test_dqdq

Your code looks good otherwise.

-- Mike Treseler

 

[rickman]

Mike Treseler wrote:

Srinivasan Venkataramanan wrote:

Just put the signal assignment
queueisfull <= 1 when queuetop = '100' else '0';
inside your process.

Isn't when..else a concurrent statement?

You're right, better make that:
"Just put a signal assignment inside your process."

-- Mike Treseler

It doesn't matter. Moving the assignment of queueisfull inside the
clocked process will make it a registered signal which is not what the
OP seems to intend. But from the several mistakes he has made, I think
he might not be sure of what he intended.

My guess is that he is learning the language. In that case I think he
is taking the wrong approach. I encourage people to always design in
terms of hardware, thinking of how they expect to implement the design
in logic and register blocks, *then* try to describe this logic using
the HDL. Typically this produces very consistent code that is easier to
understand and debug.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[rickman]

Khashishi wrote:

If I have a signals a and b, how can I make another signal c === a &
b.
I want to be able to assign c, and automatically update a and b.
In addition, I want to be able to assign a, and update c. I want them
to physically refer to the same signal. This is for convenience and
maintainability reasons.

Personally I don't see how this would improve maintainability. In fact,
it can reduce it since it sounds like you want to be able to assign this
"wire" in separate modules which would be very hard to debug.

I can't use assigment, because vhdl assignment operators are
directional, which makes no real physical sense to me.
So if I do
c <= a & b;
I can't assign c to update a & b, because then it would be multiple
drivers.

Verilog has a wire command which does what I want. I'm constrained to
vhdl.
Aliases don't have the full flexibility of signals in vhdl. I can't
seem to build an alias like this:
alias c(1) is b;
alias c(0) is a;
(You'll tell me, it's not allowed in VHDL. Well, I can't see any
reason why it shouldn't be allowed.)
I could do:
alias a is c(0);
alias b is c(1);
; however, this method won't allow me to set a as a port out variable
which I want to define in an upper level.

If a is an out port, then why can't you use an assignment? Or assign a
to z and use z in the output port.

I think it might be possible to instantiate some component and route
a, b, c through the port mapping somehow, but this just seems tortuous
and contra my goal of convenience and maintainability.

Is VHDL inadequate to provide a solution to this? Or am I just missing
something?

I think I am missing the reason that you want to do this. Where are the
different assignments to this one wire? Normally assigning values to a
signal can only be done in a single process or concurrent assignment
unless it is a tristate bus. Is that what you are doing? If so, you
might want to use inout port for a.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[rickman]

Mike Treseler wrote:

Nicolas Matringe wrote:

I think the problem comes from wr which is probably asynchronous, or
badly resynchronized.

I agree. Find all the inputs not synchronous with extclk,
and fix them something like this:

http://groups.google.com/groups?q=test_dqdq

Your code looks good otherwise.

I think the code will work, but it looks like he is trying to use
one-hot encoding, but I don't think this is going to work. Plus I see
one possible error. He is using four states, 0000, 0001, 0010 and
0100. The msb never changes. I think the states should be 0001, 0010,
0100 and 1000. Plus the way he has coded this, unless the compiler is
very smart about recognizing one-hit encoding, it will still generate
logic to decode all four bits on each transition.

To use one-hot encoding, typically an enumerated type is used and an
attribute is added to indicate one-hot encoding. I don't like this
myself since I am not sure it is fully portable. So I construct my
one-hot FSM by describing the various bits separately. temp_w(0) <=
f(...). Then the optimal logic is easily obtained.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[jandc]

Hi alls,
I am facing problem with the following process.
state machine from state "0001" goes to state "0011" instead of "0010"
when the wr signal is low.
Can u suggest something ?

Regards,

Anupam


PROCESS (rst, extclk) --PROCESS no 01

BEGIN
IF rst = '0' THEN
temp_w <= "0000";
wrpointer_tx <= (OTHERS => (OTHERS => '0'));
wren_txram <= '0';
wraddress_txram <= (OTHERS => '0');
ELSIF rising_edge(extclk) THEN
case temp_w is
when "0000" =
wren_txram <= '0';
IF cs = '0' AND offset < "100000" THEN
temp_w <= "0001";
else temp_w <= "0000";
end if;
when "0001" =
wren_txram <= '0';
wraddress_txram <= ch_no & wrpointer_tx(conv_integer(ch_no));
data2txram <= datain;
if wr = '0' then
temp_w <= "0010";
elsif rd = '0' then
temp_w <= "0000";
else temp_w <= "0001";
end if;
when "0010" =
temp_w <= "0100";
wren_txram <= '1';
wrpointer_tx(conv_integer(ch_no)) <=
wrpointer_tx(conv_integer(ch_no)) + 1;
when "0100" =
wren_txram <= '1';
IF cs = '1' OR wr = '1' THEN
temp_w <= "0000";

ELSE
temp_w <= "0100";
END IF;

when others => null;
end case;
IF cs = '0' AND wr = '0' AND offset = OFFSET_XRES AND
datain(bit_XRES) = '1' THEN
wrpointer_tx(conv_integer(ch_no)) <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;

Euhm... first of all: using a seperate process for the statemachine
(which calculates nextstate) and a register to store state itself is a
very good idea...

Is it possible thet wr is a 'weak low' signal? This means that wr is 'L'
and nog '0'. So in simulation this check will be false...
If this is true change
if wr = '0' then
to
if wr /= '1' then
or
if to_X01(wr) = '0' then