I hate VHDL!!!

[Ralf Hildebrandt]

ALuPin wrote:

When l_load is high I want to load data but these data
should be random for example between 0 and 7 (integer).

How can I solve that problem with a function ?

Use a pseudo-random number generator, which is a linear feedback shift
register (LFSR). This is nothing more than a chain of flipflops with
some feedback at special (!) points via XOR-gates.

In number theory it is a primitive and irreducible polynomial over
Galois Field of 2. This polynomial can easily represented by a LFSR.

Polynomials with the same characteristics are used in CRC checksum
generators - so you can take one of these.


Initialize such a LFSR during reset and let it run freely with your main
clock. (That consumes a little bit energy...)

Note: LFSRs provide not a true random signal - only pseudo-random.


Ralf

 

[Mike Treseler]

Bob wrote:

Say I am contracted to design an FPGA or ASIC, or indeed write some
e.g. 'C' code for another company. When finished, I supply the device
netlist/programming file to the company, who pay me for my work.
Q1...Who owns the source VHDL or in the case of software the source C
code?
Q2...Do I have any claims over the copyright in the case of source?
Q3...If I develop some innovative hardware in the VHDL, who is the
owner...company or me ?

Whatever it says in the contract.
If it's not in the contract, it's debatable.

-- Mike Treseler

 

[Egbert Molenkamp]

"Mohammed A.khader" <akfami@hotmail.com> schreef in bericht
news:a132b118.0409060042.76c27062@posting.google.com...

Hi all,

I have a State Machine with 6 states (binary encoded).
TYPE state_vector IS (s0,s1,s2,s3,s4,s5);
SIGNAL pstate,nstate : state_vector;

In order to avoid combinational logic after Filp Flops in a moore
model , I want to assign specific binary values so that I could take
o/ps directly from Flip Flops.

If you want the output to be an output of a flipflop you can also assign to
that output signal in the"synchronous part" of the process.
The you will get then automatically a flipflop. Maybe more flipflops then
minimal required for the system.

what should I do to achieve it ? I know about the Pragma
ENUM_ENCODING, but it is only for sythesis.I want to check design by
simulation. Is there any particular keyword or other means to assign
particular value to states in VHDL.

During simulation your type state_vector is not mapped on any code. During
simulation you will see the states s0 .. s5.
If you want to simulate also the coding you could use the following approach

constant s0 : std_logic_vector(2 downto 0):="000";
...
constant s5 : std_logic_vector(2 downto 0):="101";
signal (or variable) state : std_logic_vector(2 downto 0);]
and then the code you have.

Now you have a combination "logical namens (the constants)" and the binary
code.

Later I have the PORT MAP the o/p from Filp Flop (Present state) to
the next module(which is of type std_logic). Hence I need to convert
the SIGNAL pstate (see above signal declaratoin) to type std_logic.
what could be the better way to do this ?

If the next module requires type std_logic(_vector) you have to make the
conversion. You can write a function.
However if the type state is globaly known you can still use s0 .. s5.

Egbert Molenkamp

 

[valentin tihomirov]

Pl add the "sel" in sensitivity list and assign the value to
out_5,....,out_8 at sel = '1' and value to out_1,....,out_4 at sel = '0'

Is'nt it what he is doing now? It was mentioned that latches will be
incured.

 

[Thomas Rudloff]

ALuPin wrote:

Hi VHDL folks,

does somebody know if there are VHDL models available for
USB devices ? A simple model (behavioral) would do the
job.

Any hints are appreciated.

Thank you for your help.

Rgds


Look at

http://www.opencores.org/

Regards
Thomas

 

[Klaus Falser]

In article <ch2j0j$1bc$1@reader08.wxs.nl>, rajan100000@hotmail.com
says...

Hi,

I want to ask you if the following code written is correct:

process (in_1, in_2, in_3, in_4, in_5, in_6, in_7, in_8)
begin
if (sel = '1') then
out_1 <= in_1;
out_2 <= in_2;
out_3 <= in_3;
out_4 <= in_4;
else
out_5 <= in_5;
out_6 <= in_6;
out_7 <= in_7;
out_8 <= in_8;
end if;
end process;

I would appreciate your help.

Thank you.

rajan

IMHO the simplest way to write a 2-way multiplexer for switching
between 2 signals is :

MuxedOut <= SignalA when sel= '1' else SignalB;

This is short and there is no need to worry about sensitivity
lists.

The second recommandation for you is to learn to use
vectors.
It is much more readable and less error prone if you
write

out(4 downto 1) <= input(4 downto 1);

instead of writing 4 single assignments.

Best regards

--
Klaus Falser
Durst Phototechnik AG
kfalser@IHATESPAMdurst.it

 

[Sunil Shukla]

Hi ALuPin,

Probably, the compiler wants you to use mux (using case statement, as the
conditions are mutually exclusive) instead of priority encoder.

Cheers,
Sunil
====================
www.uq.edu.au/~uqsshukl

"ALuPin" <ALuPin@web.de> wrote in message
news:b8a9a7b0.0409070107.4ddf842f@posting.google.com...

Hi VHDL folks,

I get the info warning
"Info, conditions are mutually exclusive; resolve without priority."


when compiling the following process:


process(Reset, Clk)
begin
if Reset='1' then
l_speed <= '0';

elsif rising_edge(Clk) then

if Rx_data(3 downto 0)="0100" then
l_speed <= '0';
elsif Rx_data(3 downto 0)="1010" then
l_speed <= '1';
else
l_speed <= l_speed;
end if;
end if;
end process;

What does the info warning mean?

Thank you for your help.

Rgds

 

[Allan Herriman]

On 9 Sep 2004 01:33:18 -0700, unisol44@gmail.com (Dev) wrote:

Hi all,

I want to convert 16E1 lines into E3 using VHDL.

Can anybody suggest how to go about it.

This is a standard mux configuration, as defined by the ITU-T.

As a rough guess, this document may be applicable:

G.753 11-1988 Third order digital multiplex equipment operating at 34
368 kbit/s and using positive/zero/negative justification

You will need to read a large number of other ITU-T documents to fully
understand the requirements. It is best to buy the CD.
The ITU-T documents are a little "dry". I suggest reading the
datasheets for some commercial M13 mux chips (such as those from
PMC-Sierra) to get you started.


You will also need to have a good idea about how to design for a
particular jitter transfer function when using justification.


http://www.itu.int/publications/main_publ/itut.html

Regards,
Allan

 

[valentin tihomirov]

IMHO the simplest way to write a 2-way multiplexer for switching
between 2 signals is :

MuxedOut <= SignalA when sel= '1' else SignalB;

This is short and there is no need to worry about sensitivity
lists.

Will these internal muxes be supported in VHDLXX

MuxedOut <= A when S1 else (B when S2 else C);


???

 

[Nicolas Matringe]

Mohammed A.khader a écrit:

Hi all;

The significance of std_ulogic is to simulate the digital circuits
at electrical level, for synthesis it does'nt have any significance.
So when I write code for RTL synthesis I can use binary logic since
this the one which is going to be implemented. But many books suggest
to use std_logic though I am not using any buses . My question is why
should one choose other than bit logic for RTL synthesis . (Expection
is std_logic for bus).

Hi
There are many reasons.
If you use std_logic for busses, you will need std_logic for its
elements, logic feeding it or being fed by it, unless you want to use
conversion function.
You design for synthesis, that's OK. We all do that too. But before you
implement your code you will have to simulate it, and std_logic is much
nicer than bit (unitialized or conflicting signals appear, for example)

These are the 2 reasons that come to my mind but I'm sure I can think of
others )

--
____ _ __ ___
| _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
| | | | | (_| |_| | Invalid return address: remove the -
|_| |_|_|\__|\___/

 

[Pieter Hulshoff]

jin wrote:

then call 24 processes like:
U1: process ( config_clock(1))
variable j; --j is valid from 1 to 24
...
... clock_chain_mask_1(j) <= '1';
end process U1;

U2: process ( config_clock(2))
variable j;
...
... clock_chain_mask_1(j) <= '1';

I presume you meant clock_chain_mask_2(j) here?

This works fine. If I change data structure to array, like:
U1: process ( config_clock(1))
variable j;
...
... clock_chain_mask(j)(1) <= '1';
end process U1;

U2: process ( config_clock(2))
variable j;
...
... clock_chain_mask(j)(2) <= '1';
end process U2;
the clock_chain_mask array cannot ouput any signal. I am wondering if
the array signal can be assigned in process like this way. Thanks.

Signals are considered one entity. This means that if you write 1 element of
an array, you implicitely write the other elements with their current
value. Since you cannot write to one signal from multiple processes, you
cannot do this with elements of an array either. That's why your first
example has no problems, and the second example does.

Regards,

Pieter Hulshoff

 

[valentin tihomirov]

Yes, you are right, std_logic is needed for busses but all the
other logic is of type bit.

I was sure it is bit_vector that is needed for describing buses.

 

[rickman]

valentin tihomirov wrote:

Yes, you are right, std_logic is needed for busses but all the
other logic is of type bit.

I was sure it is bit_vector that is needed for describing buses.

The term bus is being misused to describe a signal shared between
multiple sources. Think tri-state bus.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[rickman]

"Mohammed A.khader" wrote:

To believe as you think please answer one more question.
what would synthesis tool would do if I write this code.....

All signals are of type std_logic.
process (SEL, A, B, C, D)
begin
case SEL is
when "00" => MUX_OUT <= A;
when "01" => MUX_OUT <= B;
when "10" => MUX_OUT <= C;
when "11" => MUX_OUT <= D;
when others => MUX_OUT <= 'X';
end case;
end process;

I believe synthesis tools ignore the others since all of the states of
interest to a synthesis tool have been listed. You will get warnings in
a simulator, but in synthesis you can leave off the "others" clause.

what would synthesis tool would do if 1)I declare signals as of type
bit 2)I declare signals as of type std_logic.(what would it do with
others clause in this case).

The same in both cases. Why don't you try it and let us know if you get
a difference?


--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[ivailokroumov]

Hi Mohammed,
You know me just through my e-mail. I am Ivaylo Krumov from Bulgaria.
About your question
"My question is why should one choose other than bit logic for RTL
synthesis"
You should use std_logic because it can be syntesisable and this type
cover different electronic levels. You know that has logic "0" and logic
"1" where represent LOW and HIGH levels It's OK of course, these are real
representation about 0 Voltage and Vcc. Actually this is something
relative. For digital circuits are recognized different Vil, Vih, Vol and
Voh. These are different logic levels. And of course, if you use TTL logi
they are with values Vil belongs between 0 and 0,8V and Vih belongs
between 2V and 5V. Vol belongs between 0 and 0.4V VoH belongs between 2.4V
and 5V. These values are different for other kind logic like LV, CMOS,
HCMOS, HCTMOS, F, ALS, ALVC e.g.
In this way, imagine that you operate with 2-input XOR and need to manage
input_A with different bits either "0" or "1" Actually You can connect
this input directly to ground or Vcc. it is going to be either HARD 1 or
HARD 0 and if you use bit type everything is OK. But imagine that you are
going to connect this input through resistor, it's going to represent wake
"0" or wake "1" Actually these aren't real "0" and "1" and if you use bit
type, you cann't produce implementation. At rise time of digital
electronic and design different company showed up to 46 different leves
for coverring. So you neet to use std_logic or std_logic_vector if you
wish to make syntesisable models and to see real design. But if you wish
just to make models or design, for simulation, no problem to use bit or
bit_vector.
At the other view point, has difference betweeen std_logic and std_ulogic,
std_logic_vector and std_ulogic_vector. The difference is that std_ulogic
or std_ulogic_vector kinds are used in components that have JUST one
driving source. Where as The signals aren't share between the sources
Best Regards:
Ivaylo Krumov

 

[David Bishop]

Sridhar Hegde wrote:

Hi,

Im new here so be gentle.My first post

I am trying to synthesize a ROM and it works out fine in Xilinx ISE
6.2.03i for Synthesize and Implement.However when I create a test
bench and try to see a Post Translate simulation result, I get
warnings about unbound components. Following is the warning and the
snippet of code that Im using.What am I doing wrong here....Any help
is appreciated!!!

First, read the Synplicity style guide. They have a very specific
way that they want to see ROMs done. What you have will most likely
get crunched down to a boolean equation, and not a ROM.

Second you may consider building a ROM with the Xilinx CoreGen
tool. Then you can just plug it in.

I am getting the following warnings(a lot of them) when I synthesize
the following code for a ROM. What am I doing wrong?

Without seeing them, I can't say.

On a post translate or a post place and route simulation, I get a 'U'
on my output pin...

The error I see looks something like
Warning: (vsim-3473) Component 'mmux_n0001_inst_mux_f8_3' is not
bound.
# Time: 0 ps Iteration: 0 Region: /inromtbw/uut File:
inrom_translate.vhd
# ** Warning: (vsim-3473) Component 'mmux_n0001_inst_mux_f5_49' is not
bound.
# Time: 0 ps Iteration: 0 Region: /inromtbw/uut File:
inrom_translate.vhd
# ** Warning: (vsim-3473) Component 'mmux_n0001_inst_mux_f5_32' is not
bound....

and so on

Then a "U" is exactly what I would expect to see. It's not finding
this component.

Code snippet for Inrom:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

Here is your first problem.
Either use "numeric_std" OR "std_logic_arith". Both define the types
"signed" and "unsigned". The rule in VHDL is that if two objects of
the same name are visible within a scope, then neither are visible.
You are not using the functionality in any of the last 3 packages.

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity inrom is
Port ( en : in std_logic;
clk : in std_logic;
dout : out std_logic_vector( 15 downto 0);--16 bit data that needs to
be input to the system
valid : out std_logic; --Tells that valid data is present on output
reset : in std_logic
);
end inrom;

architecture rtl of inrom is

type array_rom is array (31 downto 0) of std_logic_vector( 15 downto
0);
signal myarray : array_rom;
signal valid_sig:std_logic;
signal dout_sig : std_logic_vector(15 downto 0);
signal clk2: std_logic;

begin

myarray(0) <= x"0000";
myarray(1) <= x"0000";
myarray(2) <= x"0000";
myarray(3) <= x"003C";
myarray(4) <= x"0000";
myarray(5) <= x"0000";
myarray(6) <= x"0064";
myarray(7) <= x"0000";
myarray( <= x"0000";
myarray(9) <= x"000A";
myarray(10) <= x"0000";
myarray(11) <= x"0000";
myarray(12) <= x"003C";
myarray(13) <= x"0000";
myarray(14) <= x"0000";
myarray(15) <= x"0064";
myarray(16) <= x"0000";
myarray(17) <= x"0000";
myarray(18) <= x"0046";
myarray(19) <= x"0000";
myarray(20) <= x"0000";
myarray(21) <= x"006E";
myarray(22) <= x"0000";
myarray(23) <= x"0000";
myarray(24) <= x"000A";
myarray(25) <= x"0000";
myarray(26) <= x"0000";
myarray(27) <= x"0046";
myarray(28) <= x"0000";
myarray(29) <= x"0000";
myarray(30) <= x"006E";
myarray(31) <= x"0000";

process( reset,clk)
variable romvar:natural range 0 to 31;
--variable incr: boolean;

begin



if reset = '1' then
dout_sig <= (others=>'0');
valid_sig <='0';
romvar :=0;



elsif (clk'event and clk='1') then
if en='1' then

dout_sig <= myarray (romvar);
valid_sig<='1';
romvar :=romvar + 1;

else
dout_sig <= myarray (romvar);
valid_sig<='0';

This looks functionally Ok. Must be something else going on.

end if;

end if;

end process;

dout <= dout_sig;
valid <=valid_sig;

end rtl;
===================================
Thanks in advance,
Sridhar

--------------------------------------------------------------------------------

 

[Nicolas Matringe]

EmbSys a écrit:

Hello -

[...]
I can do this thus:

LCD_Data <= data & data & data & data;

Is there are a better (more elegant?) way?

Hi
you can use a for...generate loop:

data_rep : for i in 0 to 3 generate
LCD_data(8*i to 8*i+7) <= data;
end generate;

--
____ _ __ ___
| _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
| | | | | (_| |_| | Invalid return address: remove the -
|_| |_|_|\__|\___/

 

[Allan Herriman]

On 13 Sep 2004 05:04:45 -0700, ALuPin@web.de (ALuPin) wrote:

Hi VHDL folks,

I want to display some comments on the wave window of Modelsim.

In my VHDL testbench I have the following signal assignments.
At the locations with *** I would like to see some comment
in the simulation wave.

Does somebody know how to realize that?

Have you tried creating a signal of type "string" then assigning
values to it? Modelsim can display the string value in the waveform
window.

Regards,
Allan

 

[Tim Hubberstey]

ALuPin wrote:

Have you tried creating a signal of type "string" then assigning
values to it? Modelsim can display the string value in the waveform
window.

Regards,
Allan
I have tried something like
signal l_show_in_wave : string(10 downto 0);

...
l_show_in_wave <= "Example ";

But the problem with that is that you have to define the range
with regard to the number of used characters.
I mean if the comment gets longer you have to change the
range and all other assignments.

Is there a more elegant way?

Create an enumerated type and assign to it. The values that show up in
the wave window will be the same as what you use in your TYPE
declaration, except that they will be all lowercase. For example:

type states is (phase_1, phase_2, done);
signal whatsgoingon : states;
....
whatsgoingon <= phase_1;
--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com

 

[anupam]

All the other logics will consume the same logic and the same hardware will
be generated.
Regards,
Anupam