I hate VHDL!!!

[Stéphane Acounis]

Le Mon, 16 Aug 2004 06:38:22 -0700, Patrick a écrit :

Hello,

Do you know if Quartus II 4.0 Software is functionning with 1 Go RAM ?

The software getting an Internal Error which is not related in the
altera site web...

Thanks...

I am using Quartus2 4.1 on my laptop with 1GB of memory under Linux with
no problem.

--
Stéphane ACOUNIS
ŤChaque fois, chaque fois, chaque fois, que je te vois,
chaque fois que tu sors de chez moi, tu es complčtement fracať

 

[Mike Treseler]

cp wrote:

Could anyone advise me which synthesis software packages that claim to
be IEEE 1076.6 (VHDL Synthesis Interoperability standard) compliant?

You don't need any special vendor packages for synthesis.
ieee.std_logic_1164 and maybe ieee.numeric_std are all you need.
Successful synthesis has more to do with coding style.

--Mike Treseler

 

[Nicolas Matringe]

Mike Treseler a écrit:

pegase5705@yahoo.co.uk (Mike) wrote in message news:<35df03b2.0408151012.c75567d@posting.google.com>...

There seems to be a problem using named association with ModelSim. If
I instantiate a component with:

uut: cnt8
port map (
clk_i => clk,
n_reset_i => n_reset,
tco_o => tco,
q_o(0) => cnt_q(0),


The line above is the problem.
The right hand side can't be a slice.

Actually it can. Used it many times. I would say the *left* hand side
can not be a slice.


--
____ _ __ ___
| _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
| | | | | (_| |_| | Invalid return address: remove the -
|_| |_|_|\__|\___/

 

[Duane Clark]

Nicolas Matringe wrote:

Mike Treseler a écrit:

pegase5705@yahoo.co.uk (Mike) wrote in message news:<35df03b2.0408151012.c75567d@posting.google.com>...


There seems to be a problem using named association with ModelSim. If
I instantiate a component with:

uut: cnt8
port map (
clk_i => clk,
n_reset_i => n_reset,
tco_o => tco,
q_o(0) => cnt_q(0),


The line above is the problem.
The right hand side can't be a slice.


Actually it can. Used it many times. I would say the *left* hand side
can not be a slice.

I have made both sides slices many times. The restriction that I have
found is that if the left side is a slice, then all bits of that bus
must be assigned to signals; none can be open.

isa_d: ISA
port map(
....
ES_MON(0) => M_OUT_I(1), -- ESR
ES_MON(10 downto 1) => ES_MONI,
ES_MON(14 downto 11) => M_OUT_I(11 downto 8), -- bypass signals
ES_MON(15) => M_OUT_I(6), -- shunt
....

Can't say about the original question though. I have not tried that.

--
My real email is akamail.com@dclark (or something like that).

 

[Niels Bakker]

M.A.Khader wrote:

HI,

I was solving the following question and came up with a solution. I
am a beginner and sloving the exercises from Ashenden's "Designer's
guide for VHDL".
DEVELOP A BEHAVIORAL MODEL FOR A D LATCH WITH A CLOCK-TO-OUTPUT
PROPAGATION DELAY OF 3NS AND DATA-TO-OUTPUT PROPAGATION DELAY OF 4NS.

What I worte is ......
Entity D_latch IS
Port(d,clk : in std_ulogic;
q : out std_ulogic);
End entity D_latch;
Architecture behave of D_latch is
Begin
latch: Process is
Begin
if(clk='1') then
q<=d after 4ns;
end if;
wait on clk,d;
end process latch;
End architecture behave;
I am not able to incorporate clock-to-output delay of 3 ns. Where
should I insert this delay to emulate this .

Thanks in advance.

Regards,
akfami.

Might this be something?

--Niels Bakker

library ieee;
use ieee.std_logic_1164.all;

Entity D_latch IS
Port(d,clk : in std_ulogic;
q : out std_ulogic);
End entity D_latch;

Architecture behave of D_latch is
Begin
latch: Process is
Begin
if clk='1' then
if d'event then -- latch transparent and change of data
q<=d after 4 ns;
elsif clk'event then -- latch is being enabled
q<=d after 3 ns;
end if;
end if;
wait on clk,d;
end process latch;

end architecture behave;

 

[Ralf Hildebrandt]

M.A.Khader wrote:

latch: Process is
Begin
if(clk='1') then
q<=d after 4ns;
end if;
wait on clk,d;
end process latch;

I am not able to incorporate clock-to-output delay of 3 ns. Where
should I insert this delay to emulate this .

Take the template for synthesizable latches:

process(clk,d)
begin
if(clk='1') then
q<=d;
end if;
end process;

Remember: There is no reset included.
If you want to apply a delay for simulation:

process(clk,d)
begin
if(clk='1') then
q<=d after 3 ns; -- not synthesizable
end if;
end process;


Ralf

 

[Egbert Molenkamp]

"Mike Treseler" <mike_treseler@comcast.net> wrote in message
news:865ab498.0408170940.7563599d@posting.google.com...

I think the OP's original problem is not slicing, but
interrupting the assending indexes in the instance.

A PhD student today had the same problem. The order changed and it worked!
I read the VHDL-93 standard on page 63 line 508 (also in VHDL-2002)

"Furthermore, every scalar subelement of the explicitly declared interface
object must be associated
exactly once with an actual (or subelement thereof) in the same association
list, and all such associations
must appear in a contiguous sequence within that association list."

I think that the last part "contiguous" requires that the "interruption" is
not allowed.
Based on that I think that ModelSim seems to be correct (and thus Xilinx is
not).

Egbert Molenkamp

 

[Jonathan Bromley]

On 20 Aug 2004 08:41:07 -0700, pshanker@ciena.com (Pankaj) wrote:

Anyone know how to specify default value to a variable of
unconstrained type
INSIDE a VHDL procedure ?
For example,

type t_HEADER_LENGTH_array is array (natural range<&gt of integer ;
-- unbounded array of integers

procedure provision_EHI_RAM(
variable headerLength : t_HEADER_LENGTH_array (0 to
ci_NUMBERofHEADERS-1) := (14,2);
...)

compiles with error:
** Error: .\rtl\gbe_wan_tb_defn_pkg.vhd(2361): Parameter default
values do not conform between declarations in package header an
d body: 'headerlength'.

That's not a local variable of the procedure; it's an input
parameter of class variable.

Input parameters of variable class are, as far as I know,
legal but useless. You can't change their values, because
they are of mode "in", so you might as well make the parameter
be of constant class, so that you can supply an expression
rather than a variable as the actual parameter.

If you take off the keyword "variable", and make sure that
the aparameter list is *exactly* the same in both the
package and package body, then it should be OK.

If you want a local variable of the procedure, visible only
within the procedure, that's easier: don't declare it in
the parameter list, but instead declare it in the procedure
body's declarative region:

(package)
procedure provision_EHI_RAM (...);

(package body)
procedure provision_EHI_RAM (...) is
variable headerLength: t_HEADER_LENGTH_array.......
begin
...
end;

Finally, I spy trouble ahead...

variable headerLength :
t_HEADER_LENGTH_array (0 to ci_NUMBERofHEADERS-1)
:= (14,2);

The variable initialisation will work correctly only if
ci_NUMBERofHEADERS) is exactly 2. Can you be sure of this?
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[rocky30]

Hai David,
I tried the link what u gave but i am unable open usb2.zip.
Please can u send in a copy of it from ur folder.My e-mailid is
rakesh_eng@yahoo.com.
Thanks
Rakesh

 

[anupam]

Hi Pankaj,
You have to fix the NUMBERofHEADER here as 2 in a package entity. only
then u will be able to compile the same.
Anupam Garg

 

[Tuukka Toivonen]

In article <c9cb3993.0408231433.11fd4ed6@posting.google.com>, Viswan wrote:

purpose. While coding in VHDL can I just represent this value of
1.7895 as some 'signal' and assign this constant value to that signal
as follows:
signal exvalue : std_logic_vector (15 downto 0);
exvalue <= "0001.........1";

Yes, you can. No synthesizer should have problems with that.

Or you could use "when" to select correct constant:

m <= "101010101" when STATE=CONST1 else "101111101";

or a "process" statement with case...end case.

 

[Marcus Harnisch]

ALuPin@web.de (ALuPin) writes:

My question:
Why do the addresses on the local interface "local_col_addr"
"020","021","022","023","030","031","032","033"
turn to the memory addresses
"0040","0042","0044","0046","0060","0062","0064","0066" on the DDR
SDRAM Interface ?

It is said later in the User Guide that the controller runs the DQ
port to the DDR devices at one half the width and twice the rate of
the DATAIN port (input data at the local interface of the
controller).

But how are the coherence with the shown example addresses?

Because the internal interface has a data width of sixteen bit while
the the SDRAM interface is only eight bits wide...

--Marcus

 

[Jonathan Bromley]

On 25 Aug 2004 00:34:59 -0700, peter.hermansson@sts.saab.se (Peter
Hermansson) wrote:

Hi,

I am rather confused about the use of procedures in testbenches. My
intention is to model an I2C-bus with pullup resistors. My testbench
consists of a testprocess with a couple of procedures;reset, do
something, check that, do something else, check that etc.
If I set the I2C SCL and SDA line to 'H' in the reset-procedure and
then to '0' in another later procedure, everything is fine. But if set
them to 'H' outside the test-process, in the parallell part of the
code, both are 'U' from the very beginning of the simulation.
Both SCL and SDA are declared std_logic so why isnt the conflict
between 'H' and '0' resolved? And why are they 'U' from the beginning,
not just from the point in time were they are set to '0'?

Every process in VHDL represents a driver on each signal assigned
within that process. Continuous assignments, like your external
pullup assignments, are processes too. So, at time 0 you have
your pullup process assigning 'H', and your test process assigning
the initial value of the signal, which is 'U'. Since 'U' is the
strongest of all std_logic values, you see 'U' until the test
process assigns a different value.

Since it's a test bench, one possible solution is to give the I2C
signals initial values:

signal SCL, SDA: std_logic := 'H'; -- or 'Z' if you have a pullup

This means that the initial value of SCL and SDA *in every process
that drives them* is 'H'.

I don't really see why the external pullup process is useful. Your
test process must drive the signal to '0' when it wants zero, and
then to either 'H' or 'Z' when it wants the pullup to drive 1.
Consequently, you save yourself nothing by adding the external
pullup process.

HTH
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[ivailokroumov]

I am sure that these books are very good for beginners, and I wish to post
other book that is very interesting for juniors and seniors. The name is:
"VHDL Starter's guide"
The autor is Sudhakar Yalamanchili

 

[Jonathan Bromley]

On 25 Aug 2004 15:33:23 -0700, orbe7947us@yahoo.com (Chad) wrote:

Hi Johnathan. Sorry, I wasn't specific enough, so the answer seems
obvious. "param" is actually an array of 8-bit std_logic_vector's:

generic(pnum : integer := 24);
.
.
.
PARAMS : out std_logic_vector(pnum*8-1 downto 0);
.
.
.
type param_array is array(0 to pnum-1) of std_logic_vector(7 downto
0);

signal param : param_array;

So, I'm trying to concatenate all the individual "param"s to form
PARAMS, generically. The ordering of bits in PARAMS is not a problem
at this point. Any improvements to the clunky code is appreciated.

OK, sorry, now I understand. You have an array of arrays, and you
need to flatten them to a single wide array.

Assuming all the subscripts go in a sensible order (and if they
don't, you can easily fix it with alias or intermediate variables):

process (param)
constant wordsize: positive := 8; -- probably defined elsewhere
constant wordmax : integer := wordsize-1;
begin
for word in param'range loop
PARAMS(wordsize*word + wordmax downto wordsize*word)
<= param(word);
end loop;
end process;

If you need to do this a lot, it might be a good idea to write
an array-flattening function...

HTH
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Alex Gibson]

"Unibus" <unibus@gmail.com> wrote in message
news:cgcffk$ea2@odak26.prod.google.com...

I have the problem with the selection of a suitable book for learning
VHDL. I've Googled, looked at the Amazon reviews, checked out the FPGA
groups and still don't have a satisfactory answer.

I've done chip level work on mainframes, maintained microprogramed and
state machines (if you accept DEC LA180 printers), done some small
design work, like the Mick & Brick bit-slice text, have manufacturer's
data books, etc. Played with network protocols for some years so my
reference library has the standard Cisco texts, Stevens' TCP/IP
Illustrated, etc. Can write microcode if somebody twists my arm. I
don't need the standard introductory material that is required for the
target audience of some books. Alternatively I'm not looking for a
cookbook that has lots of fragments. I would not be approaching VHDL as
a 'computer' language for hardware but as a tool to implement logic if
that makes sense. Hence my problem of buying a book sight unseen is the
contradictory reviews.

Anyone have some thoughts?

Regards,
Garry

Have a look at confluence , may be of interest to you as well.
http://www.confluent.org/

 

[Niels Bakker]

Helle Dev,,

LFSRs are used to create pseudo random sequences.
You can create a random sequence which repeats in 255 cycles with an 8
bits wide LFSR, by feeding certain bits in that register back to the
first bit. Usually done via an XNOR or XOR gate.

You can find the necessary tap-positions in the xapp052.pdf document of
Xilinx. (Google) or:

direct.xilinx.com/bvdocs/appnotes/xapp052.pdf

Good luck!

Niels Bakker

Javier Castillo wrote:

Hello:

I suppose you talk about a LFSR, a linear feedback shift register.
In hardware is primarily used for generate pseudo-random number sequences.

If you look in google LFSR you will find lot of information about them

Regards

Javier Castillo
jcastillo@opensocdesign.com


unisol44@gmail.com (Dev) wrote in news:78403711.0408252022.165c5da1
@posting.google.com:


Hi all,


Could you pls explain what LSFR is ?
or where can I obtain some information on them.

thanks in advance

Dev

 

[Jonathan Bromley]

On Thu, 26 Aug 2004 11:05:18 +0200, Niels Bakker
<Niels.Bakker@zonnet.nl> wrote:

LFSRs are used to create pseudo random sequences.

But be careful...

LFSRs are quite good for creating random streams of
*bits*. They are rubbish for creating random
streams of *numbers*, because the LFSR register
value is highly correlated from one sample to the
next. If you want a new random *number* from an
LFSR, you must clock it as many times as there
are bits in your desired number.

LFSRs are great in hardware, because they map on
to such a simple and fast hardware structure. But
in a test fixture, the various linear-congruential
and other numerical recipes for random numbers are
likely to be more efficient, and will also provide
better-quality random numbers. The UNIFORM
procedure in IEEE.MATH_REAL does the job, and spares
you the very great pain of understanding the maths
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Javier Castillo]

Hello:

I suppose you talk about a LFSR, a linear feedback shift register.
In hardware is primarily used for generate pseudo-random number sequences.

If you look in google LFSR you will find lot of information about them

Regards

Javier Castillo
jcastillo@opensocdesign.com


unisol44@gmail.com (Dev) wrote in news:78403711.0408252022.165c5da1
@posting.google.com:

Hi all,


Could you pls explain what LSFR is ?
or where can I obtain some information on them.

thanks in advance

Dev

 

[Jonathan Bromley]

On 26 Aug 2004 04:48:49 -0700, niko@mtl.t.u-tokyo.ac.jp
(Niko D. Barli) wrote:

I am trying to use VHDL's RAND function in my test benches.
In Synopsys VCS the function is defined in IEEE.math_real.
However, I couldn't find it in Modelsim 5.7c. Is the function
defined in other package ? Or, is it because Modelsim doesn't
support random generation ?

No, it's because there is no RAND function in the standard
IEEE.math_real package. I guess it was invented by
Synopsys for users' convenience.

The standard random generator in IEEE.math_real is the
UNIFORM procedure. To use it you must provide two
variables of type POSITIVE (note: variables, NOT signals)
to hold the seed values for the generator. You also
provide a REAL variable to hold the random result.
Then, whenever you want a random number, you invoke

UNIFORM(seed1, seed2, rand);

and in "rand" you get a REAL value in the range
0.0 to not-quite 1.0. You can then massage this value
in any way that takes your fancy to get the random
distribution you require. You could probably
use this to re-implement the Synopsys RAND function,
but that gets us into the unhappy land of IMPURE
functions and shared variables...
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.