EDK : FSL macros defined by Xilinx are wrong

[Ray Andraka]

The problem with the multiplier block approach is that the
construction is predicated on the specific coefficients. As
a result it is considerably harder to use for an arbitrary
set of coefficients. It may reduce area over a straight FIR
filter running at the same clocks per sample, but at a
considerable cost in design time and flexibility. You also
give up regularity in the structure, which may reduce the
overall performance. Essentially what the block multiplier
and distributed arithmetic approaches are is a rearrangement
of the bitwise product terms. The mutliplier block takes
advantage of duplicate terms by adding the inputs before
they are multiplied by the term.

Michael Spencer wrote:

Hello,

Has anyone compared FPGA implementations of full-rate
digital FIR filters based on the use of Multiplier Blocks
vs. traditional FIRs with constant coefficient
multipliers? By full rate, I mean: one output result per
clock cycle and no interpolation or decimation.

For anyone not familiar, a multiplier block is a network
of shifters and adders that performs multiplications by
several coefficients efficiently by exploiting common
sub-expressions. The multiplier block can be exploited in
FIR filters by transposing the standard filter so that the
products of all the coefficients with the current
input-sample are required simultaneously.

Also, by representing the coefficients in the
Canonical-Signed-Digit number system (a small number of
+1 and -1’s) along common sub-expression sharing the
multiplier block can get even smaller.

For example, the multiplier block for a 100 tap FIR filter
(fp=0.10 and fs=0.12) can be realized with only 61 adds
(zero explicit multiplications). See filter example #4 in
“FIR Filter Synthesis Algorithms for Minimizing the Delay
and the Number of Adders,”
http://ics.kaist.ac.kr/~dk/papers/TCAD2001.pdf
If the adder depth is constrained to a maximum of four,
then the authors’ algorithm can do the multiplier block in
69 additions.

It would seem that this approach would be very efficient
in a target such as the Xilinx Spartan-IIE (with no
dedicated multipliers).

Another question: If we only need one result per K clock
periods (K ~= 1000 for audio applications), could a
multiplier block approach realized with, say, bit-serial
addition be more efficient than some other approach such
as distributed arithmetic?

Comments welcome. Thanks.

-Michael
______________________
Michael E. Spencer, Ph.D.
President
Signal Processing Solutions, Inc.
Web: http://www.spsolutions.com

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin
Franklin, 1759

 

[rickman]

Bob Perlman wrote:

Whoever said, "If you require noise to shift you out of metastability,
then the people who argue that more noise will get you out quicker
could then be right," could you explain further? Are you saying that
noise is required to resolve the metastable state, or is this a
counter-argument to the "noise may get you out faster" claim? Or is
it something else entirely?

I guess this was not well stated. This was in response to someone else
who seemed to be saying that noise is needed to get out of
metastability. Just before this I believe I spoke about the perfect
balance point being so small that it was not significant. So noise is
not really needed. The quote above was to say that if noise really is
required, then the advocates of more noise may be right. But my point
is that noise is not needed since there is virtually never a "perfect"
balance.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[rickman]

Luiz Carlos wrote:

If you think there is no uncertanty in measuring the spin of an
electron, you need to go back to school.

Rick, I din't say that. I said electron spin does not presents
metastability.

It does not matter in the least what state the electron is in.
Metastability is a measurement problem. When you try to measure the
state of a FF with a gate or second FF, that is where metastability is
an issue. The first FF is in a state where the voltage will ultimately
resolve itself to a final value. So the issue of metastability is
really one of measuring the state well enough to resolve the final state
of the FF. Just like the metastability was created by the inability of
the FF to measure the state of the input at the sampling time.

Electron spin has all the same measurement issues that a FF has. If the
state of the electron spin is changing as the measurement is made, then
what state is it in? What will be the result of the measurement?

Anyway, did you hear about spintronics? Maybe the scientists behind
this idea may go back to school too!

Look at
http://www.eetimes.com/story/OEG20001221S0035
Cut and paste please, I don't know how to include hypertexts.
I think that shows my whole point of view: if you believe, insist!

Unhappily (for me) I could not find the text about the electron
position.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[rickman]

Glen Herrmannsfeldt wrote:

"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3F50A0E8.15AAA082@yahoo.com...

(snip regarding the DEC KA-10, metastability, and self-timed logic)

I am no expert in async logic, but I have never heard of a circuit that
can even detect metastability. I also thought that async logic did not
"measure" the time it took for a calculation, it simply allowed
different times for different calculations. The control path for a
given circuit has a longer delay than the data path and would be
dependant on the calculation being performed. How exactly would a
circuit detect when an async calculation is complete?

Well, I agree with the skepticism in the first place, but consider a CPU
with lights indicating the current contents of the registers. Normally, the
values will be changing very fast. If they suddenly stop changing, it could
be because of unresolved metastability. The logic will wait quietly for it
to resolve, and then continue.

I don't see how this is possible. You are assuming that the CPU has
some way to measure that a FF output is metastable. I don't know of any
way of doing that. How is this circuit designed?

It might be, though, that the machine is in I/O wait, and there really is
nothing to do. I never got to actually see the machine, but at the time
many machines had console lights, at least for the instruction counter and a
few other important registers. (Though I don't believe that the PDP-10 had
a wait state like IBM S/360 did, where no instructions were executed.)

It is also possible that the lights are not a valid indication of the
state of the CPU. Since the CPU runs at thousands of times faster than
the eye can see, it is entirely possible that a loop is being executed
that makes the lights appear to be lit, but are actually flashing much
faster than you could see. If the duty cycle is high for each light
that is flashing you would not see a dimming either.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Ray Andraka]

Noise is not needed, but it may help to accelerate departure from the
balance point shortening the metastable period. On the other hand, noise
can also work the other way pushing the Q point closer to the balance point
thereby delaying recovery. As a result, noise has no net effect on the
metastable probabilities.

rickman wrote:

Bob Perlman wrote:

Whoever said, "If you require noise to shift you out of metastability,
then the people who argue that more noise will get you out quicker
could then be right," could you explain further? Are you saying that
noise is required to resolve the metastable state, or is this a
counter-argument to the "noise may get you out faster" claim? Or is
it something else entirely?

I guess this was not well stated. This was in response to someone else
who seemed to be saying that noise is needed to get out of
metastability. Just before this I believe I spoke about the perfect
balance point being so small that it was not significant. So noise is
not really needed. The quote above was to say that if noise really is
required, then the advocates of more noise may be right. But my point
is that noise is not needed since there is virtually never a "perfect"
balance.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Glen Herrmannsfeldt]

"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3F550C7E.6A451965@yahoo.com...

(snip)

I don't see how this is possible. You are assuming that the CPU has
some way to measure that a FF output is metastable. I don't know of any
way of doing that. How is this circuit designed?

There are books, and probably web sites explaining self timed logic, or
asynchronous logic.

There are no clocks, but it takes more wires for each signal. Designing is
completely different than synchronous logic designs, which means that the
current design tools don't help very much. I don't know it well enough to
explain here, though.

-- glen

 

[rickman]

Glen Herrmannsfeldt wrote:

"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3F550C7E.6A451965@yahoo.com...

(snip)

I don't see how this is possible. You are assuming that the CPU has
some way to measure that a FF output is metastable. I don't know of any
way of doing that. How is this circuit designed?

There are books, and probably web sites explaining self timed logic, or
asynchronous logic.

There are no clocks, but it takes more wires for each signal. Designing is
completely different than synchronous logic designs, which means that the
current design tools don't help very much. I don't know it well enough to
explain here, though.

Yes, everything I have read (which is not a lot) simply relies on the
control path (the clock) to have a longer delay than the data path. So
the data will always reach the next stage before the control saying the
data is ready.

There is no way to determine when a circuit is metastable or not. Async
circuits are not magic, they just depend on predictable delays, just
like any other circuit. The design is different because there is no
common clock so each circuit can run with its own delay. Since the next
circuit will take the output when it is ready, there is no problem with
synchronization.

One problem I do see is that if each stage has a different delay, then
it can not accept a new input from the preceding stage until the output
has been taken by the following stage. It seems in the end the async
circuit will run no faster than the slowest stage, which is what the
sync clocked circuit will do.

But I have not read about it much, so perhaps there is more to it than
just this. But without design tools or any expectation of using it
soon, there is not much incentive to spend much time reading up on it
now.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Duane Clark]

Theron Hicks wrote:

Hello,
Is there a way that I can (within ISE 5) use a different editor? I want
the editor to be integrated into the ISE system but I want to use a
different editor. The feature that I most want is automatic formating of
indents, etc. ISE does a good job, but if I screw up when I put in a new
block of code I want to add auto-indent (like that available in Matlab).
Folks at Xilinx.... Take this as a hint.

Why does it have to be "within ISE"? If you edit a file with an external
editor and save it, ISE will see that it has changed and will get rid of
all the green check marks to indicate the project has to be recompiled.

--
My real email is akamail.com@dclark (or something like that).

 

[rickman]

Luiz Carlos wrote:

Electron spin has all the same measurement issues that a FF has. If the
state of the electron spin is changing as the measurement is made, then
what state is it in? What will be the result of the measurement?


Rick, the electron spin is +1/2 or -1/2, there is no in between state,
it changes instantaneously (in one fundamental clock tick, ~10^-43
seconds).

Luiz Carlos

But the measurement is not instantaneous. So the transistion could
occur during a measurement. Result... inconclusive measurement which is
what metastability is all about.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[rickman]

"Nicholas C. Weaver" wrote:

In article <3F559A3F.91184B1A@yahoo.com>,
rickman <spamgoeshere4@yahoo.com> wrote:

There is no way to determine when a circuit is metastable or not. Async
circuits are not magic, they just depend on predictable delays, just
like any other circuit. The design is different because there is no
common clock so each circuit can run with its own delay. Since the next
circuit will take the output when it is ready, there is no problem with
synchronization.

Silly question: I don't see why an ANALOG flip-flop couldn't determine
that it is in the intermediate state at some fixed interval after the
clock, and then force the flop one way or another. Of course, it
might double-glitch in the meantime (flop goes up before logic forces
it down), but it would make a flop with a fixed-maximum metastabel
interval.

Of course, it seems like such a massive headache to do.

If you don't see the problem it is because you are not looking hard
enough. The issue with metastability comes from trying to measure the
state of a FF or other digital voltage. When a signal is at an
intermediate value a measurement can be inconclusive. Your ANALOG FF
can be just as inconclusive as the digital FF. Besides, the result is
always digital (or more accurately, discreet instead of continuous).

You are suggesting that you add a third state to the measurement, but
you get the same inconclusive measurement between the metastable state
and either the one or the zero states. The result is that the output of
your ANALOG FF would be indeterminate which could result in
metastability in the next stage.

If I am not grasping your idea, then please provide more details.

One problem I do see is that if each stage has a different delay, then
it can not accept a new input from the preceding stage until the output
has been taken by the following stage. It seems in the end the async
circuit will run no faster than the slowest stage, which is what the
sync clocked circuit will do.

The trick with asynchronous logic is that the longest stage WHICH IS
IN THE COMPUTATION is the critical path. EG, if 9 of the stages take
1 ns, and the last takes 2ns, but the last only affects 1/2 the data,
with the asynchronous circuitry doing the shortcutting, it will be
considerably faster than the synchronous one.

Except that sync designs can do the same thing. A multiply accumulate
typically takes twice as long as the other ops in a calculation. So
they split it into two stages running at full speed. Or if only half
the data needs the MAC, then they can do nothing since this will run at
full speed.

The problem is: You can automatically balance the pipelining
(retiming) for a synchronous circuit, while asynchronous really playes
havoc with the CAD flow and testing.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Daniel Lang]

"Nicholas C. Weaver" <nweaver@ribbit.CS.Berkeley.EDU> wrote in message
news:bj59us$55k$1@agate.berkeley.edu...

The flip flop core exists in one of THREE states: Vdd, Vss (the stable
points) and Vms +/- epsilon (the metastable range, in between Vdd and
Vss).

The analog circuitry in the flip flop measures the flip-flop state at
Tdelay after the clock edge.

If it is within Vms +/- a large epsilon (that is, metastable at this
point in time), the analog circuitry forces the flip-flop to Vss, and
also signals that a metastable capture/correction was performed.
nweaver@cs.berkeley.edu

The problem is that the analog circuitry that is trying to determine if
the flip-flop is in a metastable state can itself go metastable if the
flip-flop level is near Vms +/- epsilon.

Daniel Lang

 

[rickman]

"Nicholas C. Weaver" wrote:

In article <3F56292C.E9F89B7F@yahoo.com>,
rickman <spamgoeshere4@yahoo.com> wrote:
"Nicholas C. Weaver" wrote:
If you don't see the problem it is because you are not looking hard
enough. The issue with metastability comes from trying to measure the
state of a FF or other digital voltage. When a signal is at an
intermediate value a measurement can be inconclusive. Your ANALOG FF
can be just as inconclusive as the digital FF. Besides, the result is
always digital (or more accurately, discreet instead of continuous).

You are suggesting that you add a third state to the measurement, but
you get the same inconclusive measurement between the metastable state
and either the one or the zero states. The result is that the output of
your ANALOG FF would be indeterminate which could result in
metastability in the next stage.

If I am not grasping your idea, then please provide more details.

The flip flop core exists in one of THREE states: Vdd, Vss (the stable
points) and Vms +/- epsilon (the metastable range, in between Vdd and
Vss).

The analog circuitry in the flip flop measures the flip-flop state at
Tdelay after the clock edge.

If it is within Vms +/- a large epsilon (that is, metastable at this
point in time), the analog circuitry forces the flip-flop to Vss, and
also signals that a metastable capture/correction was performed.

This may cause a spurrious transition (eg, the metastable state is
measured, it goes high, and then the post-measurement kick drags it
back down to Vss).

You are not accounting for the fact that the voltage is being measured
by the analog circuit and it can not distinguish between the metastable
state and the non-metastable states any better than the original FF
could distinguish the two valid states. If the voltage is at the cusp
of the metastable range, the analog circuit will have an invalid or
indeterminate output and will not drive the FF to a valid state. In
fact, it may drive the FF back toward a state with an even longer
transistion time.

This is very circular. Each measurement has a range in which the
measurement is indeterminate within a given amout of time. That is the
nature of metastability. It is not just the state of the FF. The FF
became metastable because it could not measure the input to be either a
1 or a 0. Trying to measure the state of the FF has the same problem,
ad infinitum.

The trick with asynchronous logic is that the longest stage WHICH IS
IN THE COMPUTATION is the critical path. EG, if 9 of the stages take
1 ns, and the last takes 2ns, but the last only affects 1/2 the data,
with the asynchronous circuitry doing the shortcutting, it will be
considerably faster than the synchronous one.

Except that sync designs can do the same thing. A multiply accumulate
typically takes twice as long as the other ops in a calculation. So
they split it into two stages running at full speed. Or if only half
the data needs the MAC, then they can do nothing since this will run at
full speed.

The promise of the asynchronous is that this can occur on a much finer
grain, eg if all the ops are 1 ns, but the final one is either 1 or
1.5 ns.

Of couse, it has never really lived up to this promise, mostly because
the handshaking overhead can be severe, as well as the other problems
(CAD, testing).
--
Nicholas C. Weaver nweaver@cs.berkeley.edu

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Nicholas C. Weaver]

In article <3F56292C.E9F89B7F@yahoo.com>,
rickman <spamgoeshere4@yahoo.com> wrote:

"Nicholas C. Weaver" wrote:
If you don't see the problem it is because you are not looking hard
enough. The issue with metastability comes from trying to measure the
state of a FF or other digital voltage. When a signal is at an
intermediate value a measurement can be inconclusive. Your ANALOG FF
can be just as inconclusive as the digital FF. Besides, the result is
always digital (or more accurately, discreet instead of continuous).

You are suggesting that you add a third state to the measurement, but
you get the same inconclusive measurement between the metastable state
and either the one or the zero states. The result is that the output of
your ANALOG FF would be indeterminate which could result in
metastability in the next stage.

If I am not grasping your idea, then please provide more details.

The flip flop core exists in one of THREE states: Vdd, Vss (the stable
points) and Vms +/- epsilon (the metastable range, in between Vdd and
Vss).

The analog circuitry in the flip flop measures the flip-flop state at
Tdelay after the clock edge.

If it is within Vms +/- a large epsilon (that is, metastable at this
point in time), the analog circuitry forces the flip-flop to Vss, and
also signals that a metastable capture/correction was performed.

This may cause a spurrious transition (eg, the metastable state is
measured, it goes high, and then the post-measurement kick drags it
back down to Vss).

The trick with asynchronous logic is that the longest stage WHICH IS
IN THE COMPUTATION is the critical path. EG, if 9 of the stages take
1 ns, and the last takes 2ns, but the last only affects 1/2 the data,
with the asynchronous circuitry doing the shortcutting, it will be
considerably faster than the synchronous one.

Except that sync designs can do the same thing. A multiply accumulate
typically takes twice as long as the other ops in a calculation. So
they split it into two stages running at full speed. Or if only half
the data needs the MAC, then they can do nothing since this will run at
full speed.

The promise of the asynchronous is that this can occur on a much finer
grain, eg if all the ops are 1 ns, but the final one is either 1 or
1.5 ns.

Of couse, it has never really lived up to this promise, mostly because
the handshaking overhead can be severe, as well as the other problems
(CAD, testing).
--
Nicholas C. Weaver nweaver@cs.berkeley.edu

 

[David R Brooks]

There was an open source project called "Camille", which was intended
to replace Mentor's "Renoir". But I haven't heard anything of it for
some time.

Jay <se10110@yahoo.com> wrote:

:Ok,
:
:This is slightly off-topic but what do people in here use to create
:their digital logic block diagrams?
:
:I am hopefully looking for something that runs on Win2000, but I'd
:consider Linux/FreeBSD alternatives.
:
:Currently I am using "SmartDraw" (www.smartdraw.com) but I find my block
:digrams look messy and it's not easy to "rubber band" things like clock
:signals. I sometimes like to place text in a block (i.e. "Counter") but
:also like to leave room for connections like a clock triangle (&gt and
:text for EN(able) but when I'm finished the results aren't appealing.
:
:I've also used Edge Diagrammer (from Pacesoft) and found it was "weird"
:in many respects.
:
:Both Edge and SmartDraw are annoying in one particular aspect; if a line
:is "attached" to an object, when the object is moved, instead of using
:right-angles to re-draw the lines, the connecting line is put at an
:angle.
:
:I know a lot of people in general use Visio, what is considered the
:best, most lean version of Visio? I loathe Office and especially
:anything beyond Office '97.
:
:I'm also interested to hear if anyone uses Kivo/Kivo MP.
:
:Thanks!
:Jay.

 

[Glen Herrmannsfeldt]

"Hal Murray" <hmurray@suespammers.org> wrote in message
news:vlc0kv1m4flm5f@corp.supernews.com...

Silly question: I don't see why an ANALOG flip-flop couldn't determine
that it is in the intermediate state at some fixed interval after the
clock, and then force the flop one way or another. Of course, it
might double-glitch in the meantime (flop goes up before logic forces
it down), but it would make a flop with a fixed-maximum metastabel
interval.

DING DING DING

Nobody has been able to fix metastability yet. If you really have
a fix, it's worth a Nobel Prize.

It might be that you can change the shape of the probability vs. time curve,
while keeping the area constant. That could reduce the probability of
metastability lasting too long for a given clock rate.

I don't know the physics well enough to say. Also, it might be pretty
expensive to do that.

-- glen

 

[Hal Murray]

This isn't FIXING metastability, this is detecting and responding to
it, changing an exponentially decaying bounds into a fixed bounds.

If you could build a circuit with a "fixed bounds", that would solve
the metastability problem and you would be a hero. (Just set your
clock period to that fixed bounds.)

I put metastability in the same category as perpetual motion.
I assume any proposal is wrong, even if I can't spot the problem
right away. Best one I've ever heard of was a bicycle wheel
that ran off changes in air pressure.

Yes, but the point is it would fix the maximum metastability window,
which is the key requirement, as "did the data come before or after
the clock edge" is really an irrelevant question at the metastable
capture point, you jsut want it to go to ONE or the other (not stick
around and make up its mind a half clock cycle later), and possibly to
tell you.

If you have a circuit that you think will work, please send me
the schematic. There is a reasonable chance I (or somebody here)
can find the bug in it. No promises. The thing I would look for is
runt pulses.

The best non EE-geek example of metastability I have seen is
rolling a ball over a speed bump. Left of the bump is 0. Right of
it is 1. Give it a good shove and it goes over. Give it a gentle
shove and it bounces back. For some speed, the ball will teeter on
the top for a while, then fall off one side or the other.

The initial speed of the ball corresponds to meeting setup/hold times.
If the system is continuous, there is some value in the middle that will
cause troubles. Setup/hold times and ball speed both seem continuous
to me.

--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.

 

[Martin Euredjian]

Why don't you just tell it to ignore these?

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_" = "martineu"




"David Lamb" <gretzteam_nospam@yahoo.com> wrote in message
news:bj54ns$7nr$1@home.itg.ti.com...

I found a workaround. If I add a new UCF, it seems like the old one gets
updated with the new design (with missing ports). I just add a new UCF,
delete it right away, and work with the old one.
David
"David Lamb" <gretzteam_nospam@yahoo.com> wrote in message
news:bj547c$6pr$1@home.itg.ti.com...
Hi,
I have a vhdl project and I used a UCF file to assign the package pin to
each port in the design. This works fine. However, if I change my vhdl
code
(let's say I remove an output port), I always get the following error
when
I
try to run the UCF editor:
ERROR:NgdBuild:756 - Line 3 in 'constraints.ucf': Could not find net(s)
'outputA' in the design. To suppress this error specify the correct
net
name or remove the constraint.

It seems like the UCF doesn't update itself with the new design. I tried
everything and I always have to start with a new UCF each time. The
removed
port doesn't exist in the Edit constraints (TEXT) because I didn't add
any
constraint to it. I really don't see how to do it.
Thanks
David

 

[Jon Elson]

peterzhu wrote:

Due to a chip bug, I have to extend a pulse width(negative)from 10ns
to 100ms in CPLD(Altera 7128). But the difficult is that I have no any
clock into the CPLD, so the CPLD is pure combination logic. how to
extend it in such case?

Help me!


I have delayed strobe signals several hundred nS with an external series

resistor, and used the input capacitance of the chip as the C of the RC
network. For mS, you will need an external capacitor, of course. if you
want the delay to be asymmetric (like a one-shot), you might need to
put a diode in parallel with the R. You feed the signal out one pin,
through a series R, to a pin loaded with a cap to ground, and then take
the signal in from that pin. This may cause multiple pulses with a
delay this long, however. So, you might end up using a 74HC4538
or similar one shot, or a 74HC14 Schmitt trigger to prevent the
pulses as the output of the RC crosses the threshold.

Jon

 

[Assaf Sarfati]

Jay <se10110@yahoo.com> wrote in message news:<MPG.19bf56e7871d6a089896dc@news.surfcity.net>...

Ok,

This is slightly off-topic but what do people in here use to create
their digital logic block diagrams?

I am hopefully looking for something that runs on Win2000, but I'd
consider Linux/FreeBSD alternatives.

Currently I am using "SmartDraw" (www.smartdraw.com) but I find my block
digrams look messy and it's not easy to "rubber band" things like clock
signals. I sometimes like to place text in a block (i.e. "Counter") but
also like to leave room for connections like a clock triangle (&gt and
text for EN(able) but when I'm finished the results aren't appealing.

I've also used Edge Diagrammer (from Pacesoft) and found it was "weird"
in many respects.

Both Edge and SmartDraw are annoying in one particular aspect; if a line
is "attached" to an object, when the object is moved, instead of using
right-angles to re-draw the lines, the connecting line is put at an
angle.

I know a lot of people in general use Visio, what is considered the
best, most lean version of Visio? I loathe Office and especially
anything beyond Office '97.

I'm also interested to hear if anyone uses Kivo/Kivo MP.

Thanks!
Jay.

I use Visio 5 Technical (last version before Visio was bought by MS). It
is great for all H/W design documentation - I even use it to draw waveforms
when designing interfaces. Unlike applications designed specifically to
draw waveforms, it allows to violate timing without constatly
yelling at me.

I've tried to use Visio 2000, but MS had slowed it down and screwed about
with the UI; it may be more office-compatible, but it is far less
me-compatible. I will stay with Visio 5 until I leave Windows (I use
Win2K and have no plans to ever switch to any later Windows version;
I'll switch to Linux before using WinXP and its "cute & friendly" UI).

 

[Glen Herrmannsfeldt]

"Hal Murray" <hmurray@suespammers.org> wrote in message
news:vld55e7r7pvj2e@corp.supernews.com...

This isn't FIXING metastability, this is detecting and responding to
it, changing an exponentially decaying bounds into a fixed bounds.

If you could build a circuit with a "fixed bounds", that would solve
the metastability problem and you would be a hero. (Just set your
clock period to that fixed bounds.)

(snip)

If you have a circuit that you think will work, please send me
the schematic. There is a reasonable chance I (or somebody here)
can find the bug in it. No promises. The thing I would look for is
runt pulses.

The best non EE-geek example of metastability I have seen is
rolling a ball over a speed bump. Left of the bump is 0. Right of
it is 1. Give it a good shove and it goes over. Give it a gentle
shove and it bounces back. For some speed, the ball will teeter on
the top for a while, then fall off one side or the other.

The initial speed of the ball corresponds to meeting setup/hold times.
If the system is continuous, there is some value in the middle that will
cause troubles. Setup/hold times and ball speed both seem continuous
to me.

One thing that I still remember from the first discussions about
metastability was that the sharper you make the peak, the smaller the chance
of getting into the metastable state, but the longer it stays when you get
there. I don't know if the analogy is quite right, but consider a very
sharp speed bump. It will deform the ball as it goes over, such that it
sticks more.

Not so long after that, I was taking a shower at a pool with a valve
designed not to stay on. I managed to get it into the metastable (stay on)
state, so that I could wash with both hands. (It worked just like the speed
bump, where on top of the bump the valve was on.)

-- glen