EDK : FSL macros defined by Xilinx are wrong

[Peter Alfke]

Andrew, I know, and I hope I made that clear in all my comments, App
Notes, and TechXclusives.
Metastability is unavoidable in asynchronous interfaces.
Where I differ from most correspondents: I have measured it and
described it quantitatively, using modern CMOS flip-flops.
That's why I can state with certainty that the window is 0.07
femtoseconds for a 1.5 ns delay. How often your system might change
inside that window is up to you to calculate...
Peter Alfke

Andrew Paule wrote:

Hi Peter:

the problem with metastability is probably best understood by looking
through some of the ieee papers by Dike and Burton - these guys did the
measurements and there is no solution - metastability requires thermal
noise on two nodes inside a flop(including the Xilinx model that I saw a
couple years ago) to force the output change, and that's a statistical
quantity - metastability can reign out to infinity, although the
probability is small. No solution known to us under device physics as
we know it now, just getting the probabilities smaller. This is why
hold time is just a statistic, and much like we qualify things under
BERT and jitter (more statistical quantities), we are human and guessing
our best.

Andrew

Peter Alfke wrote:

Luiz,
you need to read up on metastability.
There are things even in physics that have no solution. Perpetual motion
is one. If you want to get philosophical about metastability, read
Heisenberg's Uncertainty papers.

Phil Freidin has described the problem very well. He and I agree 100% on
the problem. But I have made quantitative tests and know the (very low)
probability. Everybody has an opinion, very few have performed measurements...

Peter Alfke
=================================
Luiz Carlos wrote:


Peter Alfke <peter@xilinx.com> wrote in message news:<3F4D17D9.5CFD8B91@xilinx.com>...


The output level of a flip-flop during its metastable time is
irrelevant. If it were in the middle ( which it isn't) we could easily
fix this with a zener diode.
The problem is timing. The Q output can - and will - change to the
opposite state at a totally unpredictable time. That's the problem:
unpredictable timing, not unknown levels.

Cascading flip-flops is the standard remedy, but it introduces latency.

Remember: Metastability causes an extra 3 ns of unpredictable delay once
in a billion years... Seems to be an affordable risk.

Peter Alfke


Peter, kind of disagree.

Of course for the designer, the problem is timing. But the timing
problem is caused by the voltage problem. If we had a well defined
voltage behavior (as I thought, but now I know I were wrong), we could
fix the timing problem (as you said for the "in the middle" problem).
Anyway, I undestood what you said.

I also disagree that the problem has no solution. As an engineer I
don't believe in no solution problems, we just don't know the
solutions yet. But this is philosophy!

Luiz Carlos

 

[Jim Granville]

Andrew Paule wrote:

Hi Peter:

the problem with metastability is probably best understood by looking
through some of the ieee papers by Dike and Burton - these guys did the
measurements and there is no solution - metastability requires thermal
noise on two nodes inside a flop(including the Xilinx model that I saw a
couple years ago) to force the output change, and that's a statistical
quantity - metastability can reign out to infinity, although the
probability is small. No solution known to us under device physics as
we know it now, just getting the probabilities smaller. This is why
hold time is just a statistic, and much like we qualify things under
BERT and jitter (more statistical quantities), we are human and guessing
our best.

The (simple) statistical models must fall down when they hit
the quantization of single electrons.
How close are we to that ?
Has anyone tried to actually plot the tail of time/probability,
to see what law it follows ?
How does this actual tail vary with temperature.

-jg

 

[Bob Perlman]

On 28 Aug 2003 12:52:11 -0700, oen_br@yahoo.com.br (Luiz Carlos)
wrote:

Nobody knows everything. Physics don't change (I hope), but the way we
model it is always evolving. Things considered impossible became
possible.

This is the classic defense of otherwise indefensible ideas. "They
said that a flying machine was impossible." "They said that Einstein
was crazy." Statements like these ignore certain realities, namely:

(a) Much of what was said to be impossible still is, and shows every
sign of remaining so. If you believe that there are laws of physics,
even laws that are somewhat at odds with the ones we now hold true,
then those laws must say that certain things can happen and others
cannot. If they don't, they aren't laws.

(b) In all of human history, most of the people "they" called crazy
were, in fact, crazy.

Luiz, it's fine with me if you want to believe that metastability can
be prevented. But for all of you folks who have been reading this
thread and wondering just what to do about metastability in your
designs, just read Philip Freidin's excellent summary and follow the
link he pointed to for more information.

Do we really want to keep repeating the same old mistakes? Woudn't it
be more fun to make some new ones?

Bob Perlman
Cambrian Design Works

 

[Nicholas C. Weaver]

In article <8471ba54.0308281344.364a2a0d@posting.google.com>,
Luiz Carlos <oen_br@yahoo.com.br> wrote:

But I remember people saying CMOS is slow, copper can't be used as
metal layer, and a better example: "We are reaching the silicon
physical limits"!

This is a kind of religion, I don't believe in "not possible", only in
"I don't know how to do".

However, there are many thing which are "NOT POSSIBLE" barring a
massive change in our understanding of basic physics and math.

It is not possible to build a perpetual motion machine ("In this house
we obey the laws of thermodynamics!").

It is not possible to measure a particle's position and velocity with
perfect precision (heisenberg uncertanty principle).

It is not possible to have two energetically stable local-minima
without an energetically-stable local maxima between them: a point of
metastibility.
--
Nicholas C. Weaver nweaver@cs.berkeley.edu

 

[Andrew Paule]

Hi Jim -

this has nothing to do with quantization, until you get into QED, but is
a matter of statistical thermal noise on two cells that are used to jam
the outputs of a flop. You need the noise, but that has nothing to do
with undergrad quantum mechanics. Read Peter's stuff - he's quite good
and knowledgable.

Andrew

Jim Granville wrote:

Andrew Paule wrote:


Hi Peter:

the problem with metastability is probably best understood by looking
through some of the ieee papers by Dike and Burton - these guys did the
measurements and there is no solution - metastability requires thermal
noise on two nodes inside a flop(including the Xilinx model that I saw a
couple years ago) to force the output change, and that's a statistical
quantity - metastability can reign out to infinity, although the
probability is small. No solution known to us under device physics as
we know it now, just getting the probabilities smaller. This is why
hold time is just a statistic, and much like we qualify things under
BERT and jitter (more statistical quantities), we are human and guessing
our best.



The (simple) statistical models must fall down when they hit
the quantization of single electrons.
How close are we to that ?
Has anyone tried to actually plot the tail of time/probability,
to see what law it follows ?
How does this actual tail vary with temperature.

-jg

 

[Greg Steinke]

Matt,
Glad to hear that your configuration is working.
Thanks for the feedback on App Note 250. We have since replaced this
App Note with a chapter in the Cyclone Handbook. The link follows:
http://www.altera.com/literature/hb/cyc/cyc_c51013.pdf

We have updated the file type descriptions in this new chapter.
There's a section called "Device Configuration Files" which describes
the file types.

Sincerely,
Greg Steinke
gregs@altera.com
Altera Corporation



matt@ettus.com (Matt Ettus) wrote in message news:<e8fd79ea.0308271334.7dab22@posting.google.com>...

The problem turned out to be in the file I was sending. I was using
an SOF, because I thought it was raw. Once I found the .rbf option, I
switched to that, and it works now. I didn't find mention of this in
appnote 250, which is on Cyclone configuration.

Thanks for your help.
Matt

 

[John Dimtsios]

Acutally Lattice does have parts larger that the XCR3512XL. If you
are looking for 256 fpBGA you can get up 768 macrocells in that
package using their ispXPLD family. Not only that but each logic
block can alternately be made into a large memory element so you will
have plenty of room to spare.



"Neeraj Varma" <neerajNOSPAMM@cg-coreel.com> wrote in message news:<3f2dc715@shknews01>...

Cypress is anyway getting out of the PLD business...
http://www.eet.com/semi/news/OEG20030730S0063


"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3F2A84FE.20106575@yahoo.com...
Marc Randolph wrote:

rickman <spamgoeshere4@yahoo.com> wrote in message
news:<3F29C212.EC74896B@yahoo.com>...
I have been given a very good price on the Coolrunner XCR3512XL, but
even with 512 macrocells, including small FIFOs (8 bits x 16 words,
two
FIFOs) uses up half the chip.
^^^^^^^^^^^^^
Unless the design is complete and you can verify that it fits AND you
have a pinout, this would scare the hell out of me. I have to admit
not having used the Coolrunnner, but over the past six years, we have
had an absolutely horrible time making very minor changes to
moderately full 95xxx series Xilinx CPLD's. Again, this may not apply
as much to the Coolrunner, since it is a completely different family -
but I'd still verify it first.

I agree with the other poster - what about the Cypress or Lattice
devices? I realize that gets you away from your "all Xilinx" board,
but is there really a good reason for desiring that (except maybe you
can get all parts from one distributor)?

No, sticking with Xilinx is not a strong desire since the software is
not common anyway. But Lattice has nothing that will fit this socket
and I have not been able to get a decent price on a Cypress part. I
guess that is also part of my goal to use Xilinx. I have gotten some
really great pricing on the parts I have discussed with them. They are
working with me, so it makes me want to work with them.

But I agree that using the XCR3512XL is scaring me as well. That is why
I am asking about other Xilinx alternatives.

I am sure I looked at the Cypress parts. I need about 170+ IOs in a 256
FBGA. The insides are not real important since that many IOs almost
always means a larger part than what I need, say 20,000 gates or 1000
LUT/FF. The memory is optional since with that many FFs I can make my
own FIFOs easily. Any idea of what a real price in a Cypress part would
run? I don't really see much that will fit the socket unless I am
missing something.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Martin Schoeberl]

Hi Antti,

2) you may also ask for Actel for APA075 it has nonvolatile config so
you probably save on the configuration. one off price for APA075 what
I have seen is 17 EUR, and I think I did see a price estimate for smallest
ProAsicPlus (eg APA075) to be around $7

Have you used the Actel FPGAs? Are there free tools? Can the flash also be

used to store additional data? Looks like a good candidate for a soft core
cpu (as for JOP

Martin
----------------------------------------------
JOP - a Java Processor core for FPGAs:
http://www.jopdesign.com/

 

[Uwe Bonnes]

Antti Lukats <antti@case2000.com> wrote:

: I guess the smallest spartan III and cyclone devices should also come down
: below 10$ but then S3-50 does not have BRAM and both Spartan and Cyclone
: do require config memory to be present what may add significant amount to
: the final price (both money as board estate, etc)

XC3S50 _will_ have BRAM, only the first batch didn't have.

Bye
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

 

[Luiz Carlos]

This is the classic defense of otherwise indefensible ideas. "They
said that a flying machine was impossible." "They said that Einstein
was crazy." Statements like these ignore certain realities, namely:

(a) Much of what was said to be impossible still is, and shows every
sign of remaining so. If you believe that there are laws of physics,
even laws that are somewhat at odds with the ones we now hold true,
then those laws must say that certain things can happen and others
cannot. If they don't, they aren't laws.

Hi Bob,
Which laws?
Classical physics laws, like every other, have a domain where they
give better approximations. We are still trying to find the Theory Of
Everything.
Peter has mentioned the "Heisenberg's Uncertainty Principle", but I
read somewhere, althought we can't know where a particle is in a
momentum, we can know where it is not, so, we can infer where it is.
If we take the electron spin, there is no metastability. It changes
it's direction in one "fundamental" clock cycle (time is not
continuous). I think there is also no metastability problems in Single
Electron Devices. So, Virtex436 possibly will not have metastability
problems.

(b) In all of human history, most of the people "they" called crazy
were, in fact, crazy.

Luiz, it's fine with me if you want to believe that metastability can
be prevented. But for all of you folks who have been reading this
thread and wondering just what to do about metastability in your
designs, just read Philip Freidin's excellent summary and follow the
link he pointed to for more information.

Do we really want to keep repeating the same old mistakes? Woudn't it
be more fun to make some new ones?

Bob Perlman
Cambrian Design Works

Bob, I know that everything I said don't help us with our today
metastability problems. I spent a lot of time trying to defend my
opion about something that is not related to the topic, fruitless!
I'll try to not repeat the same mistake.
I agree with you about Philip, it really looks like he knows a lot.
Thanks to everybody, I learned a lot about metastability.

Luiz Carlos

 

[CB]

On 27 Aug 2003 23:55:31 -0700, catfist2003@yahoo.com (John Lee) wrote:

Hi all,

What is the price for a maximux of 50K system gates, IO counts is not
an issue, with more than 100K volumn per year? We look at cyclone and
spartan series because Xilinx and Altera claimed they are cheap.

100K is the minimum.

Thanks,
John

for this volume you will obviously need to contact the disti/factory
but for the Cyclone the quantity 50K pricing from the disti as below.
better deals may be found I suspect if the volume goes up a bit and in
2004 ...

EP1C3 $5 , EP1C4 $11 , EP1C6 $13 , EP1C12 $27 , EP1C20 $60

 

[Martin Schoeberl]

snip
I guess the smallest spartan III and cyclone devices should also come
down
below 10$ but then S3-50 does not have BRAM and both Spartan and Cyclone
do require config memory to be present what may add significant amount
to
the final price (both money as board estate, etc)
/snip

It's only the engineering samples of the S3-50 that doesn't have BRAM (or
DCMs for that matter) but the production version will be fully outfitted.
Check the Xilinx site for the latest info.

If the system already includes a controller and flash and can get by
without
a programmed FPGA for a short time, the flash can take the place of the
config memory by allowing the controller (processor, whatever) to program
the device.


The cheapest way for the configuration is using a standard flash and a small

PLD (like max7032 or max7064) and you can use the rest of the flash for
other data (like program for a soft core cpu).

Martin
--
----------------------------------------------
JOP - a Java Processor core for FPGAs:
http://www.jopdesign.com/

 

[Peter Alfke]

The smallest Spartan3 part, the -50 came out without BlockRAM and DCMs,
but only in its rushed "early silicon" a.k.a. "engineering samples"
form. The real part, coming later this year, will have BRAMs and DCMs,
just like all its larger brothers do.

Peter Alfke
================
Antti Lukats wrote:

snip> I guess the smallest spartan III and cyclone devices should also come down
below 10$ but then S3-50 does not have BRAM and both Spartan and Cyclone
do require config memory to be present what may add significant amount to
the final price (both money as board estate, etc)

antti

 

[Jay]

David,

It's better for you not using the Architecture Wizard and instantiate the
DCM by yourself.
I guess it was just developped and has some bugs.
For another example the jitter calculator also could not work fine.

"David Lamb" <gretzteam_nospam@yahoo.com> Đ´ČëĎűϢĐÂÎĹ
:bill3u$852$1@home.itg.ti.com...

Hi,
I'm using a virtexII and I'm trying to use the Architecture wizard to
divide
a clock by 5. However, the divided clock rising edge is aligned with the
falling edge of my input clock. Is this normal or I'm doing something
wrong
in the Architecture wizard? How can I have both rising edge aligned?

Here are the parameters I use
Input clock: 26Mhz, External
Divide by 5
Feedback: internal, 1X
Duty cycle correction: yes
Phase shift: none.

Thank you very much
David

 

[Pawel Kolodziej]

In article <a2214fd40dcc30b0380a43f3441e0804@news.teranews.com>, Rene Tschaggelar wrote:

Yes.
I'd get the peche melba by saving my time by not spending a
few hours on the internet looking for free samples of 4$ parts.

Could someone tell me what is price of Altera Cyclone devices ?
In Poland EP1C3T100C7 costs about 30$ (When I want to buy only 1
piece). I think it's to expensive.

Thank you,
Pawel

 

[rickman]

Glen Herrmannsfeldt wrote:

"Richard Iachetta" <iachetta@us.ibm.com> wrote in message
news:MPG.19b83b577df3e40d989823@ausnews.austin.ibm.com...
In article <rzt3b.288788$uu5.63948@sccrnsc04>, gah@ugcs.caltech.edu
says...
I used to hear stories, though I am not sure that I believe them, of
people
seeing metastability effects on the PDP-10 (KA10), which used self timed
logic. Supposedly they could see it stop processing, and then start
again
with no ill effect. How they know it wasn't in I/O wait, or some other
such
state, I have no idea.

Sorry for being skeptical, but they "saw" it stop processing for
approximately
10 to 100 ns that the metastability would resolve and then they saw it
start
again?

Well, I am skeptical, too, but logic was somewhat slower in those days, and
the resolving time may be much longer. Not that logic speed and resolution
time are proportional. Also, the metastability pathways in self-timed
logic are somewhat different.

I am no expert in async logic, but I have never heard of a circuit that
can even detect metastability. I also thought that async logic did not
"measure" the time it took for a calculation, it simply allowed
different times for different calculations. The control path for a
given circuit has a longer delay than the data path and would be
dependant on the calculation being performed. How exactly would a
circuit detect when an async calculation is complete?

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[rickman]

Luiz Carlos wrote:

But I remember people saying CMOS is slow, copper can't be used as
metal layer, and a better example: "We are reaching the silicon
physical limits"!

This is a kind of religion, I don't believe in "not possible", only in
"I don't know how to do".

This has nothing to do with the problem. There is nothing you can do
with gates or noise or voltage to solve it. But to understand that, you
need to go beyond these things and consider the problem from a
theoretical viewpoint.

Take a look at a graph of energy (or voltage) levels of a bi-stable
function. If you analyze the behavior of varying amount of energy being
applied, you will find that the time it takes to return to one of the
minimum energy level states is indeterminate. There is nothing you can
do to add gates or noise or voltage, this is a basic property of
bi-stable systems... even quantum mechanical ones!

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[rickman]

Yes, but the 5 volt tolerance is limited to 64 pins. This may or may
not be an issue with a given design.

John Dimtsios wrote:

Acutally Lattice does have parts larger that the XCR3512XL. If you
are looking for 256 fpBGA you can get up 768 macrocells in that
package using their ispXPLD family. Not only that but each logic
block can alternately be made into a large memory element so you will
have plenty of room to spare.

"Neeraj Varma" <neerajNOSPAMM@cg-coreel.com> wrote in message news:<3f2dc715@shknews01>...
Cypress is anyway getting out of the PLD business...
http://www.eet.com/semi/news/OEG20030730S0063


"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3F2A84FE.20106575@yahoo.com...
Marc Randolph wrote:

rickman <spamgoeshere4@yahoo.com> wrote in message
news:<3F29C212.EC74896B@yahoo.com>...
I have been given a very good price on the Coolrunner XCR3512XL, but
even with 512 macrocells, including small FIFOs (8 bits x 16 words,
two
FIFOs) uses up half the chip.
^^^^^^^^^^^^^
Unless the design is complete and you can verify that it fits AND you
have a pinout, this would scare the hell out of me. I have to admit
not having used the Coolrunnner, but over the past six years, we have
had an absolutely horrible time making very minor changes to
moderately full 95xxx series Xilinx CPLD's. Again, this may not apply
as much to the Coolrunner, since it is a completely different family -
but I'd still verify it first.

I agree with the other poster - what about the Cypress or Lattice
devices? I realize that gets you away from your "all Xilinx" board,
but is there really a good reason for desiring that (except maybe you
can get all parts from one distributor)?

No, sticking with Xilinx is not a strong desire since the software is
not common anyway. But Lattice has nothing that will fit this socket
and I have not been able to get a decent price on a Cypress part. I
guess that is also part of my goal to use Xilinx. I have gotten some
really great pricing on the parts I have discussed with them. They are
working with me, so it makes me want to work with them.

But I agree that using the XCR3512XL is scaring me as well. That is why
I am asking about other Xilinx alternatives.

I am sure I looked at the Cypress parts. I need about 170+ IOs in a 256
FBGA. The insides are not real important since that many IOs almost
always means a larger part than what I need, say 20,000 gates or 1000
LUT/FF. The memory is optional since with that many FFs I can make my
own FIFOs easily. Any idea of what a real price in a Cypress part would
run? I don't really see much that will fit the socket unless I am
missing something.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Hal Murray]

This is a kind of religion, I don't believe in "not possible", only in
"I don't know how to do".

Yes, but there are several types of problems. A few of them
are "well known" to be impossible. Examples include traveling
faster than light and perpetual motion machines. I think
metastability is one of these.

Sure, I'll keep an eye open for new results, but I won't waste any
time if I'm working on an engineering problem with current technology
and I will use claims/suggestions of a solution as an idiot filter
unless they are backed up by some amazing evidence. A usenet post
isn't good enough. We're talking Nobel Prize class work.

--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.

 

[Bob Perlman]

On Sat, 30 Aug 2003 23:15:18 -0400, rickman <spamgoeshere4@yahoo.com>
wrote:

Hal Murray wrote:

this has nothing to do with quantization, until you get into QED, but is
a matter of statistical thermal noise on two cells that are used to jam
the outputs of a flop. You need the noise, but that has nothing to do
with undergrad quantum mechanics. Read Peter's stuff - he's quite good
and knowledgable.

Do I need noise? Why? I thought the normal exponential decay
was well modeled (Spice?) without noise. Perhaps you need
it if the FF is "perfectly" ballanced but that has a vanishingly
small probability in the real world.

I think you are right. There is only one point on a continuous range
that will be perfectly balanced. The probability of that is in essence
the inverse of infinity which I don't know that it even has meaning.

If you require noise to shift you out of metastability, then the people
who argue that more noise will get you out quicker could then be right.

A metastable failure doesn't require that you land exactly on the
balance point. There may be only one point that keeps you in the
metastable state forever, but there's a range of points that will
delay FF settling long enough to make your design fail. The more time
you give the design to settle, the shorter that range of points is.

Accordingly, noise doesn't have to kick the FF to that perfect balance
point. It need only force you close enough that the FF output
transition is sufficiently delayed to hose over the circuit.

Bob Perlman
Cambrian Design Works