EDK : FSL macros defined by Xilinx are wrong

[Peter Ryser]

The EDK reference design for ML300 is now directly downloadable from
http://www.xilinx.com/ise/embedded/EDK/ml300_edk1.zip

You can reach the same link as "example 21" from
http://www.xilinx.com/ise/embedded/edk_examples.htm

- Peter

Antti Lukats wrote:

Hi

those who want to build a linux hardware ref. platfrom for Virtex 2Pro
ML300 the reference desing for Xilinx EDK does exist - just received it.
it should be sufficient to run Montavista distribution, but I guess
denx ELDK would also work with minor patching.

antti
this reference design really is available from your local Xilinx FAE!
(I didnt believe it until got it)

 

[rickman]

Bob Perlman wrote:

On Sat, 30 Aug 2003 23:15:18 -0400, rickman <spamgoeshere4@yahoo.com
wrote:

Hal Murray wrote:

this has nothing to do with quantization, until you get into QED, but is
a matter of statistical thermal noise on two cells that are used to jam
the outputs of a flop. You need the noise, but that has nothing to do
with undergrad quantum mechanics. Read Peter's stuff - he's quite good
and knowledgable.

Do I need noise? Why? I thought the normal exponential decay
was well modeled (Spice?) without noise. Perhaps you need
it if the FF is "perfectly" ballanced but that has a vanishingly
small probability in the real world.

I think you are right. There is only one point on a continuous range
that will be perfectly balanced. The probability of that is in essence
the inverse of infinity which I don't know that it even has meaning.

If you require noise to shift you out of metastability, then the people
who argue that more noise will get you out quicker could then be right.

A metastable failure doesn't require that you land exactly on the
balance point. There may be only one point that keeps you in the
metastable state forever, but there's a range of points that will
delay FF settling long enough to make your design fail. The more time
you give the design to settle, the shorter that range of points is.

Accordingly, noise doesn't have to kick the FF to that perfect balance
point. It need only force you close enough that the FF output
transition is sufficiently delayed to hose over the circuit.

I don't think you understand the point. We are not saying that balance
or noise are required to demonstrate metastability. It was pointed out
that in a simulation of the effect, something would be needed to move
the FF off the balance point and noise was suggested. But in the real
world the "balance point" is so vanishing small, it would never actually
happen. That is not saying that the FF can not go metastable without
being balanced.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Bob Perlman]

On Sun, 31 Aug 2003 10:55:19 -0400, rickman <spamgoeshere4@yahoo.com>
wrote:

Bob Perlman wrote:

On Sat, 30 Aug 2003 23:15:18 -0400, rickman <spamgoeshere4@yahoo.com
wrote:

Hal Murray wrote:

this has nothing to do with quantization, until you get into QED, but is
a matter of statistical thermal noise on two cells that are used to jam
the outputs of a flop. You need the noise, but that has nothing to do
with undergrad quantum mechanics. Read Peter's stuff - he's quite good
and knowledgable.

Do I need noise? Why? I thought the normal exponential decay
was well modeled (Spice?) without noise. Perhaps you need
it if the FF is "perfectly" ballanced but that has a vanishingly
small probability in the real world.

I think you are right. There is only one point on a continuous range
that will be perfectly balanced. The probability of that is in essence
the inverse of infinity which I don't know that it even has meaning.

If you require noise to shift you out of metastability, then the people
who argue that more noise will get you out quicker could then be right.

A metastable failure doesn't require that you land exactly on the
balance point. There may be only one point that keeps you in the
metastable state forever, but there's a range of points that will
delay FF settling long enough to make your design fail. The more time
you give the design to settle, the shorter that range of points is.

Accordingly, noise doesn't have to kick the FF to that perfect balance
point. It need only force you close enough that the FF output
transition is sufficiently delayed to hose over the circuit.

I don't think you understand the point. We are not saying that balance
or noise are required to demonstrate metastability. It was pointed out
that in a simulation of the effect, something would be needed to move
the FF off the balance point and noise was suggested. But in the real
world the "balance point" is so vanishing small, it would never actually
happen. That is not saying that the FF can not go metastable without
being balanced.

Whoever said, "If you require noise to shift you out of metastability,
then the people who argue that more noise will get you out quicker
could then be right," could you explain further? Are you saying that
noise is required to resolve the metastable state, or is this a
counter-argument to the "noise may get you out faster" claim? Or is
it something else entirely?

Bob Perlman
Cambrian Design Works

 

[Rene Tschaggelar]

Pawel Kolodziej wrote:

In article <a2214fd40dcc30b0380a43f3441e0804@news.teranews.com>, Rene Tschaggelar wrote:

Yes.
I'd get the peche melba by saving my time by not spending a
few hours on the internet looking for free samples of 4$ parts.


Could someone tell me what is price of Altera Cyclone devices ?
In Poland EP1C3T100C7 costs about 30$ (When I want to buy only 1
piece). I think it's to expensive.

I did a search on EBV : http://www.ebv.com , a European distributor,
it was listed there for 25,72 Euros.
Their prices are about right I think.
There are also distributors here with a minimum billing value of
100 Euros. EBV is not one of them, IIRC.

Rene
--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

 

[Subroto Datta]

Right click on the block you created. You can use use the Create Design File
From Selected Block. to generate a lower level Schematic file (bdf), VHDL
file (vhd), Verilog File (v) or AHDL (tdf) file for the selected Block.
These generated files will contain the I/O definitions that were defined by
the block. You can then open the generated file and enter the rest of the
design.

For example my schematic had a block called block_name with 4 ports. I right
clicked on the block and used the Create Design File From Selected Block
command to generate the file block_name.vhd file. The contents of the
generated block_name.vhd is as follows:

......Copyright text
-- Generated by Quartus II Version 3.0 (Build Internal Build 225 08/11/2003)

LIBRARY ieee;
USE ieee.std_logic_1164.all;


-- Entity Declaration

ENTITY block_name IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
PORT
(
a : IN STD_LOGIC;
b : IN STD_LOGIC_VECTOR(2 downto 0);
c : OUT STD_LOGIC;
d : OUT STD_LOGIC_VECTOR(3 downto 0)
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!

END block_name;


-- Architecture Body

ARCHITECTURE block_name_architecture OF block_name IS


BEGIN
-- Enter your logic here
END block_name_architecture;


Hope this helps.

- Subroto Datta
Altera Corp.

"Panic" <panic74@hotmail.com> wrote in message
news:Zxm4b.18758$os2.258386@news2.e.nsc.no...

I'm new to Quartus II, and all I have done with it so far
is walking through the tutorials. But there is one thing that
I can't figure out:

Is there a way to link the contents of a block in a schematic
block diagram to another schematic block diagramm file, in
order to get a hierarchy of schematic block diagrams, where
finaly the bottom-most sbd-files are linked to hdl-source-files,
like it is in say FPGA Advantage?

Hopefully
-"Panic"

 

[Andy Peters]

"John" <305liuzg@163.net> wrote in message news:<bit2o5$o0$1@mail.cn99.com>...

Hi,all
I use synplify or Quartus to do the synthesis.
What files should I pass to Modelsim to do the timing simulation?

The tools should spit out a .SDF file and a new Verilog or VHDL
top-level file. Compile the top-level file, replacing the RTL code,
and tell the simulator to apply the SDF file appropriately. For
example, if your test bench is called foo_tb.v, and it instantiates
your design as:

mychip uut (this, that, theother);

tell ModelSim that it should apply the .SDF to /uut and it should just
work. You may also have to compile a library of Altera primatives.

I would imagine that Altera's documentation spells all of this out in
gory detail

=a

 

[Jim Granville]

The (simple) statistical models must fall down when they hit
the quantization of single electrons.
How close are we to that ?
Has anyone tried to actually plot the tail of time/probability,
to see what law it follows ?
How does this actual tail vary with temperature.
Hi Jim -

this has nothing to do with quantization, until you get into QED, but is
a matter of statistical thermal noise on two cells that are used to jam
the outputs of a flop. You need the noise, but that has nothing to do
with undergrad quantum mechanics. Read Peter's stuff - he's quite good
and knowledgable.

I understand the (dominant) thermal aspects, but my physics teacher
taught me that all extrapolation is dangerous - hence the question
about the quantize effects, on the tail.

Problem is, the tail is by nature hard to measure, and so mostly we get
the
statisical arm waving of a continuous 'vanishingly small' curve of
Time/Probability.

With each FPGA generation, we must be getting closer to being
able to look for these more subtle effects.

eg Electron charge is in region of 10^-19, and Gate charge of a MOS FET
is
measured in some fC/um^2 (femto = 10^-15), so in 90nm devices we
should be in the 10^-17/10^-18 region.

Does anyone have a real value for Qc in 90nm process ?

-jg

 

[Philip Freidin]

On Sun, 31 Aug 2003 22:17:41 +0800, "Chen Bin" <sunwen_ling@hotmail.com> wrote:

Hi,
I am a colledge student,one of my dreams is to design a 16-bit CPU,it has
some basic functions,such as arithmatic and MMU and so on.

But I don't have any idea how to get it.Can you give some suggestions about
it?

I mean,what steps should I take to obtain this dream,and at each step,which
book should I read,how long will I get the dream?

Any help appreciated!!

This is a cry from a puzzled student for your help.

Chen Bin

Cry no more!

Lucky for you, there is a web site that covers this in detail,
including a worked and explained example!

http://www.fpgacpu.org/

and in particular, look at the 3 PDF files at

http://www.fpgacpu.org/xsoc/cc.html

Have fun!

Philip

Philip Freidin
Fliptronics

 

[Glen Herrmannsfeldt]

"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3F50A0E8.15AAA082@yahoo.com...

(snip regarding the DEC KA-10, metastability, and self-timed logic)

I am no expert in async logic, but I have never heard of a circuit that
can even detect metastability. I also thought that async logic did not
"measure" the time it took for a calculation, it simply allowed
different times for different calculations. The control path for a
given circuit has a longer delay than the data path and would be
dependant on the calculation being performed. How exactly would a
circuit detect when an async calculation is complete?

Well, I agree with the skepticism in the first place, but consider a CPU
with lights indicating the current contents of the registers. Normally, the
values will be changing very fast. If they suddenly stop changing, it could
be because of unresolved metastability. The logic will wait quietly for it
to resolve, and then continue.

It might be, though, that the machine is in I/O wait, and there really is
nothing to do. I never got to actually see the machine, but at the time
many machines had console lights, at least for the instruction counter and a
few other important registers. (Though I don't believe that the PDP-10 had
a wait state like IBM S/360 did, where no instructions were executed.)

-- glen

 

[Jonathan Bromley]

"Skull-Lee" <Skull-Lee@tuks.co.za> wrote in
message news:1062408392.909742@nntp.up.ac.za...

I need to comunicate with a DSP in serie.
Is there a way that any one know of?

What DSP? Most of the Texas DSP processors have various
different serial interfaces, all of which are fully documented
in the data sheets. I don't know about other manufacturers'
offerings, but I suspect something similar is available.
DSP chips commonly use serial interfaces to communicate
with slow peripherals such as audio DACs.
--

Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Luiz Carlos]

If you think there is no uncertanty in measuring the spin of an
electron, you need to go back to school.

Rick, I din't say that. I said electron spin does not presents
metastability.

Anyway, did you hear about spintronics? Maybe the scientists behind
this idea may go back to school too!

Look at
http://www.eetimes.com/story/OEG20001221S0035
Cut and paste please, I don't know how to include hypertexts.
I think that shows my whole point of view: if you believe, insist!

Unhappily (for me) I could not find the text about the electron
position.

Luiz Carlos

 

[Roger Larsson]

Terry wrote:

Hi, have anyone successfully installed Xilinx Foundation Series 2.1i on
Linux?

I've tried doing so, but without success.
This is what I have done.

cd /mnt/cdrom
wine setup.exe

With the above command executed, a new window with the Xilinx logo
appeared and disappeared without doing any installation.

The specs of my comp. are as follow:
Pentium 3 500 MHz
Mandrake 9.1

Thank you.

Might this be related to the buggy Java interpreter mentioned in
"Xilinx Foundation Series F2.1i + win2k" (comp.arch.fpga)

/RogerL
--
Roger Larsson
Skellefteĺ
Sweden

 

[Luiz Carlos]

Peter, Austin!
Nobody can help me?

Luiz Carlos

 

[Austin Lesea]

Luiz,

The input comparator is not characterized as a general purpose
comparator, but it actually is pretty useful in that way.

There is some samll offset voltage from the mis-match between the
differential pairs (both nmos and cmos to cover the voltage range). I
do not know what this offset might be, but I suspect it is less than a
few tens of millivolts, worst case from the transistor models.

The comparator will switch as soon as the voltage is greater than the
offset (we spec 100 mV for speed reasons, not because it needs > 100 mv
to function).

So with 50 mV it will switch, just more slowly than if it was 100 mV.

Austin

Luiz Carlos wrote:

Peter, Austin!
Nobody can help me?

Luiz Carlos

 

[Austin Lesea]

Hĺkon,

You are welcome. It is wonderful to hear from folks who are doing what I used
to do for 23 years (design telecoms equipment) and using the parts I helped
design. It is your feedback that leads to future feature enhancements,

Austin

"Hĺkon Lislebř" wrote:

Yes I use a 2V40 in that application (155Mb clock data switch/mux), and I
have not found a simple way to multiplex the clock quality logic. We ended
up with a combination of SW logic and HW logic for supervising of the DCM's.
It works, but the SW guys dont like the extra lines of code! A picoBlaze is
interesting for my next project, I'll take a deeper look at that one. Thank
you for the conversation!

Hakon Lislebo

"Austin Lesea" <Austin.Lesea@xilinx.com> wrote in message
news:3F4B78A5.6E3FEED8@xilinx.com...
Hĺkon,

Well, sounds like you really do have a demanding application, and it
therefore
it needs a well thought out and debugged solution. I would hate to try to
match
our system design skills with yours (and get it wrong) so the cheapest and
best
way to address thius is still using LUTs, SRL16s, and FFs.

And what are you using, a 2V40? We are still talking about less than a
few
hundred CLB's, which is a tiny number in a 2V1000 or larger. If it is a
2V40,
or a 2V80, I can see your point, as it might get a bit crowded.

Is it possible to multiplex your clock quality logic among multiple DCMs?
Sort
of a reset controller? Or use a picoBlaze to control all DCM resets? It
is not
a function that needs the speed of the fabric, so one can replace it with
software, and a soft controller core like the picoBlaze. Might be an
advantageos trade-off.

Austin

 

[Austin Lesea]

Chen,

For University Support:

MIT is hosting a Xilinx users group. This will be an unmediated forum where you
can exchange curriculum and project ideas with your peers around the world as
well as find solutions to problems. To subscribe send email with subscribe in
the subject line to: xilinxusers-admin@mit.edu , once you have subscribed
send subsequent comments etc. to: xilinxusers@mit.edu . By subscribing, you
will get a digest of the email traffic sent to you.

The Xilinx University Program thanks MIT and specifically Andrew Huang for
hosting this newsgroup.

(From our website as our hotline does not support students),

Austin

Chen Bin wrote:

Hi,
I am a colledge student,one of my dreams is to design a 16-bit CPU,it has
some basic functions,such as arithmatic and MMU and so on.

But I don't have any idea how to get it.Can you give some suggestions about
it?

I mean,what steps should I take to obtain this dream,and at each step,which
book should I read,how long will I get the dream?

Any help appreciated!!

This is a cry from a puzzled student for your help.

Chen Bin

 

[John_H]

"Luiz Carlos" <oen_br@yahoo.com.br> wrote in message
news:8471ba54.0309020217.567a3f03@posting.google.com...

Peter, Austin!
Nobody can help me?

Luiz Carlos

Maybe they can shed some light, but using a digital circuit for analog
functions is like trying to use a car as a tractor. It might work but it
sure as heck wasn't designed to plow fields - you're bound to have problems.

Since digital logic has fixed thresholds and large noise margins (difference
beteween Vih and Vil) there's no need for the designers to be detailed about
keeping the internal noise to the sub-millivolt level when there's so much
activity in the adjacent I/O cells or internal logic.

The Vref pins on the bank are designed for I/O signalling where the
threshold does not change so dynamically changing this value dramatically
can have unforseen effects.

LVDS signalling produces the best differential capability, allowing a
dynamic "Vref" for your doomed analog comparator in the digital device but
the noise margin for LVDS is still a rather large value.

If you put nothing else in the FPGA, I imagine you could get good noise-free
results with a consistent transition (though subject to an offset voltage in
the many 10s of millivolts). My guess is you want more than just the analog
comparator in there.

Consider using... an analog comparator!

- John_H

 

[Christian Schneider]

Well, if you have the tools, why don't you have a look at the results?
Just use the Floorplanner or the FPGA Editor.

If nothing helps, try a more recent version. You may wish to have a look
at the xilinx home page.

BR Chris

Kload wrote:

Hi all,

Lets assume I'm using a Xilinx Virtex device and I have a VHDL design
that includes the following

a<=b+c;

Will the design tools (I happen to be using Foundation 2.1i) infer a
"simple" adder or will the tools automatically infer an adder that uses
the dedicated carry look ahead logic?? Will that logic be placed
appropriately (i.e. like the ACC and ADD standard components that use
the RLOC constraint)?

Thanks for your help.

 

[Jon Elson]

Terry wrote:

Hi, have anyone successfully installed Xilinx Foundation Series 2.1i
on Linux?

I've tried doing so, but without success.
This is what I have done.

cd /mnt/cdrom
wine setup.exe

I can guarantee it will work with VMWare. But, this requires a full Windows

(your favorite flavor here) OS to be installed as a guest to the Linux
system.
And, there is no longer a free version of VMWare. They do have demos,
however.

Jon

 

[Andrey Likholit]

Hi Luiz,
I'll try to comment.

The manual says:
Vout = low, if Vin <= Vref - 0.5
Vout = high, if Vin >= Vref + 0.5
But, what does hapen if Vin=Vref+0.1?
I see other numbers in document "Spartan-IIC and Switching

Characteristics" (table on pg.3).
Inequations should be as following:
Vout = low, if Vin <= Vref - 0.1
Vout = high, if Vin >= Vref + 0.1(volts, here and below)

Does Vout still go high?
Suppose Vin=Vref+0.02 in your question to match corrected inequations.

Vout will not go high. As you are breaking the logical input level
requirements hence the input buffer will behave like non-linear
differential amplifier (so it is always possible to find such Vin
value on DC input-to-output transfer curve that Vout will stand
between Vhigh and Vlow,
say Vout=(Vhigh+Vlow)/2+Voffset and this point will be stable if Vin
is stable).

I think this is related to the metastability problem, but I preferred
to start a new thread.
I don't think this is about metastability unless you bring positive

feedback to input buffer.

This is only my opinion, I can't verify it with measurements,
unfortunately.

Regards,
Andrey