EDK : FSL macros defined by Xilinx are wrong

[Luiz Carlos]

Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:<3F55FE76.532A72CE@xilinx.com>...

Luiz,

Last things first, the LVTTL input does not use the comparator(s) (there are
three different comparators, as well as other ciruits for the various input
standards).

The comparator is designed to have a relatively high gain, so that it
switches quickly.

As I said, the offset voltage is due to the Vt mismatch on the pmos and nmos
diff pairs, and since these are built with .35u (VII) or .25u (VII Pro)
transistors, they are pretty darn fast diff-amps. There is a classic gain
stage after the cmos diff-amp (similar to the ones in "CMOS Circuit Design,
Layout & Simulation" by Baker, Li, and Boyce). The offset voltage is
typically less than a few 10's of mV (say 10 to 20 mV worst case). I am sure
that if you vary the voltage difference slowly enough, you could measure the
gain of the diff-amp. It was designed for HSTL and SSTL IO standards, which
as someone already pointed out, are pretty sloppy. What I will point out
here, is that I am not aware of any monolithic separate comparator that is as
fast as the one that is in the input circuit. This comparator is good for
400 Mbs+ speeds, which is a lot faster than most separate IC comparators....

Austin

Thankyou Austin.

I'm thinking of using this internal comparator for a Delta-Sigma ADC.

Luiz Carlos.

 

[Thomas Oehme]

Hallo David,

i also had this problem. My workaround is to delete the removed ports
manually from the ucf-file by using "Edit Constaints(Text)" from
theProcesses-Window.
This works fine and is fast.

best regards

Thomas Oehme

"David Lamb" <gretzteam_nospam@yahoo.com> schrieb im Newsbeitrag
news:bj547c$6pr$1@home.itg.ti.com...

Hi,
I have a vhdl project and I used a UCF file to assign the package pin to
each port in the design. This works fine. However, if I change my vhdl
code
(let's say I remove an output port), I always get the following error when
I
try to run the UCF editor:
ERROR:NgdBuild:756 - Line 3 in 'constraints.ucf': Could not find net(s)
'outputA' in the design. To suppress this error specify the correct
net
name or remove the constraint.

It seems like the UCF doesn't update itself with the new design. I tried
everything and I always have to start with a new UCF each time. The
removed
port doesn't exist in the Edit constraints (TEXT) because I didn't add any
constraint to it. I really don't see how to do it.
Thanks
David

 

[Luiz Carlos]

But the measurement is not instantaneous. So the transistion could
occur during a measurement. Result... inconclusive measurement which is
what metastability is all about.

You just need to measure the spins to see the results. You can
maintain they stable during this. To carry out the operations the
spins interact and you don't need to measure them. But, if you imply a
measure in the interaction process, so the measure is instantaneous.

Luiz Carlos

 

[Aurelian Lazarut]

arkaitz wrote:

Hi,

I'm trying to connect a user peripheral to the Microblaze OPB bus. I
have done all as mentioned in the "User Core Template for OPB (Slave
Services Package 0) but without success.

I have added some code lines in the correponding places to match the
IPIF to my user_core.

I have routed the Bus2IP_CS, Bus2IP_WrCE and Bus2IP_RdCE to some user
leds in my development board and I haven't noticed any effect, so I
imagine that I'm not accesing to my peripheral.

If you are attaching LEDs on these signals you will not see anything
(maybe with an osilloscope) these signals are active only for an OPB bus
transaction which will match your C_BASEADDRESS, depending on your OPB_Ack
latency (transaction acknoledge) this will keep from 2 to 16 OPB_Clk
periods so you need a very good eye to see a ~1 us blink. (assuming 100Mhz
OPB_Clk)

Aurash

I have also checked the BASEADDR and the HIGHADDR and I think they're
correct.

Here you are part of my MPD file

PARAMETER c_baseaddr = 0xFFFFFFFF, DT = std_logic_vector, MIN_SIZE
= 0xFF
PARAMETER c_highaddr = 0x00000000, DT = std_logic_vector
PARAMETER c_mir_baseaddr = 0xFFFFFFFF, DT = std_logic_vector, MIN_SIZE
= 0xFF
PARAMETER c_mir_highaddr = 0x00000000, DT = std_logic_vector
PARAMETER c_user_id_code = 3, DT = integer
PARAMETER c_include_mir = 0, DT = integer
PARAMETER c_opb_awidth = 32, DT = integer
PARAMETER c_opb_dwidth = 32, DT = integer
PARAMETER c_family = virtex2, DT = string

Note that I actualize "c_baseaddr" and "c_highaddr" parameters on the
component as well as the "c_mir_baseaddr" and "c_mir_highaddr".

I'd be very grateful if someone could help me.

Thanks.

Arkaitz.

--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/

phone: 353 01 4032639
fax: 353 01 4640324

 

[Austin Lesea]

Luiz,

We have done this, and it works. The question is how well? The answer is that we have never
actually used this in a system where other things are going on as well, and then measured the S/N
of the ADC, resolution, THD, etc. Let us know how it turns out. Better than using Vref and the
input would be to use an LVDS input buffer (as was already pointed out) differentially. You will
only get a good 1V to 1.5V span (where the comparator works the fastest and best), but the
differential input leads to less noise.

Austin

Luiz Carlos wrote:

Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:<3F55FE76.532A72CE@xilinx.com>...
Luiz,

Last things first, the LVTTL input does not use the comparator(s) (there are
three different comparators, as well as other ciruits for the various input
standards).

The comparator is designed to have a relatively high gain, so that it
switches quickly.

As I said, the offset voltage is due to the Vt mismatch on the pmos and nmos
diff pairs, and since these are built with .35u (VII) or .25u (VII Pro)
transistors, they are pretty darn fast diff-amps. There is a classic gain
stage after the cmos diff-amp (similar to the ones in "CMOS Circuit Design,
Layout & Simulation" by Baker, Li, and Boyce). The offset voltage is
typically less than a few 10's of mV (say 10 to 20 mV worst case). I am sure
that if you vary the voltage difference slowly enough, you could measure the
gain of the diff-amp. It was designed for HSTL and SSTL IO standards, which
as someone already pointed out, are pretty sloppy. What I will point out
here, is that I am not aware of any monolithic separate comparator that is as
fast as the one that is in the input circuit. This comparator is good for
400 Mbs+ speeds, which is a lot faster than most separate IC comparators....

Austin

Thankyou Austin.

I'm thinking of using this internal comparator for a Delta-Sigma ADC.

Luiz Carlos.

 

[Steven K. Knapp]

"Antti Lukats" <antti@case2000.com> wrote in message
news:80a3aea5.0308282129.5f483d78@posting.google.com...
<...snip...>

I guess the smallest spartan III and cyclone devices should also come down
below 10$ but then S3-50 does not have BRAM and both Spartan and Cyclone
do require config memory to be present what may add significant amount to
the final price (both money as board estate, etc)

antti

The Xilinx Spartan-3 XC3S50, in its production form, has four 18Kbit block
RAMs (BRAM), four 18x18 hardware multipliers, and two digital clock
managers. For the correct specifications, see
http://www.xilinx.com/bvdocs/publications/ds099-1.pdf.

In volume, the XC3S50, the XC3S200, and the XC3S400 are all less than $10 in
the smallest packages.

To reduce the overall "solution cost", Spartan-3 FPGAs optionally use Xilinx
PlatformFlash, which does NOT add a significant amount to the final price.
See http://www.xilinx.com/platformflash. Alternatively, configuration data
can be stored in just about any non-volatile memory available elsewhere in
the system, such as ...

* Same Flash that holds the boot code or application code for a processor
or microcontroller,
* Downloaded from hard disk.
---------------------------------
Steven K. Knapp
Sr. Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3: Make it Your ASIC

 

[Jan Panteltje]

On a sunny day (Thu, 04 Sep 2003 07:41:43 -0700) it happened Austin Lesea
<Austin.Lesea@xilinx.com> wrote in <3F574F27.75C87433@xilinx.com>:

Luiz,

We have done this, and it works. The question is how well? The answer is that we have never
actually used this in a system where other things are going on as well, and then measured the S/N
of the ADC, resolution, THD, etc. Let us know how it turns out. Better than using Vref and the
input would be to use an LVDS input buffer (as was already pointed out) differentially. You will
only get a good 1V to 1.5V span (where the comparator works the fastest and best), but the
differential input leads to less noise.
So with say 10 mV and a 1 V span, is 1 in 100, and that speed, put a R2R on some 8 output pins,

and do succesive aproximation to create a video ADC?
For a span of 2.5 V you would get 8 bits... That would be usable.
At 400Mbs / s in 8 steps would be 50 MHz
Do I understand this right?
(Non linearity could be corrected in software, maybe the gamma would be good hehe
?

 

[Austin Lesea]

Jan,

You could resolve finer than 10 mV (offset does not equal resolvable step size), so that the
resolution is limited more by the noise, and response time.

And all of the self-calibraing tricks used in modern ADCs could be used here as well to improve the
linearity and the response.

Austin

Jan Panteltje wrote:

On a sunny day (Thu, 04 Sep 2003 07:41:43 -0700) it happened Austin Lesea
Austin.Lesea@xilinx.com> wrote in <3F574F27.75C87433@xilinx.com>:

Luiz,

We have done this, and it works. The question is how well? The answer is that we have never
actually used this in a system where other things are going on as well, and then measured the S/N
of the ADC, resolution, THD, etc. Let us know how it turns out. Better than using Vref and the
input would be to use an LVDS input buffer (as was already pointed out) differentially. You will
only get a good 1V to 1.5V span (where the comparator works the fastest and best), but the
differential input leads to less noise.
So with say 10 mV and a 1 V span, is 1 in 100, and that speed, put a R2R on some 8 output pins,
and do succesive aproximation to create a video ADC?
For a span of 2.5 V you would get 8 bits... That would be usable.
At 400Mbs / s in 8 steps would be 50 MHz
Do I understand this right?
(Non linearity could be corrected in software, maybe the gamma would be good hehe
?

 

[peterzhu]

Jon Elson <elson@pico-systems.com> wrote in message news:<3F56CE61.5010802@pico-systems.com>...

peterzhu wrote:

Due to a chip bug, I have to extend a pulse width(negative)from 10ns
to 100ms in CPLD(Altera 7128). But the difficult is that I have no any
clock into the CPLD, so the CPLD is pure combination logic. how to
extend it in such case?

Help me!


I have delayed strobe signals several hundred nS with an external series
resistor, and used the input capacitance of the chip as the C of the RC
network. For mS, you will need an external capacitor, of course. if you
want the delay to be asymmetric (like a one-shot), you might need to
put a diode in parallel with the R. You feed the signal out one pin,
through a series R, to a pin loaded with a cap to ground, and then take
the signal in from that pin. This may cause multiple pulses with a
delay this long, however. So, you might end up using a 74HC4538
or similar one shot, or a 74HC14 Schmitt trigger to prevent the
pulses as the output of the RC crosses the threshold.

Jon

The board is in production, so I can not change the SCH and PCB, all
things should be done in CPLD.

Peter

 

[Stephan Flock]

You could take two cascaded flip-flops, feed the first with '1' and use your
10 ns strobe as async reset for both. Take a 100 ms (10 Hz) clock or clock
enable signal for the FFs and combine both outputs to a 100 ms strobe.

Regards,
Stephan Flock

 

[H. Peter Anvin]

Followup to: <3F562773.EC0F14B8@yahoo.com>
By author: rickman <spamgoeshere4@yahoo.com>
In newsgroup: comp.arch.fpga

Luiz Carlos wrote:

Electron spin has all the same measurement issues that a FF has. If the
state of the electron spin is changing as the measurement is made, then
what state is it in? What will be the result of the measurement?


Rick, the electron spin is +1/2 or -1/2, there is no in between state,
it changes instantaneously (in one fundamental clock tick, ~10^-43
seconds).

Luiz Carlos

But the measurement is not instantaneous. So the transistion could
occur during a measurement. Result... inconclusive measurement which is
what metastability is all about.

Well, actually it is. It might *affect* the spin (Heisenberg wins
again) but unlike classical measurements there shouldn't be any ifs
about the result.

There is a lot of things in the quantum world which is completely
counterintuitive to everything we have learned. If you look at
quantum teleportation, for example, you'd have to conclude information
was conducted backwards in time...

<thhgttg>This is of course, impossible.</thhgttg>
--
<hpa@transmeta.com> at work, <hpa@zytor.com> in private!
If you send me mail in HTML format I will assume it's spam.
"Unix gives you enough rope to shoot yourself in the foot."
Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64

 

[Ron Cline]

rickman wrote:

There is no way to determine when a circuit is metastable or not.

It is possible -- I did it once for a FF design for another company. It
requires a separate, combinational output signal ("metastable flag-out").
But, of course, there's no way to use this to kick the FF circuit itself out
of metastability. All previous comments about this being a no-fix are true.

The flag is generated by taking advantage of the fact that the latch going
metastable has a cross-coupled gate with a known threshold point during
metastability. A 2-input logic gate with a different threshold can detect
that both inputs (ie, Q and Q-bar) are above (or below) it's own (different by
design) threshold point.

Cheers,
Ron Cline

 

[Tom Seim]

Ron Cline <Ron.Cline@xilinx.com> wrote in message news:<3F58C987.41B42E6F@xilinx.com>...

rickman wrote:
There is no way to determine when a circuit is metastable or not.

It is possible -- I did it once for a FF design for another company. It
requires a separate, combinational output signal ("metastable flag-out").
But, of course, there's no way to use this to kick the FF circuit itself out
of metastability. All previous comments about this being a no-fix are true.

The flag is generated by taking advantage of the fact that the latch going
metastable has a cross-coupled gate with a known threshold point during
metastability. A 2-input logic gate with a different threshold can detect
that both inputs (ie, Q and Q-bar) are above (or below) it's own (different by
design) threshold point.

Why can't you use this flag to generate another (delayed) clock to the
same FF? It would continue to retrigger itself until it was in a
stable state. If you ORed all of these flags together in a register
you would have a data valid output.

Nothin like async logic to get your blood flowing!

Tom

 

[Ron Cline]

Tom Seim wrote:

Ron Cline <Ron.Cline@xilinx.com> wrote in message news:<3F58C987.41B42E6F@xilinx.com>...
The flag is generated by taking advantage of the fact that the latch going
metastable has a cross-coupled gate with a known threshold point during
metastability. A 2-input logic gate with a different threshold can detect
that both inputs (ie, Q and Q-bar) are above (or below) it's own (different by
design) threshold point.

Why can't you use this flag to generate another (delayed) clock to the
same FF? It would continue to retrigger itself until it was in a
stable state.

This newly-created feedback loop would have a much longer metastable
time-constant than had the original latch. Better to leave well enough alone,
I think.

If you ORed all of these flags together in a register
you would have a data valid output.

The flag wouldn't indicate a logic state (valid or not), only the presence of
metastability. The logic state is indeterminant while the flag is active.

- Ron

 

[rickman]

Ron Cline wrote:

rickman wrote:
There is no way to determine when a circuit is metastable or not.

It is possible -- I did it once for a FF design for another company. It
requires a separate, combinational output signal ("metastable flag-out").
But, of course, there's no way to use this to kick the FF circuit itself out
of metastability. All previous comments about this being a no-fix are true.

The flag is generated by taking advantage of the fact that the latch going
metastable has a cross-coupled gate with a known threshold point during
metastability. A 2-input logic gate with a different threshold can detect
that both inputs (ie, Q and Q-bar) are above (or below) it's own (different by
design) threshold point.

And what happens to the output of this MS-detector gate if one of the
voltages is right at the threshold of the gate? Is it possible that the
output of the gate is at an intermediate voltage and is therefore
indeterminate?

Once again the problem comes from the measurement. There is no knife
that is sharp enough to split every hair known to man or nature.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Thomas Womack]

In article <umnslv4dggc3i11nrfikf1knlf9t1ldjob@4ax.com>,
Robert Myers <rmyers@rustuck.com> wrote:

The enormous throughput of GPU's, special-purpose processors like
GRAPE, and speculation about PlayStation keep my interest in what
might be possible if you wanted to build a special-purpose compute
engine.

Special-purpose compute engines are unavoidably rather expensive;
http://www.xilinx.com/apps/sp3app.htm gives a couple of interesting
directions to look in for the technology level that's actually
close to affordable.

The second-biggest Spartan3 chip has 96 18x18->36 multipliers, which gives
you eight 54x54 and a 72x72 to work with. A medium-sized XC2VP50
Virtex2 Pro has 232 of the 18x18 multipliers, and a pair of PPC440
CPUs -- and sixteen Hypertransport links -- but probably costs as much
as a Madison 1300MHz/3MB (IE $2000 or so). But I don't know what
speed you can clock that great array of multipliers at.

[note I've cross-posted this to comp.arch.fpga in case they know the
speed and cost details off the top of their heads; the idea is to
implement an array of double-precision FMA units on an FPGA, to see
how they'd compare to the few much-faster-clocked FMAs on high-end
CPUs. I don't know how exotic the Spartan3/4000 or the XC2VP50 are]

Tom

 

[Nicholas C. Weaver]

In article <v9x*dzc2p@news.chiark.greenend.org.uk>,
Thomas Womack <twomack@chiark.greenend.org.uk> wrote:

The enormous throughput of GPU's, special-purpose processors like
GRAPE, and speculation about PlayStation keep my interest in what
might be possible if you wanted to build a special-purpose compute
engine.

Special-purpose compute engines are unavoidably rather expensive;
http://www.xilinx.com/apps/sp3app.htm gives a couple of interesting
directions to look in for the technology level that's actually
close to affordable.

The second-biggest Spartan3 chip has 96 18x18->36 multipliers, which gives
you eight 54x54 and a 72x72 to work with. A medium-sized XC2VP50
Virtex2 Pro has 232 of the 18x18 multipliers, and a pair of PPC440
CPUs -- and sixteen Hypertransport links -- but probably costs as much
as a Madison 1300MHz/3MB (IE $2000 or so). But I don't know what
speed you can clock that great array of multipliers at.

I've done some back-of-the-enveloping. It looks reasonable to make a
vector procesor that is about 1/2 to 1/4 the throughput of the Earth
Simulator vector processor in a large FPGA (eg, V2Pro), eg 8 lane, 8
FP MAC/cycle, but only ~250 MHz.

The interesting parts really come in not in the computation but in the
communication: how do you do a low latency, high throughput, flexible
network to connect a whole BUNCH of computing elements. This is where
the FPGAs get interesting, with 3 Gbps SERDESes being standard and 10
Gbps SERDESes on the near-term horizon. With a cut-through routing,
the latency per hop is fairly low (~20-30 cycles at the 3 GHz stream
clock), so a network could be made that isn't full connectivity like a
crossbar, but is rather fast and routed.

[note I've cross-posted this to comp.arch.fpga in case they know the
speed and cost details off the top of their heads; the idea is to
implement an array of double-precision FMA units on an FPGA, to see
how they'd compare to the few much-faster-clocked FMAs on high-end
CPUs. I don't know how exotic the Spartan3/4000 or the XC2VP50 are]

Tom

--
Nicholas C. Weaver nweaver@cs.berkeley.edu

 

[Ray Andraka]

It very heavily depends on your implementation. The fact that it is
radix2 and
not radix 4 or higher tells me already that your implementation is not a
very
efficient one. A radix 4 kernel is very little added complexity over a
radix 2
kernel and cuts the processing time and area considerable. Depending on
your
speed requirements and your design prowess, you can certainly fit a 128
point
real-only FFT in a much smaller part than a 1M gate part. As your speed
requirements decrease, you can take advantage of iterative or shared
hardware
to reduce the gate count considerably. I did a 4096 point design in a
Xilinx
XCV1000 that does the complex transform in 68 us (the floorplan and a
brief
description are on the gallery page on my website). That one only
occupies
about 40% of the FPGA and includes some floating point stuff as well as
windowing multipliers and some other goodies. It takes intimate
knowledge
of the FPGA structure and of algorithms to achieve that level of density
(the customer called the design "a work of art"), but even a novice can
achieve a density/performance level of half that design with some
carefully
thought out design.

PJ wrote:

Hello,

I am implementing a 128 point real Radix-2 fft, data and coefficient
widths are 16 bit.
I am synthezising it for use in an FPGA. However, it is taking a very
long time to synthesize. (approx 3 days using Leonardo on a 2 GHz
machine with 512 MByte RAM) I am using a 20K1000 Altera FPGA. The ram
required by the fft will be internal to the FPGA

Will this design take up all the space on the device. From past
experience, can someone give me an indication of what area of the
device the fft will occupy.

Surely if it takes up most of the device, then it will be too big, as
I have other features to implement in the FPGA also !!

Thank you
PJ

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Khim Bittle]

On Mon, 15 Sep 2003 17:07:22 -0400, "jakab tanko" <jtanko@ics-ltd.com>
wrote:

Thanks for the suggestion, it looks like they also have USB 2.0 chip,
the board you have looks interesting too. I will search a bit more before
deciding.

Their chip will not run USB2.0 high speed, only full speed. ( I have
been able to get 1 MB/sec max on a real board ) Otherwise it is
great, I have used it on several boards. They are going to have a
high speed chip but it is at least a year off as it is just in
planning , this is a major bummer for my projects.

---
jakab
"Nial Stewart" <nial@spamno.nialstewart.co.uk> wrote in message
news:3f65cb6d$0$10961$fa0fcedb@lovejoy.zen.co.uk...
jakab tanko <jtanko@ics-ltd.com> wrote in message
news:bk4g4g$j0f$1@news.storm.ca...
Hi,

I am looking for an USB transceiver chip that can be interfaced to an
FPGA WITHOUT microcontroller. USB 2.0 would be ideal, 1.1 is also ok.
Any suggestions?

The FTDI 245BM sounds like what you want (although it's only 1.1).

See..

http://www.ftdichip.com/

..for details.

I've a board based on this I built for my own use (see under
downloads on my web site). I've a couple sitting here that
someone said they wanted but money hasn't been forthcoming.

Yours for Ł30 each if you want one/both for prototyping.

See my downloads page for details of an example project showing
how to drive it, it's relatively easy.


Nial Stewart

------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
www.nialstewartdevelopments.co.uk

 

[Duane Clark]

rickman wrote:

...
If you need info on changing your hard drive serial number, there is a
program available for that (as long as you are running a FAT drive and
not NTFS)...

VolumeID:
http://www.sysinternals.com/ntw2k/source/misc.shtml

--
My real email is akamail.com@dclark (or something like that).