EDK : FSL macros defined by Xilinx are wrong

[Kenneth Land]

Have you looked at the USB 1.1 and 2.0 IP Cores at www.opencores.com?

I looked very closely at the 1.1 version and found it took only 6 pins and
$1.75 transceiver chip.

Ken

"jakab tanko" <jtanko@ics-ltd.com> wrote in message
news:bk4g4g$j0f$1@news.storm.ca...

Hi,

I am looking for an USB transceiver chip that can be interfaced to an
FPGA WITHOUT microcontroller. USB 2.0 would be ideal, 1.1 is also ok.
Any suggestions?

Thanks,
---
jakab

 

[rickman]

John Williams wrote:

Hi Rick,

rickman wrote:
Looks like I have not done my homework on this. I had done some
research on modular configuration which was what I required. The
Spartan lines seem to be supported for this although they don't yet list
the Spartan3 chips. But I was under the impression that partial
configuration was the down load technique to support this in the
devices. I see that only Virtex and Virtex-II are supported by partial
configuration. This is not good.

Don't panic! the S3 still supports partial reconfiguration - the ICAP
primitive that Antti and I were talking about is a block that allows the
partial reconfigruration to be controlled from within the device itself
ie. self-reconfiguration.

All the Virtex's and S3 can be partially reconfigured from *outside* the
device, via SelectMap or slave serial or whatever, either partial or
total reconfiguration.

So why the disconnect on partial configuration Xilinx? Why not support
Spartan-3 devices?

As I said, it's just the ICAP (internal configuration access port), not
the partial reconfig capability itself.

Regards,

John

I am still in panic mode. I started digging and found that the Spartan
3 devices are not suitable for modular configuration. Seems the tbuf is
one of the features in the V2 devices that has been taken out for
"optimization" in the S3. The tbuf is required for signals that
traverse modules.

I have exchanged a couple of emails with Xilinx on this and am waiting
for the final word. But it is looking like the Sparan 3 devices will
not be able to do what I need in any defined timeframe.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[John Williams]

rickman wrote:

John Williams wrote:

Hi Rick,

rickman wrote:

Looks like I have not done my homework on this. I had done some
research on modular configuration which was what I required. The
Spartan lines seem to be supported for this although they don't yet list
the Spartan3 chips. But I was under the impression that partial
configuration was the down load technique to support this in the
devices. I see that only Virtex and Virtex-II are supported by partial
configuration. This is not good.

Don't panic! the S3 still supports partial reconfiguration - the ICAP
primitive that Antti and I were talking about is a block that allows the
partial reconfigruration to be controlled from within the device itself
ie. self-reconfiguration.

All the Virtex's and S3 can be partially reconfigured from *outside* the
device, via SelectMap or slave serial or whatever, either partial or
total reconfiguration.


So why the disconnect on partial configuration Xilinx? Why not support
Spartan-3 devices?

As I said, it's just the ICAP (internal configuration access port), not
the partial reconfig capability itself.

Regards,

John


I am still in panic mode. I started digging and found that the Spartan
3 devices are not suitable for modular configuration. Seems the tbuf is
one of the features in the V2 devices that has been taken out for
"optimization" in the S3. The tbuf is required for signals that
traverse modules.

Given your observation, plus the info provided by Steve Knapp from
Xilinx in an earlier post (cell behaviour during partial reconfig) it
seems that partial reconfig in S3 devices is not encouraged.

I have exchanged a couple of emails with Xilinx on this and am waiting
for the final word. But it is looking like the Sparan 3 devices will
not be able to do what I need in any defined timeframe.

So it seems.

Regards,

John

 

[Jon Elson]

Duane Clark wrote:

rickman wrote:

...
If you need info on changing your hard drive serial number, there is a
program available for that (as long as you are running a FAT drive and
not NTFS)...


VolumeID:
http://www.sysinternals.com/ntw2k/source/misc.shtml

WOW, thanks Rick and Duane! Together, you've given me all the things

to fix this! I didn't know how to change the volid on an NTFS disk.
This fixed it, and the license seems to be working! (Now, i just have to
beat my vhdl file into shape so FPGA express likes it!)

Thanks again,

Jon

 

[Antti Lukats]

"Kenneth Land" <kland1@neuralog1.com> wrote in message news:<vmcl99c2s5jgc0@news.supernews.com>...

Have you looked at the USB 1.1 and 2.0 IP Cores at www.opencores.com?

I looked very closely at the 1.1 version and found it took only 6 pins and
$1.75 transceiver chip.

Ken

there is a japanese design (VHDL, and Visual basic host example)
that uses no tranceiver at all, ie USB DM,DP directly to FPGa

antti

 

[enq_semi]

The other thing is that if *any* logic changes it has to re-run the
fitter, which at least for my designs is 60% of the compile time.

Well, I guess a few wires change is also "any logic changes".

poor me ...

 

[enq_semi]

"Smart Compilation" just means save the cache files
in case they can be reused. It doesn't make the cache
any more likely to be reusable. That is a function
of device utilization, routing strategy and the
impact of the design change.

Now it looks like that's really the case here. I was mistaken and
thought it is something like Design Compiler's incremental compile or
ECO changes of final layout. I should have realized that for the prize
that I paid for the board + software, it is too good to be true.

-- Maybe "didn't work" means
"routed successfully, but did not function correctly"

It is different from in asic design that I changed 8 pads without
running any simulations, I could mis-connect those pads. Here is FPGA
you just "assign" the output signals to different pins using
"assignment editor". How can it be "not function correctly" is beyond
me.

 

[enq_semi]

Doesn't look good. What version of Quartus are you running? 2.2 or 3.0? Did
you later retry using a normal compile, and did that work?

Ben,

I used Quartus II 2.2, then a few weeks ago I upgraded it 3.0.

I still have the same problem.

Yi

 

[enq_semi]

Hi Yi,

The smart recompile feature in Quartus skips only entire steps in the
compilation process that aren't needed. So if you move pins, it knows
that your design does not need to be re-synthesized & mapped, but it
does need to be re-placed and routed (fit). So you still wind up
paying the CPU time for a full place and route, even though you moved
only a few pins.

Vaughn,

Thank you very much for your detailed explaination! I really
appreciate it!!

I kind of realized that "need to be re-placed and fitted" even I move
a few pins before too. But I did notice in this case, the synthesis is
also repeated, takes about 15 minutes on an AMD 1700+ machine with 1G
memory.

To speed things up, you can back-annotate your design to LABs before
you recompile. Back-annotate, move the pins you want to move, and
recompile. It will now be a lot faster, since your logic is locked
down, so placement is trivial. It will still need to be routed and
timing analyzed though, but it should still be 3x or so faster to
compile.

I will try this and hope it works. Thanks!

Now for your second issue: why did your design not work after a smart
recompile? I can think of two possibilities:

1. There is some dangerous timing in your design (race conditions,
asynchronous transfers without handshaking, transfers between clock
domains without timing constraints, etc.). By re-placing and routing
your design, a race condition that was latent may have become a
problem.

Yes, you are right. The clocking is kind of messy in my design, lots
of clock gating and other manipulations. So, I can accept it if the
compiled design never worked, that may even make me feel better: I
really shouldn't do those nasty things on clock.

If I change any logics around cross-clock domain region, clock
generator (not pll), clock pll or even an inverter anywhere, I can
probably accept the fact that re-placing and fitting kill the design.
However, failing after moving a few output pins, which have no timing
constraints at all, is hard to understand.


Yi

 

[Ken Land]

Is it free?

That is very interesting and that is what I went looking for. I imagined
the logic in the FPGA would wiggle D+ and D- appropriately. I understand
that the 480Mbps of 2.0 might be tough in a garden variety FPGA, but 1.1
might be doable.

I wonder if the special LVDS pins of a Cyclone or Stratix would do 2.0? Of
course going to Stratix would negate any BOM savings.

Ken

"Antti Lukats" <antti@case2000.com> wrote in message
news:80a3aea5.0309152348.5ffd5049@posting.google.com...

"Kenneth Land" <kland1@neuralog1.com> wrote in message
news:<vmcl99c2s5jgc0@news.supernews.com>...
Have you looked at the USB 1.1 and 2.0 IP Cores at www.opencores.com?

I looked very closely at the 1.1 version and found it took only 6 pins
and
$1.75 transceiver chip.

Ken

there is a japanese design (VHDL, and Visual basic host example)
that uses no tranceiver at all, ie USB DM,DP directly to FPGa

antti

 

[jakab tanko]

480 MHz LVDS IO is not out of question on Xilinx FPGAs (Altera ? don't
know)
in terms of frequency; what I question is the voltage/current levels
to/from the USB,
have to dig into the USB spec to figure this one out.
Any pointers to this japanese design or its documentation?
---
jakab
"Ken Land" <kland1@neuralog1.com> wrote in message
news:vme5iv66sv911@news.supernews.com...

Is it free?

That is very interesting and that is what I went looking for. I imagined
the logic in the FPGA would wiggle D+ and D- appropriately. I understand
that the 480Mbps of 2.0 might be tough in a garden variety FPGA, but 1.1
might be doable.

I wonder if the special LVDS pins of a Cyclone or Stratix would do 2.0?
Of
course going to Stratix would negate any BOM savings.

Ken

"Antti Lukats" <antti@case2000.com> wrote in message
news:80a3aea5.0309152348.5ffd5049@posting.google.com...
"Kenneth Land" <kland1@neuralog1.com> wrote in message
news:<vmcl99c2s5jgc0@news.supernews.com>...
Have you looked at the USB 1.1 and 2.0 IP Cores at www.opencores.com?

I looked very closely at the 1.1 version and found it took only 6 pins
and
$1.75 transceiver chip.

Ken

there is a japanese design (VHDL, and Visual basic host example)
that uses no tranceiver at all, ie USB DM,DP directly to FPGa

antti

 

[Srikanth Anumalla]

On Mon, 15 Sep 2003 22:29:18 +0000, Jan Panteltje wrote:

On a sunny day (Mon, 15 Sep 2003 14:01:17 -0500) it happened Srikanth Anumalla
srikanth@unlserve.unl.edu> wrote in <bk523v$355$1@unlnews.unl.edu>:

Hi

I am quite new in this field, Please excuse me if I talk something
nonsence. I have 10 pressure sensors which measure pressure in 10
different points in a field. I need to aggregate all these values in
realtime and send to a remote computer.For this, somebody suggested me
to use fpga, I made little research and found out that we can actually
run an some programs on fpga. I have this idea now, to build an fpga
board which can read data from the sensor and send that data to a
central computer in the field over a wireless network. and I will have
an fpga at each sensor. CEntral computer will aggregate the data and
send to a remote location via phone line etc. For this to be realized I
have to know whether an fpga is capable of collecting date from a sensor
and send the same data over a wireless network. Please give me pointers
on this . Any help would be greatly appreciated.

Thanks
Srikanth


If your pressure sensors have analog output, then why use FPGA?
Use a PIC micro with build in AD and 4 channel input mux.
3 of these or one with an external mux, use the serial port of the PIC
or make your own protocol or whatever.
12F675 is only 8 pins DIL, has a 10 bits AD with 4 input mux, internal oscillator,
costs 2 dollars, so 4 of these set you back 8 dollars and the microchip tools are
free from www.microchip.com
Why use FPGA?

The reason I went for fpga was to have wireless networking (802.11)
Actually, the sensors are 3-4 miles apart, I need the data until a
base station from where I will transfer the data to the internet.
the base station is located in the filed and will be 1-2 miles distant
from each sensor. So how do I transfer (in realtime) the data until the
base station from the sensor. Is it possible with PCI micro.
Please suggest me if there is a better solution other than fpga cpu
for doing this (wireless networking).

Thanks in advance
Srikanth

 

[Andras Tantos]

The reason I went for fpga was to have wireless networking (802.11)
Actually, the sensors are 3-4 miles apart, I need the data until a
base station from where I will transfer the data to the internet.
the base station is located in the filed and will be 1-2 miles distant
from each sensor. So how do I transfer (in realtime) the data until the
base station from the sensor. Is it possible with PCI micro.
Please suggest me if there is a better solution other than fpga cpu
for doing this (wireless networking).

Doing wireless with FPGA is not easier (nor harder) than with CPUs or MCUs.
You probably will end up using some kind of off-the-selves wireless card and
connect it to your custom application. Of what I understand of your
application probably a wireless USB card would be the best for your
application. Processing power is not an issue in your case. In that case you
need to choose (or implement) a USB host controller but for control even an
8-bit CPU (PIC or AVR or whatever) should be adequate. I don't know of any
8-bit micro that has an USB host (not function!) controller, but there's a
USB interface IC from Cypress, the SL811HS, that can be used as both a host
and a slave controller. So, my suggestion would be:

- Use an 8-bit microcontroller with an external bus (68HC11 from Motorola)
or one with enough of I/O pins (ATmega from Atmel) and probably a with
built-in A/D for the pressure sensors.
- Use the SL811HS from Cypress to implement the USB host controller
- Stick a wireless USB adapter to the unit to implement wireless
- For 1-2 miles you probably need high-gain, directed antennas so choose an
adapter that has external antenna connectivity.

Regards,
Andras Tantos

 

[Antti Lukats]

"Ken Land" <kland1@neuralog1.com> wrote in message news:<vme5iv66sv911@news.supernews.com>...

Is it free?

its free but I cant give yout the url, tried to find it again for you
but failed, searching on japanese sites is a bit difficult

it is from some-one who wrote it for XSP-009 board, but there are no
links to it from XSP-009 official site(s) as much as I see.

I have the files, can send you per email if you wish, let me know
antti

 

[Steven K. Knapp]

Like Virtex-II and Virtex-II Pro, the Spartan-3 FPGA pre-configuration
pull-up resistors are controlled by the HSWAP_EN pin.

0 = Enables weak pull-up resistors on all pins not actively involved in the
configuration process.

1 = No pull-up resistors during configuration.

After configuration, this pin is not used and should be kept at a logic 0 or
1.

See page 13 of the Spartan-3 data sheet (Module 4, Pinouts) for more
information.
http://direct.xilinx.com/bvdocs/publications/ds099-4.pdf
---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3: Make it Your ASIC

"Amontec Team" <laurent.gauch@www.DELALLCAPSamontec.com> wrote in message
news:3f65851f$1@news.vsnet.ch...

Hi,

For the Spartan-II, the preconfiguration pullup resistors were selected
by the M2 configuration pin. What about for the Spartan-3?

My new design has to connect an ARM7TDMI bus to the SPARTAN-3. I need to
make sure my ucLinux will boot correctly, and so make sure about the IO
pins states of the SPARTAN-3 on the poweron.

Regards,
Laurent

 

[Lasse Langwadt Christense]

Antti Lukats wrote:

"Kenneth Land" <kland1@neuralog1.com> wrote in message news:<vmcl99c2s5jgc0@news.supernews.com>...

Have you looked at the USB 1.1 and 2.0 IP Cores at www.opencores.com?

I looked very closely at the 1.1 version and found it took only 6 pins and
$1.75 transceiver chip.

Ken


there is a japanese design (VHDL, and Visual basic host example)
that uses no tranceiver at all, ie USB DM,DP directly to FPGa

antti

I've thought about that, two pins programmed for 3V3-cmos should be good
for tx and rx of SE0 but I never got around to checking if one of the
differential standards on the FPGA would be within spec for USB?

-Lasse

 

[Antti Lukats]

"Ken Land" <kland1@neuralog1.com> wrote in message news:<vme5iv66sv911@news.supernews.com>...

Is it free?

google usb.lzh
=>
http://member.nifty.ne.jp/fpga/freeip/usb/

found!
antti

 

[rickman]

Lasse Langwadt Christensen wrote:

Antti Lukats wrote:
"Kenneth Land" <kland1@neuralog1.com> wrote in message news:<vmcl99c2s5jgc0@news.supernews.com>...

Have you looked at the USB 1.1 and 2.0 IP Cores at www.opencores.com?

I looked very closely at the 1.1 version and found it took only 6 pins and
$1.75 transceiver chip.

Ken


there is a japanese design (VHDL, and Visual basic host example)
that uses no tranceiver at all, ie USB DM,DP directly to FPGa

antti

I've thought about that, two pins programmed for 3V3-cmos should be good
for tx and rx of SE0 but I never got around to checking if one of the
differential standards on the FPGA would be within spec for USB?

-Lasse

It has been awhile since I looked at the USB spec, but I seem to recall
that there is a non-standard state that is used to signal the rate or
some other aspect of the interface. I want to say this state is both
signals high or both low at the same time. Am I out to lunch on this?

If there is a non-standard state on these pins, you would not be able to
use an LVDS driver. You would need two independant outputs.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Srikanth Anumalla]

Andras Tantos wrote:

The reason I went for fpga was to have wireless networking (802.11)
Actually, the sensors are 3-4 miles apart, I need the data until a
base station from where I will transfer the data to the internet.
the base station is located in the filed and will be 1-2 miles distant
from each sensor. So how do I transfer (in realtime) the data until the
base station from the sensor. Is it possible with PCI micro.
Please suggest me if there is a better solution other than fpga cpu
for doing this (wireless networking).


Doing wireless with FPGA is not easier (nor harder) than with CPUs or MCUs.
You probably will end up using some kind of off-the-selves wireless card and
connect it to your custom application. Of what I understand of your
application probably a wireless USB card would be the best for your
application. Processing power is not an issue in your case. In that case you
need to choose (or implement) a USB host controller but for control even an
8-bit CPU (PIC or AVR or whatever) should be adequate. I don't know of any
8-bit micro that has an USB host (not function!) controller, but there's a
USB interface IC from Cypress, the SL811HS, that can be used as both a host
and a slave controller. So, my suggestion would be:

- Use an 8-bit microcontroller with an external bus (68HC11 from Motorola)
or one with enough of I/O pins (ATmega from Atmel) and probably a with
built-in A/D for the pressure sensors.
- Use the SL811HS from Cypress to implement the USB host controller
- Stick a wireless USB adapter to the unit to implement wireless
- For 1-2 miles you probably need high-gain, directed antennas so choose an
adapter that has external antenna connectivity.

Regards,
Andras Tantos

The solution seems promising, what kind of wireless technology can be
used ? can I use 802.11 or blue tooth or any other.

 

[Andras Tantos]

The solution seems promising, what kind of wireless technology can be
used ? can I use 802.11 or blue tooth or any other.

Whatever you can find a USB device for. 802.11 and blue tooth should both
work. You might have problems getting documentation on how to program these
devices though. I would suggest starting with one that has Linux drivers.
Those usually have open documentation and the Linux driver source is always
a good starting point for questions.

Regards,
Andras Tantos