EDK : FSL macros defined by Xilinx are wrong

[HT-Lab]

"dudesinmexico" <dudesinmexico@gmail.com> wrote in message
news:2e6bf67c-1107-4af3-8452-6b7598a4bf98@25g2000hsx.googlegroups.com...
On Jul 16, 11:57 am, Mike Treseler <mike_trese...@comcast.net> wrote:

dudesinmexico wrote:
Are there any rules of thumb to figure out the equivalent number of
logic resources
needed to implement the same design on Stratix IV vs., say,
Virtex-4/5?
I am thinking of random logic, i.e. a CLB vs. LAB conversion factor...

Quartus will give the exact utilization
and pick a device for you, if you have source code.


I don't, and that's why I am asking... I have a Virtex-4 design and
I'd like to find what Stratix IV
part it will fit in.

dudesinmexico

1) Get an evaluation license for Precision/Synplicity
2) Download a number of large free design from the web
3) Synthesize for Virtex4/Stratix4
4) P&R the designs, compare Area/Delay

IMHO there is very little point in comparing large FPGA's from an
architectural point of view without including the Synthesis/P&R factor.

Hans
www.ht-lab.com

 

[RCIngham]

For anyone but 'raj' who is interested, apparently he is talking about an
as-yet-to-be-released standard:
http://www.mipi.org/wgoverview.shtml

I think he's going to be on his own here...

Toodle-pip!

 

[Krzysztof Wisniewski]

http://www.usb.org/developers/docs/usb_20_040908.zip

 

[Nico Coesel]

Lorenz Kolb <lorenz.kolb@uni-ulm.de> wrote:

Bert wrote:
On 17 jul, 05:00, hal-use...@ip-64-139-1-69.sjc.megapath.net (Hal
Murray) wrote:
Anyway, this is not an academic exercise. Porting a very complex
Virtex4 design
to Stratix is not something that one can do in a few days, so I was
looking
for ballpark estimates about the equivalence between Xilinx and Altera
"gates".
Have you looked at the Stratix data sheet? Did you find anything
close to a CLB/FF pair? If so, assume they are 1:1.

Then count the special things you use: BRAMs, clock buffers, multipliers
and whatevber. Then see if Altera has something similar.

--
These are my opinions, not necessarily my employer's. I hate spam.

Hi,

I have searched before about the comparison Logic Elements and Logic
Cells. Most of the result say LE = LC, but once (@ Altera website) I
found that LE = 1.125*LC

Bye
Bert

This highly depends on the actual design, there are some minor
differences between LEs and LCs that might or might not have an
advantage for certain designs. Nevertheless estimating 1:1 is a fairly
good choice in my opinion. At least as long as you do not want to go
without any reserve of LEs/LCs.

I don't think so. I guess the best estimate is to determine the amount
of flipflops in use in both normal flipflops and LUT ram. You'll need
an Altera device with at least that amount of flipflops. Next thing
you'll need to compare blockrams, multipliers, etc. But the latter is
relatively easy.

--
Programmeren in Almere?
E-mail naar nico@nctdevpuntnl (punt=.)

 

[M.Randelzhofer]

Xilinx Spartan3 XC3S400 has 16 18k Blockrams, Spartan 3E & 3A only has less
BRAMs FPGA's in TQ144.

see:
http://www.xilinx.com/support/documentation/data_sheets/ds099.pdf

However the VQ100 XC3S500E has 20 18k Blockrams.
see:
http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf

BGA rulez.

MIKE

--
www.oho-elektronik.de
OHO-Elektronik
Michael Randelzhofer
FPGA und CPLD Mini Module
Klein aber oho !
Kontakt:
Tel: 08131 339230
mr@oho-elektronik.de
Usst.ID: DE130097310

 

[M.Randelzhofer]

<cs_posting@hotmail.com> schrieb im Newsbeitrag
news:8ef3c779-a9d6-48ea-8a2b-4b4bad01cd86@b1g2000hsg.googlegroups.com...

On Jul 18, 4:47 pm, "M.Randelzhofer" <techsel...@gmx.de> wrote:

However the VQ100 XC3S500E has 20 18k Blockrams.
see:http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf

Thanks - I had not realized this was a possibility. An XC3S500E in a
VQ100 would be perfect, but the question with obscure die / package
combos is if they actually make any of them on a regular basis, or
only if someone orders a hundred thousand and is willing to wait a few
months.

Unfortunately, I'm not seeing anything bigger than the 3S250E actually
for sale in the VQ100 package.

The new package options for S3E and S3A seem not to be available @ digikey
at the moment.

8 weeks ago, i ordered a few of the XC3S500E-4VQG100C parts @ silica,
delivery time was advertised to be 26 weeks, but after 2 weeks they were on
my table.

Similar delivery situation with XC3S50A-4VQG100C. After 1 week, i had them.
I'm still waiting for the XC3S200A-4VQG100C, which are announced to be
delivered in August 2008.

Some more package options for the S3AN would be very appreciated in the
industrial environment.
Product managers often are (very) afraid of the possibility, that one bit in
the configuration memory of the FPGA is toggling by SEU.
S3AN seems to be the best solution for configuration bit verification during
operation.
Maybe there is a serious space problem for the 2 chip S3AN, which doesn't
allow a XC3S400A-TQG144C.

MIKE

--
www.oho-elektronik.de
OHO-Elektronik
Michael Randelzhofer
FPGA und CPLD Mini Module
Klein aber oho !
Kontakt:
Tel: 08131 339230
mr@oho-elektronik.de
Usst.ID: DE130097310

 

[Göran Bilski]

Hi,

Depending a little on how your busy signals work, you might just hook up
your module to the FSL interface on MicroBlaze.
Your busy signal needs be high when it can't accept a new word even when
there is no attempt to write to the module.
MicroBlaze will also just do one cycle write so your module needs to accept
a new word in one clock cycle when busy is low.

Connect:
din(7 downto 0) -> FSL0_M_Data(24 to 31)
din_ready -> FSL0_M_Write
busy -> FSL0_M_Full

You need to enable FSL Interfaces to MicroBlaze with the parameter
C_FSL_LINKS (set it to 1)
You can write to the fsl interface with the function putfslx, you can read
more about this function in the document "OS and Libraries Document
Collection".

Göran

"Ray D." <ray.delvecchio@gmail.com> wrote in message
news:276dce6d-c9ed-4937-95ea-e3c86ff3656a@d45g2000hsc.googlegroups.com...

Hey all,

I have a Xilinx Spartan-3E starter board, and I'm implementing a
MicroBlaze processor on the FPGA. I would also like to use the LCD
which is on board, and I have already developed a hardware module that
takes care of initialization and printing to the LCD. The interface
is shown below:

entity LCD_top is
Port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;

din : in STD_LOGIC_VECTOR (7 downto 0);
din_ready : in STD_LOGIC;
busy : out STD_LOGIC;

LCD_D : out STD_LOGIC_VECTOR (11 downto 8);
LCD_E : out STD_LOGIC;
LCD_RS : out STD_LOGIC;
LCD_RW : out STD_LOGIC

);
end LCD_top;

I really would like to instantiate this module along with the
processor core. My question is this - how would I go about
interfacing this with the MicroBlaze processor internal to the FPGA?
What I would like to do is define a GPIO port on the processor to
connect to the din, din_ready and busy lines of the LCD module, but I
keep getting the following error:

ERROR:MDT - INST:LCD_data_status_10Bit PORT:GPIO_IO
CONNECTOR:LCD_data_status_10Bit_GPIO_IO - C:\EDK_Test_LCD
\system.mhs line 150
- connection is not connected to an external port!
MPD subproperties IOB_STATE=BUF|REG or THREE_STATE=TRUE require
that the port
be connected directly to an external port.

Is there any way to work around this? I realize I could just connect
the LCD to the GPIO directly and write software drivers, but I'm
trying to avoid that because I already have the hardware module in
place and working smoothly. It will also be nice to have this
separate module so that it does the work of printing to the LCD, and
the processor itself can stay busy with other more important jobs.

Also, is there an easier way to add another hardware module without
manually editing the generated VHDL files for the core? I'm not sure
if you can do that within Platform Studio.

Any advice would be much appreciated, thanks!

Ray

 

[RCIngham]

Hi

I was thinking about interfacing PCM4204 audio codec by TI with Xilinx
FPGA XC3S200. Audio serial port I2S needs 3 lines - two clock lines
BCK and LRCK and one data line. I thought it would be good to have
ability to change state of PCM codec between master and slave. In
master mode codec generates both LRCK and BCK clock lines, which are
connected tp my FPGA. In slave mode i need to generate that signals.
Now question - having clock master connected to FPGA (GCLKx Pin) with
12.288 Mhz frequency - can i divide that clock by 256 to have my LRCK
= 44100 Mhz ? Another question is should i use GCLK pins as input/
output for that clocks or it doesn't matter ?

best regards
wj

My calculator says that 12.288 MHz / 44100 Hz = 278.63946, which suggests
that you need a different master clock frequency, or you will have
jitter-related problems.

Whatever you do about the above, don't use GCLK pins. When LRCK is an
input, treat it as a data signal, sample it with the system clock, and
detect the edges as per normal good practice.

 

[M.Randelzhofer]

<wojjed@gmail.com> schrieb im Newsbeitrag
news:56f313a4-cf72-4d40-b478-876b1d7f709e@w7g2000hsa.googlegroups.com...

Hi

I was thinking about interfacing PCM4204 audio codec by TI with Xilinx
FPGA XC3S200. Audio serial port I2S needs 3 lines - two clock lines
BCK and LRCK and one data line. I thought it would be good to have
ability to change state of PCM codec between master and slave. In
master mode codec generates both LRCK and BCK clock lines, which are
connected tp my FPGA. In slave mode i need to generate that signals.
Now question - having clock master connected to FPGA (GCLKx Pin) with
12.288 Mhz frequency - can i divide that clock by 256 to have my LRCK
= 44100 Mhz ? Another question is should i use GCLK pins as input/
output for that clocks or it doesn't matter ?

best regards
wj

Yes you can divide your 12.288MHz clock for LRCLK (WS) and BITCLK (SCK).
A simple sync up counter generates an adequate I2S phase relationship.
see:
http://www.nxp.com/acrobat_download/various/I2SBUS.pdf

Use GCLK for the 12.288MHz master clock input, all other generated signals
can be normal I/Os.

Check if thee is a timing contraint between the ADC system clock (here
12.288MHz) and the lower ADC clocks.

A master clock of 2x or 4x 12.288MHz (49.152MHz) allows equal clock to
output times for all ADC signals.

MIKE

--
www.oho-elektronik.de
OHO-Elektronik
Michael Randelzhofer
FPGA und CPLD Mini Module
Klein aber oho !
Kontakt:
Tel: 08131 339230
mr@oho-elektronik.de
Usst.ID: DE130097310

 

[Göran Bilski]

Hi,

Then it should be a direct match for the FSL interface.
If MicroBlaze executes a 'put' instruction , it will not write until the
FSL_M_Full flag is '0' and when it write it will set the FSL_M Write high
for one clock cycle.
MicroBlaze have plenty of options for the FSL instructions, you can get all
about them in the reference manual.

Göran

"Ray D." <ray.delvecchio@gmail.com> wrote in message
news:693f947e-929e-49f6-939d-d834e0048121@27g2000hsf.googlegroups.com...
On Jul 21, 2:36 am, "Göran Bilski" <goran.bil...@xilinx.com> wrote:

Hi,

Depending a little on how your busy signals work, you might just hook up
your module to the FSL interface on MicroBlaze.
Your busy signal needs be high when it can't accept a new word even when
there is no attempt to write to the module.
MicroBlaze will also just do one cycle write so your module needs to
accept
a new word in one clock cycle when busy is low.

Connect:
din(7 downto 0) -> FSL0_M_Data(24 to 31)
din_ready -> FSL0_M_Write
busy -> FSL0_M_Full

You need to enable FSL Interfaces to MicroBlaze with the parameter
C_FSL_LINKS (set it to 1)
You can write to the fsl interface with the function putfslx, you can read
more about this function in the document "OS and Libraries Document
Collection".

Göran

"Ray D." <ray.delvecc...@gmail.com> wrote in message

news:276dce6d-c9ed-4937-95ea-e3c86ff3656a@d45g2000hsc.googlegroups.com...

Hey all,

I have a Xilinx Spartan-3E starter board, and I'm implementing a
MicroBlaze processor on the FPGA. I would also like to use the LCD
which is on board, and I have already developed a hardware module that
takes care of initialization and printing to the LCD. The interface
is shown below:

entity LCD_top is
Port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;

din : in STD_LOGIC_VECTOR (7 downto 0);
din_ready : in STD_LOGIC;
busy : out STD_LOGIC;

LCD_D : out STD_LOGIC_VECTOR (11 downto 8);
LCD_E : out STD_LOGIC;
LCD_RS : out STD_LOGIC;
LCD_RW : out STD_LOGIC

);
end LCD_top;

I really would like to instantiate this module along with the
processor core. My question is this - how would I go about
interfacing this with the MicroBlaze processor internal to the FPGA?
What I would like to do is define a GPIO port on the processor to
connect to the din, din_ready and busy lines of the LCD module, but I
keep getting the following error:

ERROR:MDT - INST:LCD_data_status_10Bit PORT:GPIO_IO
CONNECTOR:LCD_data_status_10Bit_GPIO_IO - C:\EDK_Test_LCD
\system.mhs line 150
- connection is not connected to an external port!
MPD subproperties IOB_STATE=BUF|REG or THREE_STATE=TRUE require
that the port
be connected directly to an external port.

Is there any way to work around this? I realize I could just connect
the LCD to the GPIO directly and write software drivers, but I'm
trying to avoid that because I already have the hardware module in
place and working smoothly. It will also be nice to have this
separate module so that it does the work of printing to the LCD, and
the processor itself can stay busy with other more important jobs.

Also, is there an easier way to add another hardware module without
manually editing the generated VHDL files for the core? I'm not sure
if you can do that within Platform Studio.

Any advice would be much appreciated, thanks!

Ray

That is how the module works so I'll have to try some of these
options! The busy signal is set high the entire time data is being
written to the LCD. Originally I had a module "program.vhd" that
controlled the LCD module along with a keyboard module that we we had
in place for user input. Within program.vhd, I implement a state
machine and check if the busy signal is high before writing to the
LCD. If busy = 0, then I set din_ready high and set the 8-bits of
data. This is buffered within the LCD module and you only need to
hold din_ready for a single cycle to write to the LCD. The LCD is
connected over a 4-bit interface to the FPGA and this is taken care of
within the LCD module. When the writing operation begins busy is set
to '1' until complete.

Ray

 

[Symon]

"John_H" <newsgroup@johnhandwork.com> wrote in message
news:_YWdnayv8cLc0RjVnZ2dnUVZ_ojinZ2d@comcast.com...

I would respectfully disagree that some hand routing is a complete waste
of energy. When RPMs or explicitly placed logic elements become useful
because of performance needs, one simple step further is to use manual
routing constraints - "directed routing" - that are included in the UCF
(user constraints file).


- John_H

^^ What he said.

Syms.

 

[jaink]

explore wrote:
Thanks for your response. Unfortunately the board was not designed
by us. This is an AVNET PCIe board that we happened to purchase a
while ago. We hadn't put in the XAUI core until recently. Now we are
forced to use the same GTP locations specified in the AVNET user
guide. We were suggested by Xilinx support that we can use the
flexibility of channel bonding available with rocketio's to try and
make timing and this is the reason we are still hopeful of finding a
solution to it. They also told us that some people were successful in
making changes to the channel bonding in AURORA cores and the design
to meet timing when they had a similar problem. As I mentioned
earlier, the design meets timing when the tiles have channel bonding
levels of 5,4,1,0 with 2 pipeline stages for rxchanbond signals, but I
do not get to see it work in simulation. Would like your suggestion/
inputs on this.

Thanks for your time once again.

--Chethan


On Jun 16, 7:31 pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
explore wrote:
I am using a XAUI core in my design for a PCIe board with a Xilinx
Virtex - 5 LX110t FPGA. The board specifications require the GTP
dual
tiles of XAUI to be constrained to locations X0Y0 and X0Y7 which are
far from each other on the FPGA. Due to this, the design does not
meet
timing. The user-guide for the rocketio transceivers suggests
modification of channel bonding attributes of the GTP Dual tiles to
meet timing. To try this out, the default channel bonding level for
the 4 GTP tiles (2 GTP duals) was changed to 3,2,1,0 with 3 as the
master tile. This design works fine in simulation, but does not meet
timing. The timing error as seen on timing analyzer was due to the
rxchanbondo signal.
The channel bond level was further changed to 5,4,1,0 with 5 as the
master. Two pipeline stages were added for the rxchanbondo signal
(between the tiles 4 and 1). This design meets timing, but does not
work in simulation. All these changes were made to the
rocketio_wrapper.v file in the XAUI core generated using coregen.
I feel that the wiring between the tiles in the rocketio_wrapper.v
file needs to be modified to hook-up all the signals that may have
been disturbed due to the addition of the two pipeline stages.
Unfortunately I do not have a lot of experience working with
rocketio
transceivers and their channel bonding attributes which puts me in a
state of bother while analyzing what signals need to be modified/
reassigned/patched between the gtp tiles.
I would appreciate any suggestions from anybody who has had
experience
working with XAUI, rocketio's and their channel bonding attributes.
Thanks for your help in advance
Why are the GTP_DUAL sites constrained to X0Y0 and X0Y7, these are
the
worst possible locations to choose from. If the board hasn't gone
through layout yet, can you change these to be adjacent locations?

Ed McGettigan
--
Xilinx Inc.


Ok, I understand now. I hope that when you take the design forward to
your own platform that you clean this up and don't follow this design.

I was not familiar with this particular board, but I was able to
determine that you are using the Avnet AES-XLX-V5LXT-PCIE110-G board and

after getting the schematics it does show that the XAUI/CX4 interface
that you are trying to use is split across the device using X0Y0 and
X0Y7.

There are a couple of issues with this board design, but I will address
your channel bond timing issue first.

You can make this timing work, but you have to insert additional
registers in the RXCHBONDO[2:0] to RXCHBONDI[2:0] path. These ports use

the faster 10-bit RXUSRCLK clock that will be running at at 312.5MHz in
your application. My guess is that you will need at least 2 register
stages to get across the device at this frequency and you made need
three as the clock-to-out on RXCHBONDO and the setup into RXCHBONDI are
long with respect to a 312.5 MHz clock.

You should place absolute placement LOC attributes on these registers to

ensure that MAP doesn't pack the stages into the same slice and you get
the spread that you need. After you have the timing working you will
then need to set the correct CHAN_BOND_LEVEL value for each lane based
on the number of stages that you used. This is describe in the GTP User

Guide (UG196) Configurable Channel Bonding section.

In addition to channel bonding issue you also have two other issues with

this board that impact your XAUI design.

1) You need to use two REFCLK sources, one for each GTP_DUAL. The board

supports it, but you will likely need to update the XAUI source to add
the second set of inputs to one of the GTP_DUALs.

2) The P/N nets are swapped for some of the pairs. The schematic
indicates that you need to set the TXPOLARITY0 and RXPOLARITY0 on X0Y7
and TXPOLARITY1 on X0Y0 to 1 (default is 0).

Good luck.

Ed McGettigan
--
Xilinx Inc.

Does this help resolve issues? Do you see any other issues with this
board?

 

[FJ.Perogil]

Hello Paco,

With the new code you post I think the problem is the same.
The problem is not only the time spent in context switch, also the
time in system calls is important: pthread_create and pthread_join are
both system calls that will spent many cycles running with interrupts
disabled (can't guess how many, but probably equal or more than a
context switch, you can measure it with another timer if you are
interested in the exact time it's spent).
If you are interested in measuring the time some functions spent, I
recommend you to use another timer and not to use the
xget_clocks_ticks(). If you use another timer, you can use it to count
exact cycles a function call spends, instead making 100000 calls and
calculating the mean time.

Answering your questions:
"Is too heavy the context switch in Xilkernel?" I think it is not too
heavy. I have studied the code and it's quite optimal. If you are
interested I can measure how many cycles it spends.
"Is the context switch done with interrupts disabled?" Yes. A context
switch can be reachead by two ways: a timer interrupt, or a system
call like yield(), pthread_join(), pthread_exit(), etc. In both
situations the interrupts are disabled.

Best regards,

Pablo H

PD. Saludos a Pablo. Cualquier cosa que pueda ayudar no dudes en
preguntar.

Pablo,

I appreciate very much your advices. I will try to use another timer as
you point out.

Saludos,
Paco

 

[HT-Lab]

"Zhane" <me75@hotmail.com> wrote in message
news:68049ba2-0c7a-498e-857b-b951b2a2eef8@z11g2000prl.googlegroups.com...

hmm

I'm getting quite puzzled over this... I've set all my values for
simulation, for my INOUT ports, sender_BUS to be 11111 at
modelsim..but when I run it, my 'outtest' which is supposed to go high
is 'U' instead.

Am I using INOUT the wrong way?
====================================================================
entity sender is
Port ( sender_BUS : inout STD_LOGIC_VECTOR (4 downto 0);
outtest: OUT STD_LOGIC;
sender_CLK : in STD_LOGIC);
end sender;

process(sender_CLK)

process(sender_BUS)

Hans
www.ht-lab.com



if(sender_BUS

begin
if(sender_BUS(4 downto 0) = "11111") then
outtest<='1';

end if;
end process;

 

[Göran Bilski]

Hi,

You don't need the FSL_bus.
You can directly take the MicroBlaze signals FSL0_M_Data, FSL0_M_Full,
FSL0_M_Write and connect them to your module.
If you want to do this in EDK, you will need to create a pcore for your
module and manually connect these signal in XPS.
You can also make these signal external to the EDK project and connect them
in Project Navigator.
It's depend on how your design look now.

Göran

"Ray D." <ray.delvecchio@gmail.com> wrote in message
news:0b840fac-04c0-41a6-8ca1-99593fe48018@l64g2000hse.googlegroups.com...
On Jul 23, 3:26 pm, "Ray D." <ray.delvecc...@gmail.com> wrote:

On Jul 22, 2:34 am, "Göran Bilski" <goran.bil...@xilinx.com> wrote:



Hi,

Then it should be a direct match for the FSL interface.
If MicroBlaze executes a 'put' instruction , it will not write until the
FSL_M_Full flag is '0' and when it write it will set the FSL_M Write
high
for one clock cycle.
MicroBlaze have plenty of options for the FSL instructions, you can get
all
about them in the reference manual.

Göran

"Ray D." <ray.delvecc...@gmail.com> wrote in message

news:693f947e-929e-49f6-939d-d834e0048121@27g2000hsf.googlegroups.com...
On Jul 21, 2:36 am, "Göran Bilski" <goran.bil...@xilinx.com> wrote:

Hi,

Depending a little on how your busy signals work, you might just hook
up
your module to the FSL interface on MicroBlaze.
Your busy signal needs be high when it can't accept a new word even
when
there is no attempt to write to the module.
MicroBlaze will also just do one cycle write so your module needs to
accept
a new word in one clock cycle when busy is low.

Connect:
din(7 downto 0) -> FSL0_M_Data(24 to 31)
din_ready -> FSL0_M_Write
busy -> FSL0_M_Full

You need to enable FSL Interfaces to MicroBlaze with the parameter
C_FSL_LINKS (set it to 1)
You can write to the fsl interface with the function putfslx, you can
read
more about this function in the document "OS and Libraries Document
Collection".

Göran

"Ray D." <ray.delvecc...@gmail.com> wrote in message

news:276dce6d-c9ed-4937-95ea-e3c86ff3656a@d45g2000hsc.googlegroups.com...

Hey all,

I have a Xilinx Spartan-3E starter board, and I'm implementing a
MicroBlaze processor on the FPGA. I would also like to use the LCD
which is on board, and I have already developed a hardware module
that
takes care of initialization and printing to the LCD. The interface
is shown below:

entity LCD_top is
Port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;

din : in STD_LOGIC_VECTOR (7 downto 0);
din_ready : in STD_LOGIC;
busy : out STD_LOGIC;

LCD_D : out STD_LOGIC_VECTOR (11 downto 8);
LCD_E : out STD_LOGIC;
LCD_RS : out STD_LOGIC;
LCD_RW : out STD_LOGIC

);
end LCD_top;

I really would like to instantiate this module along with the
processor core. My question is this - how would I go about
interfacing this with the MicroBlaze processor internal to the FPGA?
What I would like to do is define a GPIO port on the processor to
connect to the din, din_ready and busy lines of the LCD module, but
I
keep getting the following error:

ERROR:MDT - INST:LCD_data_status_10Bit PORT:GPIO_IO
CONNECTOR:LCD_data_status_10Bit_GPIO_IO - C:\EDK_Test_LCD
\system.mhs line 150
- connection is not connected to an external port!
MPD subproperties IOB_STATE=BUF|REG or THREE_STATE=TRUE require
that the port
be connected directly to an external port.

Is there any way to work around this? I realize I could just
connect
the LCD to the GPIO directly and write software drivers, but I'm
trying to avoid that because I already have the hardware module in
place and working smoothly. It will also be nice to have this
separate module so that it does the work of printing to the LCD, and
the processor itself can stay busy with other more important jobs.

Also, is there an easier way to add another hardware module without
manually editing the generated VHDL files for the core? I'm not
sure
if you can do that within Platform Studio.

Any advice would be much appreciated, thanks!

Ray

That is how the module works so I'll have to try some of these
options! The busy signal is set high the entire time data is being
written to the LCD. Originally I had a module "program.vhd" that
controlled the LCD module along with a keyboard module that we we had
in place for user input. Within program.vhd, I implement a state
machine and check if the busy signal is high before writing to the
LCD. If busy = 0, then I set din_ready high and set the 8-bits of
data. This is buffered within the LCD module and you only need to
hold din_ready for a single cycle to write to the LCD. The LCD is
connected over a 4-bit interface to the FPGA and this is taken care of
within the LCD module. When the writing operation begins busy is set
to '1' until complete.

Ray

OK - I'm new to using the EDK and am having trouble implementing this
with the FSL bus. I have a few questions:

1) When I create a custom peripheral, it generates an HDL wrapper - Do
I simply edit this wrapper by instantiating my LCD_top module as a
component within the top level design?

2) Should I check the box "Generate template driver files to help you
implement software interface", or will the provided functions to read
and write to the FSL bus suffice?

3) Do you know of any good tutorials on how to implement a custom
peripheral on the FSL bus? I've come across a few for adding
peripherals to the other buses, but most that I have found do not
follow through with how to edit the VHDL files and correctly add the
peripheral to the system in Platform Studio (they simply tell you go
to 'Create/Import Custom Peripheral').

Any help/input is appreciated, thanks!

Ray

Two more things -

1) the four output ports of the LCD module must be connected to the
external FPGA pins in order to drive the LCD. What is the best way to
go about doing this? Is this something that can be edited within
Platform Studio or do I need to manually edit VHDL/UCF files? I'm
assuming I will have to add the outputs to the interface shown below.

2) When I choose the master interface for the FSL bus, the ports are
defined as follows:

-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
FSL_Clk : in std_logic;
FSL_Rst : in std_logic;
FSL_S_Clk : out std_logic;
FSL_S_Read : out std_logic;
FSL_S_Data : in std_logic_vector(0 to 31);
FSL_S_Control : in std_logic;
FSL_S_Exists : in std_logic;
FSL_M_Clk : out std_logic;
FSL_M_Write : out std_logic;
FSL_M_Data : out std_logic_vector(0 to 31);
FSL_M_Control : out std_logic;
FSL_M_Full : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------

You mention that my din(7 downto 0) port should be connected to the
FSL_M_Data port, but the former is an input while the latter is an
output. Am I missing something? I tried to define this as a slave
interface, but that also yields an error when I try to generate the
bitstream.

Thanks.

 

[Göran Bilski]

Hi,

A pcore in EDK contains the HDL files and a set of data files.
All files are in ASCII format.
The hdl files is in pcores/<your module>_vX_XX_a/hdl/vhdl
The data files is in pcores/<your module>_vX_XX_a/data

There are two data files that you need.
First the .pao file which contains a the list of HDL files that your module
need.
It can contain reference to other pcores libraries if needed
The second is the .mpd files which contains all information XPS needs.
It contains: type of core, what bus interfaces exists, which
parameters/generics, signals,..

There is a document in the installation describing these files, the data
files is called PSF files.
When you use "Create and Import Peripheral" it creates the data files for
you.
You can also look in existing pcores to see what they contains.

The fit_timer in EDK is very simple and should give you a hint how to create
a pcore for your LCD module.
You don't need any bus interfaces, just pure signals.

Göran

"Ray D." <ray.delvecchio@gmail.com> wrote in message
news:61bf0515-e8b9-44fb-9e8f-268ca7ed6bca@i24g2000prf.googlegroups.com...
On Jul 24, 2:44 am, "Göran Bilski" <goran.bil...@xilinx.com> wrote:

Hi,

You don't need the FSL_bus.
You can directly take the MicroBlaze signals FSL0_M_Data, FSL0_M_Full,
FSL0_M_Write and connect them to your module.
If you want to do this in EDK, you will need to create a pcore for your
module and manually connect these signal in XPS.
You can also make these signal external to the EDK project and connect
them
in Project Navigator.
It's depend on how your design look now.

Göran

"Ray D." <ray.delvecc...@gmail.com> wrote in message

news:0b840fac-04c0-41a6-8ca1-99593fe48018@l64g2000hse.googlegroups.com...
On Jul 23, 3:26 pm, "Ray D." <ray.delvecc...@gmail.com> wrote:



On Jul 22, 2:34 am, "Göran Bilski" <goran.bil...@xilinx.com> wrote:

Hi,

Then it should be a direct match for the FSL interface.
If MicroBlaze executes a 'put' instruction , it will not write until
the
FSL_M_Full flag is '0' and when it write it will set the FSL_M Write
high
for one clock cycle.
MicroBlaze have plenty of options for the FSL instructions, you can
get
all
about them in the reference manual.

Göran

"Ray D." <ray.delvecc...@gmail.com> wrote in message

news:693f947e-929e-49f6-939d-d834e0048121@27g2000hsf.googlegroups.com...
On Jul 21, 2:36 am, "Göran Bilski" <goran.bil...@xilinx.com> wrote:

Hi,

Depending a little on how your busy signals work, you might just
hook
up
your module to the FSL interface on MicroBlaze.
Your busy signal needs be high when it can't accept a new word even
when
there is no attempt to write to the module.
MicroBlaze will also just do one cycle write so your module needs to
accept
a new word in one clock cycle when busy is low.

Connect:
din(7 downto 0) -> FSL0_M_Data(24 to 31)
din_ready -> FSL0_M_Write
busy -> FSL0_M_Full

You need to enable FSL Interfaces to MicroBlaze with the parameter
C_FSL_LINKS (set it to 1)
You can write to the fsl interface with the function putfslx, you
can
read
more about this function in the document "OS and Libraries Document
Collection".

Göran

"Ray D." <ray.delvecc...@gmail.com> wrote in message

news:276dce6d-c9ed-4937-95ea-e3c86ff3656a@d45g2000hsc.googlegroups.com...

Hey all,

I have a Xilinx Spartan-3E starter board, and I'm implementing a
MicroBlaze processor on the FPGA. I would also like to use the
LCD
which is on board, and I have already developed a hardware module
that
takes care of initialization and printing to the LCD. The
interface
is shown below:

entity LCD_top is
Port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;

din : in STD_LOGIC_VECTOR (7 downto 0);
din_ready : in STD_LOGIC;
busy : out STD_LOGIC;

LCD_D : out STD_LOGIC_VECTOR (11 downto 8);
LCD_E : out STD_LOGIC;
LCD_RS : out STD_LOGIC;
LCD_RW : out STD_LOGIC

);
end LCD_top;

I really would like to instantiate this module along with the
processor core. My question is this - how would I go about
interfacing this with the MicroBlaze processor internal to the
FPGA?
What I would like to do is define a GPIO port on the processor to
connect to the din, din_ready and busy lines of the LCD module,
but
I
keep getting the following error:

ERROR:MDT - INST:LCD_data_status_10Bit PORT:GPIO_IO
CONNECTOR:LCD_data_status_10Bit_GPIO_IO - C:\EDK_Test_LCD
\system.mhs line 150
- connection is not connected to an external port!
MPD subproperties IOB_STATE=BUF|REG or THREE_STATE=TRUE require
that the port
be connected directly to an external port.

Is there any way to work around this? I realize I could just
connect
the LCD to the GPIO directly and write software drivers, but I'm
trying to avoid that because I already have the hardware module in
place and working smoothly. It will also be nice to have this
separate module so that it does the work of printing to the LCD,
and
the processor itself can stay busy with other more important jobs.

Also, is there an easier way to add another hardware module
without
manually editing the generated VHDL files for the core? I'm not
sure
if you can do that within Platform Studio.

Any advice would be much appreciated, thanks!

Ray

That is how the module works so I'll have to try some of these
options! The busy signal is set high the entire time data is being
written to the LCD. Originally I had a module "program.vhd" that
controlled the LCD module along with a keyboard module that we we had
in place for user input. Within program.vhd, I implement a state
machine and check if the busy signal is high before writing to the
LCD. If busy = 0, then I set din_ready high and set the 8-bits of
data. This is buffered within the LCD module and you only need to
hold din_ready for a single cycle to write to the LCD. The LCD is
connected over a 4-bit interface to the FPGA and this is taken care of
within the LCD module. When the writing operation begins busy is set
to '1' until complete.

Ray

OK - I'm new to using the EDK and am having trouble implementing this
with the FSL bus. I have a few questions:

1) When I create a custom peripheral, it generates an HDL wrapper - Do
I simply edit this wrapper by instantiating my LCD_top module as a
component within the top level design?

2) Should I check the box "Generate template driver files to help you
implement software interface", or will the provided functions to read
and write to the FSL bus suffice?

3) Do you know of any good tutorials on how to implement a custom
peripheral on the FSL bus? I've come across a few for adding
peripherals to the other buses, but most that I have found do not
follow through with how to edit the VHDL files and correctly add the
peripheral to the system in Platform Studio (they simply tell you go
to 'Create/Import Custom Peripheral').

Any help/input is appreciated, thanks!

Ray

Two more things -

1) the four output ports of the LCD module must be connected to the
external FPGA pins in order to drive the LCD. What is the best way to
go about doing this? Is this something that can be edited within
Platform Studio or do I need to manually edit VHDL/UCF files? I'm
assuming I will have to add the outputs to the interface shown below.

2) When I choose the master interface for the FSL bus, the ports are
defined as follows:

-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
FSL_Clk : in std_logic;
FSL_Rst : in std_logic;
FSL_S_Clk : out std_logic;
FSL_S_Read : out std_logic;
FSL_S_Data : in std_logic_vector(0 to 31);
FSL_S_Control : in std_logic;
FSL_S_Exists : in std_logic;
FSL_M_Clk : out std_logic;
FSL_M_Write : out std_logic;
FSL_M_Data : out std_logic_vector(0 to 31);
FSL_M_Control : out std_logic;
FSL_M_Full : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------

You mention that my din(7 downto 0) port should be connected to the
FSL_M_Data port, but the former is an input while the latter is an
output. Am I missing something? I tried to define this as a slave
interface, but that also yields an error when I try to generate the
bitstream.

Thanks.

I think I understand what you are saying, but I'm still unsure of how
to implement it. I went through the 'Create and Import Peripheral'
wizard to create the pcore and HDL wrapper file, but when you go
through this it asks which bus you wish to attach the peripheral to -
this generated HDL file is an interface file for the FSL bus,
correct? I assumed I needed to edit this file and place my LCD module
within this interface file (with the interface shown in my previous
message). Do I need to go through this wizard to directly connect to
the FSL interface or is this the incorrect method?

When you say directly take the MicroBlaze signal and connect them to
my module, do you mean edit the aforementioned wrapper file for the
pcore, or is there an alternative way? Is there a top level VHD file
that I need to edit in order to port the LCD module output to the
external FPGA pins?

I realize these probably are simple questions but since I've never
been through this process within the EDK (and can't find any good
tutorials - most deal with adding peripheral to OPB or PLB bus), I'm
having a hard time figuring out which steps I need to take in order to
accomplish what you have suggested.

Anyway, I really do appreciate all your help so far. Thank you!

Ray

 

[RCIngham]

And just how does this relate to FPGAs?

(Can a moderator delete this thread?)

 

[Fred]

"Zhane" <me75@hotmail.com> wrote in message
news:ab0ae7bc-b7a5-47bd-bc2e-33d350f3026a@n33g2000pri.googlegroups.com...

are there any vhdl codes that are available for free to debounce the
pushbutton on my spartan 3E?

I require the push button to generate only 1 clock for 50mhz only upon
release.

I've gotten some code from the net but aint sure if it does what I
need....

==============================================================

library ieee;
use ieee.std_logic_1164.all;

entity debouncer is
port (clk,reset: in std_logic; -- clk frequency = 50Mhz
pb: in std_logic;
pb_debounced: out std_logic
);
end entity debouncer;

architecture rtl of debouncer is
signal count500000 : integer range 0 to 499999;
signal clk_100Hz: std_logic;
signal pb_sampled: std_logic;
begin

div_100Hz: process(clk,reset) is
begin
if reset ='1' then
clk_100Hz <= '0';
count500000 <= 0;
elsif rising_edge(clk) then
if count500000 = 499999 then
count500000 <= 0;
clk_100Hz <='1';
else
count500000 <= count500000 + 1;
clk_100Hz <='0';
end if;
end if;
end process div_100Hz;

debounce_pb: process(clk) is
begin
if rising_edge(clk) then
if clk_100Hz ='1' then
if pb = pb_sampled then
pb_debounced <= pb;
end if;
pb_sampled <= pb;
end if;
end if;
end process debounce_pb;

end architecture rtl;
==================================================

pls advise

There are a few methods of debouncing switches.

One way of thinking is what's the minimum period between switch operations,
then having a timer-counter to ensure that another swich operations can't
occur during this period.

constant integer max := xxxxx;

if reset then
timer_count = 0;
pb_debounced = '0';

else rising_edge(clk) then
if pb = '0' then
if timer_count = max then
pb_debounced <= '1';
timer_count <= 0;
else
timer_count <= 0;
end if;
else
if timer_count = max then
pb_debounced <= '1';
else
timer_count <= timer_count +1;
end if;
end if;
end if;

E&OE!

 

[peter]

Hello,
please let me know which one is the right newsgroup that I can ask question
about industrial robotics shool in dallas texas area. thanks

Peter

 

[Symon]

"Zhane" <me75@hotmail.com> wrote in message
news:a0d26059-8dae-4527-a877-8f7a29aa391c@p10g2000prf.googlegroups.com...

Checking expanded design ...
ERROR:NgdBuild:924 - bidirect pad net 'sender_BUS<4>' is driving non-
buffer
primitives:

what can I do?

You can not connect directly to the PADs but instead you should connect to
the signals on the fabric side of the IBUFs and OBUFs.
HTH., Syms.