EDK : FSL macros defined by Xilinx are wrong

[Nial Stewart]

Not new, but perhaps skeptical.

I'd also be sceptical of someone with no feedback.

I've been stung twice on ebay, once with counterfeit razors, the second
time with counterfeit Sony MDR-EX71 headphones.

Both times the copies looked _very_ good, but the razors were blunt
as (insert favourite swear word starting with 'f'), the headphones fell
apart after a weeks light use so I got my money back.

The headphones were a very good copy and didn't sound bad, it was
only when I bought a real set through Amazon I could see the differences.

I've got 100% feedback so was wary about leaving negative feedback
about these in case I got negative feedback in return :-(



Nial.

 

[HT-Lab]

<ekavirsrikanth@gmail.com> wrote in message
news:51facbfd-43fa-4247-810e-51c7d658ec5b@c65g2000hsa.googlegroups.com...

Hi All,

How to identify the Multi cycle path and the False path in the design.
do we need to identify after the Synthesis stage xilinx fpga tool it
self will recognize and through as warning or error.

If this is a medium/high budget project I would speak to the Fishtail
(http://www.fishtail-da.com/) guys. Their Focus product will automatically
find most(all?) MCP/FP in your design and output the result to a constraints
file. I believe both Precision/Synplicity are supported. This is a great
product but as I mentioned mostly for the big guys.

If you have to do this manually then start by looking at the most negative
slack path and simply plough through the code/schematics to see if that path
is false/multicycle or not. It is not going to be easy or quick especially
for false path. If you have access to a formal tool or PSL/SVA support for
your simulator then you might be able to write a property to check that, for
example, and enable pin on the output of a long combinatorial path FF is
always stable for more than 1 clockcycle.

Hans.
www.ht-lab.com

At what stage in the asic flow this multicycle path and False path are
identified. How to fix this Multi cycle path and false path in the
fpga flow

How it is going to effect the Timing Closure and the Slack of the
design.


regards
kil

 

[Tony Burch]

"vignesh_karthi" <pvprabhuraj@gmail.com> wrote in message
news:ecf5b59d-ba57-4c5f-9b30-93f0ff38e2f6@59g2000hsb.googlegroups.com...

My name is vignesh.

I am also new guy to Xilinx .. i want to know the following things...
please help me...

1. how can i create the *.ucf file using xilinx Tool ? (if you have
provide me )

2. how can i avoid the multicycle path and false path ? (if you have
provide me )

3. Do you have any basic user manual for xilinx tool ? (if you have
provide me )


Advanced Thanks to you...

Hi Vignesh,

Since you are just getting started, the videos at
http://www.burched.com/freevideos.ag.php may help you. Many basic questions
are covered.

My "Single Top FPGA Tips" might also be helpful
http://www.burched.com/fpgatoptips11.pdf

Best regards,
Tony Burch

 

[kami]

On Jun 18, 8:09=A0am, faza <fazulu.v...@gmail.com> wrote:
Hai,

I want to know which is the right way of implementing and usage of
fixed point number data types in hardware(industry standard)..I have
referred various FIR
implementations where they are mostly handling filter coefficients as
integer(truncating from fixed or floating point using MATLAB) or
binary.Is it difficult to handle and implement real(fraction) numbers
i.e.,filter
coefficients values directly in the hardware?


Google for fixed point VHDL to_ufixed and you'll get the code for the
standard (or soon to be a standard) VHDL fixed point package.

http://www.google.com/search?source=3Dig&hl=3Den&rlz=3D1G1GGLQ_ENUS278&q=3D=
fixed+point+VHDL+to_ufixed

Kevin Jennings

Hi there, I am implementing IIR filter in VHDL for Spart-3 FPGA Target. I
have found these packages you mentioned in response to this guy's question,
very good. But I don't exactly understand how to use these packages?
Any other comments welcome.
I am designing a butterworth lowpass filter (atm just 2nd order filter). I
have implemented it in simulink and could generate VHDL code as well but I
am trying to write the code myself. or atleast with a different approach
because that HDL code generated from Simulink just converts the
coefficients values manually and treat it as a signed number (converted
from an integer value of a fractional binary conversion of a floating point
number).
Anyways, If I couldn't explain this Simulink thing very well, then I beg
ur pardon but it'll be handy if u could tell about that ficed point
packages? And I could discuss this SIMULINK thing further if u wish.
Thanks very much,
Kami

 

[kami]

On Jul 11, 2:40 pm, "kami" <kamran.wad...@yahoo.co.uk> wrote:
On Jun 18, 8:09=A0am, faza <fazulu.v...@gmail.com> wrote:
Hai,

I want to know which is the right way of implementing and usage of
fixed point number data types in hardware(industry standard)..I
have
referred various FIR
implementations where they are mostly handling filter coefficients
as
integer(truncating from fixed or floating point using MATLAB) or
binary.Is it difficult to handle and implement real(fraction)
numbers
i.e.,filter
coefficients values directly in the hardware?

Google for fixed point VHDL to_ufixed and you'll get the code for the
standard (or soon to be a standard) VHDL fixed point package.


http://www.google.com/search?source=3Dig&hl=3Den&rlz=3D1G1GGLQ_ENUS27...
fixed+point+VHDL+to_ufixed

Kevin Jennings

Hi there, I am implementing IIR filter in VHDL for Spart-3 FPGA Target.
I
have found these packages you mentioned in response to this guy's
question,
very good. But I don't exactly understand how to use these packages?
Any other comments welcome.
I am designing a butterworth lowpass filter (atm just 2nd order
filter). I
have implemented it in simulink and could generate VHDL code as well
but I
am trying to write the code myself. or atleast with a different
approach
because that HDL code generated from Simulink just converts the
coefficients values manually and treat it as a signed number
(converted
from an integer value of a fractional binary conversion of a floating
point
number).
Anyways, If I couldn't explain this Simulink thing very well, then I
beg
ur pardon but it'll be handy if u could tell about that ficed point
packages? And I could discuss this SIMULINK thing further if u wish.
Thanks very much,
Kami

I'm not sure the other posts have made this clear, the package
described here is not a signal processing tool. It is just a fixed
point math library. You still have to figure out how to do the signal
processing. This library gives you the low level tools to implement
fixed point math in the FPGA.

Rick

Hi Rick,
Yes that's right. I am trying to implement fixed-point math in VHDL (for
FPGA implementation). and this is for filter coefficients. If I am able to
implement that DF-II diagram of the IIR butterworth lowpass filter, won't
it be signal processing? I guess so. That's what I am trying to do. I mean
perform some additions and multiplications on the input data (which ideally
should be a sinusoidal wave or sth but anyhow,) and the filter coefficients
which i can take as the constants coz I already know their values. so,
that's what it basically is.
Any comments/suggestions welcome.
Much Appreciated,
Kami

 

[Icky Thwacket]

"Zhane" <me75@hotmail.com> wrote in message
news:4fea5c5c-f3d4-43e6-9a2a-2759c4b3c9e1@59g2000hsb.googlegroups.com...

I've gotten the following code for the baudrate generator from
opencores

Holy crap! - you mean places actually exist for downloading such trivial
code?
You cannot be THAT interested in FPGA design if you have to download such
stuff as this - I summize that this is not your real vocation as you cannot
have enough interest to work out such trivia - get a job elsewhere!

I've created a Test Bench Waveform for it from my ISE.

Well wooppee doooo

Using single clock, Rising edge, Clock High/Low time as 3, Input setup/
Output Valid delay/ Offset as 0

when i run it in modelsim, I dont get any errors, neither do I get any
waves from baud_x_en or baud_en.

LOL - I would have thought no output was a fundamental major error?

======================
-----------------------------------------------------------------------------

snipped - loadsa copied crap

 

[KJ]

"HT-Lab" <hans64@ht-lab.com> wrote in message
news:GEEdk.197564$8k.113349@newsfe18.ams2...

It is not going to be easy or quick especially for false path.

If done manually, it's most likely going to be done incorrectly.

KJ

 

[KJ]

"Zhane" <me75@hotmail.com> wrote in message
news:78158230-6b76-447c-b0d6-6ab57c7b207f@w7g2000hsa.googlegroups.com...
On Jul 12, 11:28 pm, Gabor <ga...@alacron.com> wrote:

UART to find the center of a bit time. 4x is usually
a minimum number for the receiver to work reliably.
Modern UARTs usually have 16x oversampling. I would
suggest finding a paper on UARTs and getting an
understanding of the process involved in receiving
asynchronous data. It's really not complex and at
some point you may actually enjoy designing your
own UART.

Regards,
Gabor

hmm.. actually i only want to transmit...

Oversampling is for the UART receiver

so 4x should be more than
sufficient right?

1x is sufficient for transmit

KJ

 

[kami]

On Jul 11, 9:02 pm, "kami" <kamran.wad...@yahoo.co.uk> wrote:
On Jul 11, 2:40 pm, "kami" <kamran.wad...@yahoo.co.uk> wrote:
On Jun 18, 8:09=A0am, faza <fazulu.v...@gmail.com> wrote:
Hai,

I want to know which is the right way of implementing and usage
of
fixed point number data types in hardware(industry standard)..I
have
referred various FIR
implementations where they are mostly handling filter
coefficients
as
integer(truncating from fixed or floating point using MATLAB) or
binary.Is it difficult to handle and implement real(fraction)
numbers
i.e.,filter
coefficients values directly in the hardware?

Google for fixed point VHDL to_ufixed and you'll get the code for
the
standard (or soon to be a standard) VHDL fixed point package.


http://www.google.com/search?source=3Dig&hl=3Den&rlz=3D1G1GGLQ_ENUS27...
fixed+point+VHDL+to_ufixed

Kevin Jennings

Hi there, I am implementing IIR filter in VHDL for Spart-3 FPGA
Target.
I
have found these packages you mentioned in response to this guy's
question,
very good. But I don't exactly understand how to use these
packages?
Any other comments welcome.
I am designing a butterworth lowpass filter (atm just 2nd order
filter). I
have implemented it in simulink and could generate VHDL code as
well
but I
am trying to write the code myself. or atleast with a different
approach
because that HDL code generated from Simulink just converts the
coefficients values manually and treat it as a signed number
(converted
from an integer value of a fractional binary conversion of a
floating
point
number).
Anyways, If I couldn't explain this Simulink thing very well, then
I
beg
ur pardon but it'll be handy if u could tell about that ficed point
packages? And I could discuss this SIMULINK thing further if u
wish.
Thanks very much,
Kami

I'm not sure the other posts have made this clear, the package
described here is not a signal processing tool. It is just a fixed
point math library. You still have to figure out how to do the
signal
processing. This library gives you the low level tools to implement
fixed point math in the FPGA.

Rick

Hi Rick,
Yes that's right. I am trying to implement fixed-point math in VHDL
(for
FPGA implementation). and this is for filter coefficients. If I am able
to
implement that DF-II diagram of the IIR butterworth lowpass filter,
won't
it be signal processing? I guess so. That's what I am trying to do. I
mean
perform some additions and multiplications on the input data (which
ideally
should be a sinusoidal wave or sth but anyhow,) and the filter
coefficients
which i can take as the constants coz I already know their values. so,
that's what it basically is.
Any comments/suggestions welcome.
Much Appreciated,

So the question is, do you understand the signal processing? If you
understand that, then you need to analyze the algorithm in fixed point
arithmetic before you try to implement it in hardware. I prefer to
use fractions for all of my numbers, both the input data and the
coefficients. Then the multiply won't overflow. Of course it can
underflow, but that is not as hard to handle.

So start by working in floating point arithmetic using numbers between
1 and -1. Then scale this to fixed point values. Once you have the
simulation running you can try implementing it in hardware.

Rick

Well, Yes I do understand the signal processing (am not an expert thought)
but I've already implemented the design in SIMULINK. it's a butterworth
lowpass filter which can be used in a digital touch tone receiver. with the
specs: Fc=852Hz, F2(stop-band freq = 2000Hz) Fs=8000Hz and SB
Attenuation>=15dB. I have already implemented it in SIMULINK using FDA tool
and generated HDL code as well.
I have also implemented the DF-II block diagram in simulink after manually
calculating the coefficients values and the difference equation. So, now I
am trying to implement this block diagram for the filter in VHDL and I
already know the values of coefficients and input can be anything. Now, I
need to implement this using fixed-point arithematic. That's what I am
trying to implement. Ofcourse I am looking for simulation at the moment but
once I get the simulation right, I can implement it on FPGA. In short, if
you meant, I need to do MATLAB implementation first, then as I've said
earlier, I've done that.
Thanks,
Kami

 

[KJ]

<dadabuley@gmail.com> wrote in message
news:3a37a0c3-7557-4774-8d80-6f5ca750775f@2g2000hsn.googlegroups.com...
On 7ÔÂ12ČŐ, ĎÂÎç10Ęą13ˇÖ, Gabor <ga...@alacron.com> wrote:

I think maybe caused by the DQS sampleing or the DDR initial process
problem.
is this problems seems like DDR SDRAM problem or The DDR Controller
problem?

It could be a read problem (like sampling at the wrong time) or a write
problem. You need to perform timing analysis. In any case, it's most
likely not a problem with the DDR Controller logic itself. Do a thorough
timing analysis.

KJ

 

[kami]

On Jul 11, 2:40=A0pm, "kami" <kamran.wad...@yahoo.co.uk> wrote:

Hi there, I am implementing IIR filter in VHDL for Spart-3 FPGA Target.
I
have found these packages you mentioned in response to this guy's
questio=
n,
very good. But I don't exactly understand how to use these packages?
Any other comments welcome.

The packages come with a testbench and documentation that explains how
to use them. Read those first, then post more specific questions here
if you have any.

KJ

Hi KJ,

I've visited the site VHDL.org and read the following:

http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/Fixed_ug.pdf

and
http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/files.html

and i think the stuff on Accelera website is also the same apart from some
nice powerpoint presentations.
I could understand the logic behind these packages and they sounds really
very good (especially in my case) I mean positive and negative indices have
been used to differentiate the integer and fractional part. That's great.
But, I can't understand how to compile and add these packages to my
library? Do I need to use Modelsim for this purpose or Xilinx?
I mean how to compile it? Do I need to copy the .vhdl files of those
packages in the IEEE folder or vhdl source folder where some other
libraries are or what?
I'll be very thankful if you could give me a direction at least,
Thanks,
kami

 

[KJ]

<dadabuley@gmail.com> wrote in message
news:e69b52bd-3aaa-4e69-bd14-dab96b3bdfec@34g2000hsf.googlegroups.com...

It could be a read problem (like sampling at the wrong time) or a write
problem. You need to perform timing analysis. In any case, it's most
likely not a problem with the DDR Controller logic itself. Do a thorough
timing analysis.

KJ
Thanks for your advice.
I use osilliscope analysis the timing wave on board and find the
timing for DATA and DQS are good.
and DDR works good when system power up, error just happend after I
reset all logic.

Then apparently the outputs of the FPGA are causing data to be overwritten
when you 'reset all logic'. How long of a reset is this anyway? Long
enough that the DDR is not getting properly refreshed perhaps?

The only way the contents of the memory can change is by writing to it
(maybe during a reset the controller outputs appear to the DDR as a memory
write) or by lack of refresh...or a faulty memory device, but if this is
happening only under certain specific conditions that wouldn't seem likely.
There are no other reasons.
KJ

 

[KJ]

"kami" <kamran.wadood@yahoo.co.uk> wrote in message
news:nPidnRBnHeWspOTV4p2dnAA@giganews.com...

But, I can't understand how to compile and add these packages to my
library?

If I recall correctly, they expect to be compiled into an 'ieee_proposed'
library.

Do I need to use Modelsim for this purpose or Xilinx?

Depends what your purpose is. Modelsim is used for simulation, Xilinx is a
big company that sells FPGAs.

I mean how to compile it? Do I need to copy the .vhdl files of those
packages in the IEEE folder or vhdl source folder where some other
libraries are or what?

Put the source files wherever you want to. Then compile those files. If
you don't know how to do that then perhaps you need to understand what tool
you're using first and should go to the manual for that first.

I'll be very thankful if you could give me a direction at least,

Head in the direction of the manuals for the software you are using.

KJ

 

[RCIngham]

When running XST then XST is analysing an entity for ages that contains
the following piece of code.

if (signal1 = '1')
for I in 0 to 15 loop
if (signal2(I) = '0') then
Table0(conv_integer(Table(I)) <= '0';
end if;
end loop;
end if;


Maybe unrolling the loop should solve the problem? Or is there any other

thing that I could change so that the code sythesises?

The lack of an obvious clock signal may have comething to do with it. Post
the entire process, including sensitivity list, and you may get a more
definitive answer.

 

[jtw]

If you use the block RAMs as read-before-write, you will not see the update
until read-with-enable (or multiple, sequential write enables.)

For this, you do not need to use CoreGen; you can just instantiate the
library directly, and apply the appropriate attributes. See the appropriate
Xilinx library document.

JTW

"Vandana" <nairvan@gmail.com> wrote in message
news:9200d206-2e95-4c4a-ba05-034d46dba03c@l64g2000hse.googlegroups.com...

On Jul 14, 11:08 am, Gabor <ga...@alacron.com> wrote:
On Jul 14, 10:26 am, Vandana <nair...@gmail.com> wrote:



Hello,

Im new to Xilinx core generator tool and have a very fundamental
question. I want to generate a single port RAM with an enable signal
for the READ operation and the WRITE operation.

The write operation works fine. For the read operation, I want to see
the output only when a read_enable signal is asserted. I used the "ENA
pin" but when asserted I dont see the required output. When I choose
the option "Always enabled", it works fine and I see the previous
output always. But I want the output only when the read_enable signal
is asserted.

Can this be done? Thanks for your help.

--Vandana

If your memory is generated with block RAM, the ENA pin is actually
common
to read and write for the single port RAM. So writing will update the
data outputs unless you have specified a RAM with output registers and
a separate register enable. Also, the output from the block ram will
always update on the cycle after the ENA pin is asserted. If you want
asynchronous readout, you need to use distributed memory instead.

Regards,
Gabor

Thanks, I realised the ENA pin is common to Read/Write and Reset.

 

[jtw]

"Brian Drummond" <brian_drummond@btconnect.com> wrote in message
news:ukgm749980f7j127kv2smh4hok8e24jifj@4ax.com...

On Sun, 13 Jul 2008 17:21:23 -0700 (PDT), Andrew FPGA
andrew.newsgroup@gmail.com> wrote:

Hi,
I have designed a VHDL entity that is a subset of the complete design.
I have verified its functionality with a simulation in modelsim and
now I want to run it through the xilinx synthesis(XST) and place and
route tools to verify it meets timing. This entity is a subset of the
complete design, and one of its output ports contains a large number
of signals(several thousand). This fails to map since our target FPGA
does not have several thousand IO pads. How can I run this sub module
through the PAR tools to verify I meet timing?

You can get it through synthesis, and use the synthesis timing estimate
as an indicator whether you are on track for timing or not.

The synthesis tool provides a statistical estimate of the delays. Using the
mapper option to not strip out unused ports permits accurate measurement of
achievable timing, which can be very useful for early identification of
problem areas.

JTW

IMO there is no point taking it further; the synthesis timing estimates
are slightly conservative in my experience (though they may be accurate
for a 95% full FPGA) so you stand a good chance of exceeding them in
PAR.

On the other hand, PAR results for a block will probably NOT be repeated
when the same block is incorporated into the whole design. As you fill
up the rest of the FPGA with other stuff, the PAR tools are much more
restricted in their ability to find good fast placement and routes. So
you may believe your timings are achievable based on PAR in an almost
empty FPGA, while in reality they are not, for the entire design.


Here is what I have tried so far:
1) IOB over mapping problem solved by unchecking the XST "add I/O
buffers" option.

This is the one. It gets you through synthesis, and that gives you
estimated timings above.

However, the mapper rightfully strips the whole
design since there are now no inputs or outputs.

You *could* create a wrapper with registers on your unit's ports, and
some simple means of combining a thousand pins into a few (e.g. n-way
multiplexer, controlled by a few further external pins). You NEED the
registers; either 2 levels of registers, or ensure registers are NOT
moved into the IOBs, and CHECK the map.mrp report file to make sure that
they aren't. Routes from IOBs into the FPGA fabric can be unbelievably
slow, so you need registers in the fabric...

Then you have a viable synthesisable unit which can be run through
mapping and PAR.

But, as above, beware of trusting the timing results if the final design
will be significantly larger. If the synthesis estimates aren't good
enough, these probably aren't either.

- Brian

 

[Uwe Bonnes]

Tom P <poliquin@softcomp.remove-this.com> wrote:

On Wed, 25 Jun 2008 11:06:28 -0700, Alex.Louie wrote:

On Jun 25, 7:04 am, muthu...@gmail.com wrote:
Friends,

I have been using the Xilinx tools ISE, EDK in Windows environment.
But now planning to use Linux PC for running ISE and EDK. I am
curious, which platform (Windows or Linux) is good for Xilinx tools?
I am planning to use the ISE and EDK in GUI mode, not command line
mode.


I am using ISE 10.1 on Linux Fedora 5 (old), kernel 2.6.20-1.2316.fc5
and it works great! The USB cable programmer also works well. Xilinx
finally did it right and used libusb (standard), so no complicated
drive install. Newer versions of Fedora should work fine.

Xilinx only did it half way right. For the parallel port cables they still
use WinDriver instead of /dev/ppdev access. And there is no JTAG API to
make custom adapters known to Impact.

For the parallel port, libusb-driver http://rmdir.de/~michael/xilinx/ still
comes handy
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

 

[Symon]

"Andrew FPGA" <andrew.newsgroup@gmail.com> wrote in message
news:b8b06151-90c0-4115-a643-35a539d57e49@c58g2000hsc.googlegroups.com...

Hi FPGA Folk,
Is there any xilinx or other documentation that describes what these
symbols mean? E.g. Tcko, Tbxcy, Tcinck?

Andrew,

file:///C:/Xilinx/doc/usenglish/help/delay_types/html/web_ds_v4/ta_tbxcy.htm

for my installation of ISE8.2. Your location may vary.

HTH., Syms.

 

[RCIngham]

CONGRATULATIONS!

You have won today's "Least well specified question" prize.

;-)

 

[Hal Murray]

Anyway, this is not an academic exercise. Porting a very complex
Virtex4 design
to Stratix is not something that one can do in a few days, so I was
looking
for ballpark estimates about the equivalence between Xilinx and Altera
"gates".

Have you looked at the Stratix data sheet? Did you find anything
close to a CLB/FF pair? If so, assume they are 1:1.

Then count the special things you use: BRAMs, clock buffers, multipliers
and whatevber. Then see if Altera has something similar.

--
These are my opinions, not necessarily my employer's. I hate spam.