EDK : FSL macros defined by Xilinx are wrong

Zhane wrote:
You can not connect directly to the PADs but instead you should
connect to the signals on the fabric side of the IBUFs and OBUFs.
HTH., Syms.

???
Sorry I dont know what you mean by "the signals on the fabric side of
the IBUFs and OBUFs"

can explain to me?
Click to expand...
When you use the inserter, don't make connections to the greyed out signals.
The ones with 'Base Type' described as PORT. These signals only attach to
the fabric through IBUFs and OBUFs. So, you can't connect them to Chipscope.
Only connect to blacked signals. (You see what they've done there?)
HTH., Syms.
 
"Jim Granville" <no.spam@designtools.maps.co.nz> wrote in message
news:488f0139$1@clear.net.nz...
Yes, SPCO and SPDT are effectively interchangable
(change Over/Double Throw) - The venerable Microswitch has that,
as does the Digitast buttons. Digikey shows those for 28c+cap
Click to expand...
Hmm SPDT switches come in two varieties. Break before make and make before
break. There is a danger you'll get one where the switch will momentarily
connect all 3 terminals together for a short period of time. It's important
to check and specify you get the right one for this application.
 
"Jim Granville" <no.spam@designtools.maps.co.nz> wrote in message
news:488ff776@clear.net.nz...
Fred wrote:
"Jim Granville" <no.spam@designtools.maps.co.nz> wrote in message
news:488f0139$1@clear.net.nz...

Yes, SPCO and SPDT are effectively interchangable
(change Over/Double Throw) - The venerable Microswitch has that,
as does the Digitast buttons. Digikey shows those for 28c+cap


Hmm SPDT switches come in two varieties. Break before make and make
before break. There is a danger you'll get one where the switch will
momentarily connect all 3 terminals together for a short period of time.
It's important to check and specify you get the right one for this
application.

I have yet to see a Microswitch that is MBB. Got any references of
one that is ?
The mechanical design of uSW and closely related Digitast buttons rather
excludes that.
Click to expand...
I agree that many forms of switches are break before make. The thing is I
have come across make before break and they have ended up causing grief.
It's just something I would bear in mind.
 
"Matthias Alles" <REMOVEallesCAPITALS@NOeit.SPAMuni-kl.de> wrote in message
news:g6choh$qot$1@news.uni-kl.de...
Hi again!

stfd f30, 1760(r1) with r1 = 0x0111ed1a

The resulting address is not aligned to an 8-byte boundary which causes
the exception. It seems that the stack for the thread is not aligned to
an 8-byte boundary. Looks like a xilkernel bug.

OK, I was able to fix this issue by myself in the xilkernel. My guess
was right.
The stack for all threads is created in mem.c line 63 like this:

char thread_stack_mem[PTHREAD_STACK_MSIZE];

By replacing the line with

char thread_stack_mem[PTHREAD_STACK_MSIZE] __attribute__ ((aligned (8)));

the problems are gone. So the programmers of the xilkernel just never
thought of 64bit types that some applications might use.
Click to expand...
The issue is a bit more basic -- Xilkernel does not support the APU FPU; It
does not save/restore the floating point registers on context switches, does
not distinguish between single precision/double precision and so on.

Unless you plan to use floating point in just a single thread, you will end
up with a corrupted system.

Documentation is missing for this lack of support. We will get it added in.

Vasanth
 
if write = '1' then
irq <=0;
reload <= dbus;
elsif falling_edge(clock) then
if counter = 0 then
counter <= reload;
irq <= '1';
else
counter <= counter - 1;
irq <= '0'; -- AUTO EOI
end if;
end if;

I know I shouldn't do homework for people but what the hey. Use the write
signal as an asynchronous reset. Also, use numeric.std . It's lovely.

http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf

HTH, Syms.
 
"Gabor" <gabor@alacron.com> wrote in message
news:23a70911-0da5-4c72-8e52-dd8bbdb09035@34g2000hsf.googlegroups.com...
I often look through waveform views with many screens worth of
signals,
so I like to re-arrange the signals to have those of interest at the
top of
the view. With ModelSim PE 5.7, I could find the signals I wanted,
select them, then cut (Ctrl+X), go to the top of the window (Ctrl
+Home)
and paste (Ctrl+V) these signals at the top of the window.

Now with ModelSim 6.3, I find that this trick doesn't work with
multi-bit vectors anymore. I get errors like:

# Paste insertion failed: sim:/tst_brd_test/uut/app_af_addr: The "-
min" and "-max" options can only be used with analog formats.

I have no clue what this error message means, but my only work-
around is to painfully drag the vector to the top of the window,
waiting
for an annoyingly slow scroll when the signal needs to move more than
a screen's height. Is there a better way to do this?

Regards,
Gabor
Click to expand...
For what it is worth, I just tried it out in 6.4 under XP and it seems to
work OK. If you don't want to change to 6.4 try 6.3h,

Hans
www.ht-lab.com
 
aleksa wrote:
This isn't homework, I'm learning on my own, more or less from
scratch.
If I was a student, I would say so.
Click to expand...
Please forgive me. Sadly, not all posters here share your honesty of
disclosure.

Good luck with your project, Syms.
 
Hi there,

I already have the fixed point values for the integers and as they're just
5 coefficients, I have just taken them as constants. Do you think it is
alright? Well, then I am giving input(16-bit {1 sign bit and 15 fractional
bits}) from the switches and buttons on the Spartan-3 board. As there are
just 4 1-bit push buttons and an 8-bit switch (12-bits altogether, and then
I am keeping 4 bits constant). Then the output is also 16-bit which
includes 1 sign bit, 4 integer bits and 11 fractional bits. Now, I have
used the 7-segment display to show the output in such a way that the
leftmost digit is showing the hex value of 4 integer bits, and then a dot
to show decimal point and then the next 3 digits for fractional part but
as there are 11-bits in fractional part, so, I have padded a zero at the
end of fractional part just to make it a 4-bit value for the hex-decoder.
And then I am using the last dp (dot/decimal point on 7-seg display to
indicate the sign of the number).

So, I am only giving input from the board and getting the output and not
using any RAM/ROM or multiplier blocks, I have only used constants and the
operators ('+', '-', '*') and left it all to the VHDL to do all the
intermediate arithmetic and use the hardware components as required, will
it be fine?

Do you think it is a good design?

Now, I was wondering what will be the best option if I wanted to
demonstrate the filter operation more clearly. I mean these are just
numbers that I am showing on the 7-seg display. But if I want to give a
sinusoidal input and get a filtered waveform at the output.

1)I have got the code for vhdl sine generator.
2)Showing the ouput on the oscilloscope? it sounds a bit tedious.
3)Do you think interfacing a microphone and speaker would work for this
design (and for Spartan-3)?
4)Or giving the output back to the simulator and showing the waveform
would do?
5)or any other application/test case you would suggest for IIR filter
implementation on FPGA?
Thanks very much for your help.

Regards,

Kami
 
"kami" <kamran.wadood@yahoo.co.uk> wrote in message
news:JJudnS58eI-AdwzV4p2dnAA@giganews.com...
...
Do you think it is a good design?

A better question is, do _you_ think it's a good design?


Now, I was wondering what will be the best option if I wanted to
demonstrate the filter operation more clearly. I mean these are just
numbers that I am showing on the 7-seg display. But if I want to give
a
sinusoidal input and get a filtered waveform at the output.

It wouldn't take much to drive a VGA display.
Click to expand...
Do you mean using a logic analyzer? But my friend is struggling to develop
a logic analyzer in FPGA. So, how do you so it won't take much for VGA
display?
or do you mean using a cable (i've heard of a cable that can be connected
to FPGA and then the other end to the PC) is that what you meant?
Thanks for your help,
Cheers,
Kami
 
"fmostafa" <fatma.abouelella@ugent.be> wrote in message
news:7dd39237-2837-4722-b062-6a849321cfef@k37g2000hsf.googlegroups.com...
hi all;

I am using Edk to create IP peripheral which contains RD and WR
Fifos. My question is, if the required data to be written to the read
fifo is undefined it will not be stored in the fifo or what.

fatma
Click to expand...
If you write undefined data to a fifo .. that's what will be stored in the
fifo .. undefined data.

If you don't want this to be stored ... don't assert the fifo push signal.

Mike
 
"John_H" <newsgroup@johnhandwork.com> wrote in message
news:88fb24da-8f2b-4f3f-833a-059b79fc0eae@k30g2000hse.googlegroups.com...
fmostafa wrote:
hi all;

I am using Edk to create IP peripheral which contains RD and WR
Fifos. My question is, if the required data to be written to the read
fifo is undefined it will not be stored in the fifo or what.

fatma

Please define undefined data, electrically.
Click to expand...
??

Undefined data is not defined, by definition.

It is a simulation state, not an electrical state.

JTW
 
"kami" <kamran.wadood@yahoo.co.uk> wrote in message
news:wJOdnV4QFvPZ7w_V4p2dnAA@giganews.com...
"kami" <kamran.wadood@yahoo.co.uk> wrote in message
news:JJudnS58eI-AdwzV4p2dnAA@giganews.com...
Now, I was wondering what will be the best option if I wanted to
demonstrate the filter operation more clearly. I mean these are just
numbers that I am showing on the 7-seg display. But if I want to
give
a
sinusoidal input and get a filtered waveform at the output.

It wouldn't take much to drive a VGA display.

Do you mean using a logic analyzer? But my friend is struggling to
develop
a logic analyzer in FPGA. So, how do you so it won't take much for VGA
display?
or do you mean using a cable (i've heard of a cable that can be
connected
to FPGA and then the other end to the PC) is that what you meant?

A VGA display needs only a few signal lines to drive it, fairly easy for
the
FPGA. I was maybe wrong to suggest it. Setting up a memory controller for

the frame buffer and writing the line draw routines is too much of a
project
and distraction early on. Forget I mentioned it.

Directly displaying the filtered waveform won't show the filtering as
well a
spectrogram. Your ears are also pretty sensitive to spectral changes.
Audio
will be the simplest demonstration. A DAC can drive earphones directly.


Can you explain a little bit more about this application? where and how am
Click to expand...
I going to give input and how do I get the output? Is it just another (one
or more) VHDL file I need to write?
Thanks
 
"Svenn Are Bjerkem" <svenn.bjerkem@googlemail.com> wrote in message
news:7e7320a6-ee66-4285-9c61-20f16670f54a@d1g2000hsg.googlegroups.com...
Hi,
I converted some vhdl files from text to graphics and note that
connections to signals in records does not get a visual connection to
the pins where the single wires are supposed to be connected. They are
just open, and there are no input pins for the records entering the
block placed. I inspect the generated vhdl and symbol, and they are
added correctly to the symbol and to the output rtl.

Anybody know if this is a "feature" or is there an option that I need
to set somewhere to see the connections? I use version 2007.1a.

--
Svenn
Click to expand...
I am not sure I understand you 100%, records are supported and if you import
some VHDL and convert it to graphics all should be OK. However, you are
right that graphically you can not select an element from a record and
connect it to a blue/green block pin. So what happens is that you get a
yellow block with a "signal<=record.element;" type of assignment. This is a
real shame and proper record support is something I have been asking for it
since version 2004 :-(

Hans
www.ht-lab.com
 
Hi,



If you have the time, I invite you to contact me directly (privately) to
discuss your experience with the Spartan-3E Starter Kit. As you might
imagine, it is intended for "starters" and not intended to generate
frustration!



I know you are interested in schematic based design entry, so the following
resource may be of limited interest (but I'll include it anyway):



http://www.engr.sjsu.edu/crabill



I look forward to hearing from you,

Eric Crabill



=====



"laserbeak43" <laserbeak43@gmail.com> wrote in message
news:38faf0eb-3746-49f1-84f3-1720ba98d399@r66g2000hsg.googlegroups.com...

Schematic capture for FPGA design entry is moribund.
Consider learning vhdl or verilog instead.
If schematics are non-negotiable, consider quartus:
multimedia.ece.uic.edu/wahmad/quartus_ii_tutorial.pdf
Good luck.

-- Mike Treseler
Click to expand...
Hmm, so i've heard. Everyone says Xilinx stuff is bad for beginners
and i must admit,
I've been doing nothing but troubleshooting ever since i got this
board, what a headache.

Since the OP already bought the Xilinx stuff, he may want to
open ISE (or WebPack) and under Help --> Tutorials --
Tutorials on the Web, he can find what is available from
Xilinx. Look for "ECS" schematics. By the way I have
not looked at these myself. I too use HDL rather than
schematics since I "upgraded" from version 4.1 - the
last Foundation version with Aldec schematics. Also
go tohttp://forums.xilinx.com/and check out all of
the chatter on schematics. In my opinion, the ECS
schematics are not ready for prime time. The
associated documentation is not likely to be better.

Oh, and before you get ideas of using Foundation
4.1 schematics, it is no longer available from Xilinx
due to a termination of their agreement with Aldec.

Aldec has wonderful new software that supports
Xilinx parts and others, but it would cost a lot more
than a good Altera evaluation board and a copy of
Quartus.

Just my 2 cents,
Gabor
Click to expand...
I think i'm gonnna sell this board and go for an Altera board.
but i'll try that first.

thanks guys.
 
=A0 =A06,097,211 - "Configuration Memory Integrated Circuit"

After quickly scanning this - I'm struggling to see what the
"invention" is.

6,147,411 - "Overvoltage-Tolerant Interface For Integrated Circuits

5V tolerant I/O with a 3.3V supply. Hardly the first company to do
that. Maybe the actual circuit to implement it was novel.

=A0 =A06,314,550 - "Cascaded Programming With Multi-Purpose Pins"

LOL! They've invented multifunction I/O pins.

I have not reviewed any of these patents so I'm not sure what the
actual
patent claims are.

They all sound like the usual nonsense to me. Yet more evidence that
the patent system needs serious reform.

Jon
Click to expand...
Ther is a fairly well argued rant against patents (or at least the USA's
interpretation of patents) at
http://www.embeddedtechjournal.com/articles_2008/20080729_patent.htm

I'm not sure that the idea of patents is completely broken, but it
certainly needs major reform so that innovation is reasonably protected and
rewarded. A copiers' free-for-all would also be bad, IMHO.
 
rickman wrote:
One suggestion. When implementing counters, it is slightly more
efficient to implement them as loadable down counters.


This is because in most technologies there is a carry chain built in
that can detect when counter is 0. If you are counting up to (M-1)
the synthesizer has to use LUTs to detect the final state if M is not
a power of 2.

Rick
Click to expand...
Good point, but remember up counters are fine too! E.g. divide by 200...

if count = 255 then
count <= 56;
else
count <= count + 1;
end if;

Or something like that.

HTH, Syms.
 
what's the point here?
Click to expand...
The point is that the embedded programmer has to read the hardware manual
first and/or talk to the hardware designer. Asking generic questions here
won't help!


/Mikhail
 
"Matthias Alles" <REMOVEallesCAPITALS@NOeit.SPAMuni-kl.de> wrote in message
news:g6rmt5$ef7$1@news.uni-kl.de...
Thanks for the information. That's good to know! I didn't think about
that at all..

Are there any plans to include FPU support into xilkernel for a future
release?
Click to expand...
Yes we do plan to add the support. I don't have a hard date for it though :(
 
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