EDK : FSL macros defined by Xilinx are wrong

[Stephan van Beek]

"Zhane" <me75@hotmail.com> wrote in message
news:e92bb3c9-58a3-4941-938c-6e4587b99d8e@i18g2000prn.googlegroups.com...
On Jul 3, 4:54 pm, "Stephan van Beek" <stephan.vanb...@mathworks.nl>
wrote:

"Zhane" <m...@hotmail.com> wrote in message

news:2086f732-c988-42fa-b94d-e56af2454b72@p39g2000prm.googlegroups.com...



Im trying to make use of the fifo in my Spartan3E starter kit

i've added the component declaration and instantiation template as
instructed in the vho file. but im getting the following error when i
try to implement the design

ERROR:NgdBuild:604 - logical block 'FIFO' with type
'fifo_generator_v3_3' could
not be resolved. A pin name misspelling can cause this, a missing
edif or ngc
file, or the misspelling of a type name. Symbol
'fifo_generator_v3_3' is not
supported in target 'spartan3e'.

Ive also added "Library XilinxCoreLib;" at my top module, which refers
to the fifo component.

am I missing something?

Hi,

this error indicates that the design hierarchy is not complete
most likely there is also an ngc file generated which is the actual
content
of the core for ISE
is this file in the same folder as your ise project?
if not you could set the macro search path to include the folder in
searching for all required files

Regards,
Stephan

how to set a macro search path?

if you right click on implement design > properties > translate properties
the macro search path is one of the available options to set, you can also
set multiple paths seperated by ;

Regards,
Stephan

 

[MM]

"Zhane" <me75@hotmail.com> wrote in message
news:39230673-45bb-4f5e-ac0f-57cc904713b3@i36g2000prf.googlegroups.com...

im getting this error when I do my simulation with Modelsim
# ** Warning: Design size of 11167 statements or 0 non-Xilinx leaf
instances exceeds ModelSim XE-Starter recommended capacity.

Wich means that your ModelSim license doesn't allow for simulating design of
such size.

/Mikhail

 

[Stephan van Beek]

how to set a macro search path?

if you right click on implement design > properties > translate properties
the macro search path is one of the available options to set, you can also
set multiple paths seperated by ;

Regards,
Stephan

ooo
it searches every sub directories?



====

No I don't think so, but you can add multiple paths.

Stephan

 

[MM]

or rather... how can I simulate the FIFO?

If you can afford it upgrade your license. If you can't afford it try
partial simulations or see if you can find a less resrtictive free
simulator, or get an evaluation license, etc..


/Mikhail

 

[Icky Thwacket]

"Zorjak" <Zorjak@gmail.com> wrote in message
news:2a3e6b51-ccf4-4b1c-83cb-3cd1935a5120@m44g2000hsc.googlegroups.com...

Hi,

I have one question if anyone can give me some clues. I need to
realize SPI (Serial Pheriferal Interface for my project). Does anybody
knows is there any free version of this core that can be foud on the
net. TO be honest, I tought that I will find this easy on the net but
it turns out that it was not.. I need that my interface be fully
programed.

Please if someone can give me any clue where can I find this. If you
don't know, some good literature would also help if I must to do it by
myself from the beginning.

Thank you very much
Zoran

Christ! It takes about an hour tops to put together an SPI interface. If you
cannot even do that you should not even be playing with FPGA's!

Read the SPI interface spec for the peripheral(s) you want to interface and
go design.

Icky

 

[Nico Coesel]

Goli <togoli@gmail.com> wrote:

hi,

I am looking for connecting my proprietary 8 bit bus interface across
two Xilinx FPGAs across the back plane, (10 inch trace). I dont want
to use differential as that would take lot of pins, Is there any
single ended interface that I can use. I dont think LVTTL and LVCMOS
would work at such high speeds, whereas HSTL kind of interfaces can
not drive that long a trace.

So is there any other IO standard that I can use for this?

I'd go for external LVDS transceivers. They are very very cheap, made
for this purpose and will save you a lot of headaches.

--
Programmeren in Almere?
E-mail naar nico@nctdevpuntnl (punt=.)

 

[Symon]

"Goli" <togoli@gmail.com> wrote in message
news:3d9aeb69-2537-48cd-9bf9-e30c57dff9c3@l28g2000prd.googlegroups.com...

hi,

I am looking for connecting my proprietary 8 bit bus interface across
two Xilinx FPGAs across the back plane, (10 inch trace). I dont want
to use differential as that would take lot of pins, Is there any
single ended interface that I can use. I dont think LVTTL and LVCMOS
would work at such high speeds, whereas HSTL kind of interfaces can
not drive that long a trace.

So is there any other IO standard that I can use for this?

LVCMOS will be fine @ 70MHz. Your backplane should have a ground plane. Use

appropriate terminations at the FPGAs. Look into the DCI stuff. Simulate it
w/hyperlynx or similar.
http://www.xilinx.com/publications/xcellonline/xcell_50/xc_pdf/xc_spartan3-50.pdf
HTH., Syms.

 

[MM]

Which FPGA(s) are you using? Even if you don't have MGT's available you
could run your bus at twice or possibly even 4 times the speed while using
LVDS. This way you could even save some pins. You could even employ DDR for
more savings

/Mikhail

"Goli" <togoli@gmail.com> wrote in message
news:3d9aeb69-2537-48cd-9bf9-e30c57dff9c3@l28g2000prd.googlegroups.com...

hi,

I am looking for connecting my proprietary 8 bit bus interface across
two Xilinx FPGAs across the back plane, (10 inch trace). I dont want
to use differential as that would take lot of pins, Is there any
single ended interface that I can use. I dont think LVTTL and LVCMOS
would work at such high speeds, whereas HSTL kind of interfaces can
not drive that long a trace.

So is there any other IO standard that I can use for this?

 

[Symon]

Irfan,
What ChipScope stuff have you tried so far?
Syms.

 

[KJ]

"Zhane" <me75@hotmail.com> wrote in message
news:ae6c34d6-5951-4523-a905-ab06b5b21333@j22g2000hsf.googlegroups.com...

I'm using the following code. I've managed to make it work on my fpga
before. but when I try to simulate on my modelsim, it seems that it
never gets into the statemachine.

'Never gets into the statemachine'....is that supposed to mean something?
(Hint: It doesn't)

I've configured the settings for a 50Mhz clock...also set the config
for model sim to be 10ns 10ns for clock high and low.

How should I go about simulating this?

In a word, 'debug'.

Put some waveforms up to view, step through the code, look at the signals,
however it is that works best for you. It's your design and testbench, it's
up to you to figure out what the problem is. Debugging by newsgroup is
hardly worth the effort.

KJ

 

[Symon]

"Jim Granville" <no.spam@designtools.maps.co.nz> wrote in message
news:48728654@clear.net.nz...

It would be nice if Xilinx indicated what those 'mainstream' poackages
were, for low volume users like yourself.

Hi Jim,

They do, although you need to work it out from the pricelist!
Cheers, Syms.

 

[Symon]

"Nobby Here" <nobby@invalid.invalid> wrote in message
news:af2dnWFwxJm4-O_VnZ2dnUVZ8uadnZ2d@posted.plusnet...

Is there any information about the expected purchase lifetime for
the Virtex-4 series, specifically the FX12? We've been using it for
a couple of years now in small quantities but we want to expand
the product range we're using it in, because we're familiar with it
and have a bunch of software for the PPC processor. However we'd
like to make a value judgement based on how long we might be able to
expect to buy them.

We're looking at very small quantities, a few 10s a year max, so it's
not something that Xilinx or anyone else is going to specially extend
production for. Also, becasue it's small quantities, the R&D cost
figures heavily in the final product sale cost, so we don't want to
redesign very often.

How many years can we expect them to remain in production? Of course,
I realise we could buy a few years' worth if they do go out of
production, but we'd rather not go down that route if possible,
particularly if end of life is expected to be within the next 4 or 5
years in which case it might be better to move on to something newer
for future developments.

Nobby

Hi Nobby,

What's your alternative if they do stop making it? You gotta port it. So the
question is, spend the port money now, or later? Later's better, right?

No point worrying about stuff you can't influence!

Cheers, Syms.
p.s. Xilinx are pretty good at keeping stuff available. So, you'll probably
have got a new job long before the part goes obsolete!

 

[Symon]

"austin" <austin@xilinx.com> wrote in message
news:g50ons$qks1@cnn.xsj.xilinx.com...

m,

That bit about not using them anymore is pretty suspicious. Clicking on
other items you have for sale, it is odd that between nail guns and
kayaks you just happen to have some FPGAs.

Austin

Austin,
I guess you're new to eBay...
Cheers, Syms.

 

[Hal Murray]

Thanks Peter and all who replied. That's reassuring then so we'll continue
on the path we're taking. As you say, with 18 months in NFND we can do a
lot in that time (including go out of business ), and as someone
else pointed out it is really a matter of pushing the redevelopment
costs out into the future or facing them now. Future's definitely
better.

There is another option to add to your list.

If you still have products in production using a chip that goes
EOL, buy a lot of them, say enough for 10 more years. Maybe
round up a bit.

This obviously works better if you can accurately estimate
your production volumes and/or know how long you want to
sell those products.


--
These are my opinions, not necessarily my employer's. I hate spam.

 

[Symon]

"vignesh_karthi" <pvprabhuraj@gmail.com> wrote in message
news:ecf5b59d-ba57-4c5f-9b30-93f0ff38e2f6@59g2000hsb.googlegroups.com...

My name is vignesh.

I am also new guy to Xilinx .. i want to know the following things...
please help me...

1. how can i create the *.ucf file using xilinx Tool ? (if you have
provide me )

2. how can i avoid the multicycle path and false path ? (if you have
provide me )

3. Do you have any basic user manual for xilinx tool ? (if you have
provide me )


Advanced Thanks to you...

Hi Vignesh,

In a Windows environment, follow this procedure.

start -> All Programs -> Xilinx ISE -> Documentation -> Software manuals

Look at the contraints guide and the Development system reference.

I hope this has provided you Advanced Help.

Syms.


p.s. You might like to try this link to help you in future...
http://catb.org/~esr/faqs/smart-questions.html
and more particularly...
http://catb.org/~esr/faqs/smart-questions.html#rtfm

 

[Symon]

"Gabor" <gabor@alacron.com> wrote in message
news:e1dcc819-76e0-4f8b-8e0a-7ee345bacdbb@8g2000hse.googlegroups.com...

On Jul 8, 9:46 am, Nemesis <gnemesis2...@gmail.com> wrote:
I have two different boards (ICS-8550) the differ only for the
ruggedization level, the boards are almost the same and so should be
the FPGAs, maybe only the stepping level is different.

But on one board is working and on another one is not working.


With a sample size of just two boards, it's possible that your clock
source is not within the required jitter specs to achieve lock. What
is the source? Possibly an oscillator with a PLL to produce the
required frequency?

Or maybe cascaded DCMs?

 

[Icky Thwacket]

"vlsi_learner" <bajajk@gmail.com> wrote in message
news:e923ab5c-6a1d-4431-9630-8375a0da42b5@d77g2000hsb.googlegroups.com...

Hi,

I am using altera FPGA.

How can I put the output of my logic into the FPGA internal
memories(assuming I have unused memories available)?

Probably best to use a dual port RAM - something like a lpm_ram_dp will do
nicely. Using the megawizard decide on the width and depth required. Set up
a scanner (mux/counter combo) with each of your internal nodes that you want
to store located on the input of the mux. Wizz round (scan) the mux inputs
with your counter, at the same time using the counter output as the address
to your RAM. Output of mux is data input to RAM. Also generate an
appropriate clock/WR for the RAM. Bring the other side of the DPR address
and DATA to the FPGA I/O and weld up the WR line low (you only want to
READ). Now, assuming you internal scanned nodes have defined bit and address
positions, and you have an appropriate scan sample rate going, you can
access any node via the I/O address data lines.

Now why couldn't you think of that?


Icky

 

[Alvin Andries]

"Arnim" <clv.5.minral@spamgourmet.com> wrote in message
news:g5394o$2cj$1@svr7.m-online.net...

I have the code which successfully goes out and determines the number
of devices in the scan chain, but am having difficulty determining
how to detect the size of the instruction register for each device.
Can someone point me to some code?

Once you know the number of devices in the chain, you could retrieve
their IDCODEs and get the instruction register length for each device
from a look-up table or database.
The UrJTAG software (http://urjtag.org/) applies this mechanism to
identify the elements of the scan chain automatically.

Arnim

Hi,

Knowing the number of devices in a JTAG chain is simple: after a reset
(TRSTN = 0 or 5x TMS = 1) all devices with the IDCODE instruction must reset
to this command, the others must reset to the BYPASS instruction. The IDCODE
is always 32 bits with bit[0] = 1 and BYPASS register always captures a 0.

Finding the total length of the IR registers is do-able, but rather
difficult for individual registers: the IR register should capture 01 (or is
it 10) als it's 2 lsbs. Using the above technique to get the IDCODEs and
then going on woith the BSDL files is the best approach.

Regards,
Alvin.

 

[Brad Smallridge]

You could post your whole code, that would help.

Usually you only have clk in the sensitivity list
for synchronous operation unless you are doing
an asynchonous reset or something more exotic.

I think LittleAlex is right that something is
being optimised away. You could try
pin2<=sa(19) and sa(18);
to see if those warnings go away
on those two inputs.

Brad Smallridge
AiVision

 

[Symon]

"Frank Buss" <fb@frank-buss.de> wrote in message
news:lwpnm8xptojr$.5dpw9umuf1k2$.dlg@40tude.net...

He asked for putting the output into the
memory, only. Looks like he don't want to read it back

In which case he needs one of these:-

http://academics.vmi.edu/ee_js/Research/IC_Datasheets/digital_cmos/Write%20Only%20Memory.pdf