EDK : FSL macros defined by Xilinx are wrong

[c d saunter]

Symon (symon_brewer@hotmail.com) wrote:
: Jeff Cunningham wrote:
: >
: > Speaking of FPGA alternatives, this recently caught my eye. Don't know
: > much about it, but it sure looks cool:
: >
: > http://www.tilera.com/products/processors.php
: >
: > -Jeff

: Jeff,
: Where have I seen that before?
: Ah yes, http://en.wikipedia.org/wiki/Transputer
: Syms.

One of the things that strikes me about the Transputer is that it
was parallel hardware designed hand-in-hand with parallel software.

Not C/C++

It seems odd that there is so much convergence happening between a very
complex highly sequential CPUs and functionally simple, highly parallel
FPGA type devices, with lots of innovative hardware flying about.

All this convergence is happening in hardware, but for it to really work
don't the software environments need to do the same...

---

cds

 

[Andreas Ehliar]

On 2008-06-19, _TK_ <tom_kuhn@btopenworld.com> wrote:

My problem is, that presented with a read / write API functions I have
no idea as to what I *should* be writing to or reading from the FPGA
and to which registers (instruction / test). My goal (at least for
now) is to sample the state of every pin on the device.

This information is usually provided in BSDL (Boundary Scan Description
Language) files. Try to ask Quicklogic about this. (A quick search at
quicklogic.com didn't turn up anything when I tried it.)

/Andreas

 

[Symon]

Norman Bollmann wrote:

Now I am looking for alternative ways for a faster implementation and
came across the idea to implement the whole database searching as
electronic circuit in an FPGA. The database is of course far too big
to save it inside an FPGA, e.g. the BlockRAMs of a Spartan3.
Therefore external memory has to be used, slowing down the
throughput. Target is a database searching of 262144 elements with 16
bit each in maximum 220 ms.


Hi Norman,

If I understand correctly, you want to do one 16 bit compare per 800ns.
That's easy to do with an FPGA and some memory. You can go maybe 3 orders of
magnitude faster than that with (say) a 64 bit DDR2 external memory. The
FPGA companies and others sell development boards with memory on them.
HTH., Syms.

 

[RCIngham]

Is the concept of "Content addressable memory" known to you?

http://en.wikipedia.org/wiki/Content-addressable_memory

 

[Symon]

"techG" <giuliopulina@gmail.com> wrote in message
news:b947faa4-1d75-455a-9062-f6f8bc299625@a70g2000hsh.googlegroups.com...

Hi all,
I have a camera and a Virtex-5 FPGA, and i would like to store frames
in FPGA Block Ram.
In my design (that worked with Spartan-3E) i need to double camera
clock frequency, in order to get all data, because camera send data on
both clock edges.

Giulio

Hi Giulio,
Does the camera generate the clock or does the FPGA make a clock to drive
the camera?
Thanks, Syms.

 

[Symon]

"karthick" <karthick.kr@gmail.com> wrote in message
news:5d38b9f2-4fd7-44d2-9a87-5a9c6a6a2cd7@c19g2000prf.googlegroups.com...

Dear All

I working on a custom based board where the system is running with
xilinx 8.2i and Spartan 3E FPGA.

Now we are in process of migrating from version 8.2i to 9.2i.

Weare facing problem in debugging the system with 9.2i version. There
is a abnormal behaviour while debugging.

I would like to know the reason for this abnormal behaviour??

Experts please help me in solving this problem..

thanks a lot in advance.

regds
karthick

Dear kar thick,
There is no problem faced by Weare. Clearly, the abnormal behaviour was in
8.2i. The behaviour you're seeing now with 9.2i is normal. You should be
delighted.
HTH., Syms.

 

[Symon]

"RCIngham" <robert.ingham@gmail.com> wrote in message
news:zq6dnfbRSeEDOsLV4p2dnAA@giganews.com...

Is the concept of "Content addressable memory" known to you?

http://en.wikipedia.org/wiki/Content-addressable_memory

Hi Robert,

Do you have any examples of any 'proper' CAM devices that I can research? I
know that Altera's ESBs can be used as small CAMs, and that Xilinx have an
app. note design that can do single cycle reads and multi-cycle writes using
a BlockRAM. It would appear that Micron have dumped their 2Mb 'Harmony'
device long ago. I found various dead links to products, but nothign active.
Thanks, Syms.

 

[Symon]

"Mike Treseler" <mike_treseler@comcast.net> wrote in message
news:6cfb87F3f44j2U1@mid.individual.net...

Symon wrote:

Do you have any examples of any 'proper' CAM devices that I can research?
I
know that Altera's ESBs can be used as small CAMs, and that Xilinx have
an
app. note design that can do single cycle reads and multi-cycle writes
using
a BlockRAM. It would appear that Micron have dumped their 2Mb 'Harmony'
device long ago. I found various dead links to products, but nothign
active.

Useful CAM structures don't fit well in FPGAs
and the vendors have quit trying.
Some sort of hash table may be a better fit.
http://en.wikipedia.org/wiki/Hash_table

-- Mike Treseler
Hi Mike,

Right, but are there any custom CAM devices out there?
Thanks, Syms.

 

[Symon]

"Mike Treseler" <mike_treseler@comcast.net> wrote in message
news:6cfgdeF3g3m7sU1@mid.individual.net...

Symon wrote:

Right, but are there any custom CAM devices out there?
Thanks, Syms.

Most have dropped out.
Check idt and netlogic.


Looks like they're called "network search engines" these days. Thanks mate!

http://idt.com/?genID=75K52134
http://www.netlogicmicro.com/2-products/nse70k.htm

 

[Hal Murray]

I forgot to mention that I like to make use of Verilog's pre-processor, when
I can, and as Mark mentioned, a script/program that generates code with specific
parameters based on a template also works in certain situations.

You can also use cpp as a preprocessor.

It helps to be good with makefiles and/or may not fit your
style if you like the big green button on the GUI.

--
These are my opinions, not necessarily my employer's. I hate spam.

 

[Andreas Ehliar]

On 2008-06-25, Philip Herzog <phu@arcor.de> wrote:

Hi!

I'm designing a Spartan 3 FPGA with ISE 9.2 and just hit the point where
the FPGA couldn't be routed anymore since it was too full. Now I have to
optimize or reduce some modules to win some area, but I can only guess
which ones use a lot of area so optimizing them would win me significant space.

Is there a tool (or am I overlooking something in ISE) which tells me which
part of the design uses how much space? I'm aware that optimizing across
hierarchy may make this information inaccurate, but still I guess it would
show me the right way...

I have a small Perl script to do this at http://www.da.isy.liu.se/~ehliar/stuff/
You can see an example output of the script if you search for xdlanalyze on
the webpage.

/Andreas

 

[Mike Lewis]

"Thorsten Kiefer" <webmaster@nillakaes.de> wrote in message
news:4863c2c9$0$25950$6e1ede2f@read.cnntp.org...

Hi,
synthesizing the following code yields an error.

CODE :

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:22:54 06/23/2008
-- Design Name:
-- Module Name: main - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity main is
port(
clk,reset : in std_logic;
btn: std_logic_vector(2 downto 0);
rx : in std_logic;
tx : out std_logic;
led: out std_logic_vector(7 downto 0);
sseg : out std_logic_vector(7 downto 0);
an : out std_logic_vector(3 downto 0);

-- to/from chip
ad : out std_logic_vector(17 downto 0);
we_n, oe_n : out std_logic;
-- SRAM chip a
dio_a : inout std_logic_vector(15 downto 0);
ce_a_n,ub_a_n,lb_a_n : out std_logic;
-- SRAM chip b
dio_b : inout std_logic_vector(15 downto 0);
ce_b_n,ub_b_n,lb_b_n : out std_logic
);
end main;

architecture Behavioral of main is
signal tx_full, rx_empty: std_logic;
signal rx_data,tx_data : std_logic_vector(7 downto 0);
signal btn_tick: std_logic;
signal mem : std_logic;
signal mem_rw : std_logic;
signal mem_addr : std_logic_vector(17 downto 0);
signal mem_data_f2s : std_logic_vector(31 downto 0);
signal mem_data_s2f : std_logic_vector(31 downto 0);
signal mem_ready : std_logic;
signal h2a_hex : std_logic_vector(3 downto 0);
signal h2a_ascii : std_logic_vector(7 downto 0);
signal wr_uart,rd_uart : std_logic;

type state_t is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10);
type regs_t is record
state : state_t;
led : std_logic_vector(7 downto 0);
hex : unsigned(3 downto 0);
end record;
signal r_reg,r_next : regs_t;

begin
uart_unit : entity uart
port
map(clk=>clk,reset=>reset,rd_uart=>rd_uart,wr_uart=>wr_uart,

rx=>rx,w_data=>tx_data,tx_full=>tx_full,rx_empty=>rx_empty,
r_data=>rx_data,tx=>tx);
btn_db_unit : entity debounce
port
map(clk=>clk,reset=>reset,button=>btn(0),db_level=>open,db_tick=>btn_tick);
sram_unit : entity sram_ctrl
port
map(clk=>clk,reset=>reset,ad=>ad,we_n=>we_n,oe_n=>oe_n,dio_a=>dio_a,ce_a_n=>ce_a_n,

ub_a_n=>ub_a_n,lb_a_n=>lb_a_n,dio_b=>dio_b,ce_b_n=>ce_b_n,ub_b_n=>ub_b_n,lb_b_n=>lb_b_n,

mem=>mem,rw=>mem_rw,addr=>mem_addr,data_f2s=>mem_data_f2s,data_s2f=>mem_data_s2f,ready=>mem_ready);
hex2a : entity hex2ascii port map(hex=>h2a_hex,ascii=>h2a_ascii);

an <= "1110";
sseg <= '1' & (not tx_full) & "11" & (not rx_empty) & "111";

process(clk,reset)
begin
if reset = '1' then
r_reg.state <= s0;
r_reg.led <= "11111111";
r_reg.hex <= (others=>'0');
elsif rising_edge(clk) then
r_reg <= r_next;
end if;
end process;

process(r_reg)
begin
r_next <= r_reg;
mem_addr <= "000000000000000000";
mem_rw <= '0';
mem_data_f2s <= "00000000000000000000000000000000";
wr_uart <= '0';
tx_data <= "00000000";

case r_reg.state is
when s0 =
if btn_tick='1' then
r_next.state <= s1;
mem_addr <= "111111111111111111";
mem_rw <= '0';
mem_data_f2s <=
"01010101010101010101010101010101";
end if;
when s1 =
if mem_ready='1' then
r_next.state <= s2;
end if;
when s2 =
r_next.state <= s3;
mem_addr <= "111111111111111111";
mem_rw <= '1';
when s3 =
if mem_ready='1' then
r_next.state <= s4;
end if;
when s4 =
r_next.led <= mem_data_f2s(7 downto 0);
r_next.state <= s5;
when s5 =
wr_uart <= '1';
r_next.hex <= r_reg.hex + 1;
r_next.state <= s6;
when others =
r_next.state <= s0;
end case;
end process;

tx_data <= h2a_ascii;
h2a_hex <= std_logic_vector(r_reg.hex);
led <= r_reg.led;
end Behavioral;


ERROR:
=========================================================================
* Low Level Synthesis *
=========================================================================

ERROR:Xst:528 - Multi-source in Unit <main> on signal <h2a_ascii<7>>; this
signal is connected to multiple drivers.
Drivers are:
Output port doA<7> of instance <hex2a/Mrom_ascii> of inferred macro ROM
Signal <h2a_ascii<7>> in Unit <main> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <main> on signal <h2a_ascii<6>>; this
signal is connected to multiple drivers.
Drivers are:
Output port doA<6> of instance <hex2a/Mrom_ascii> of inferred macro ROM
Signal <h2a_ascii<6>> in Unit <main> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <main> on signal <h2a_ascii<5>>; this
signal is connected to multiple drivers.
Drivers are:
Output port doA<5> of instance <hex2a/Mrom_ascii> of inferred macro ROM
Signal <h2a_ascii<5>> in Unit <main> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <main> on signal <h2a_ascii<4>>; this
signal is connected to multiple drivers.
Drivers are:
Output port doA<4> of instance <hex2a/Mrom_ascii> of inferred macro ROM
Signal <h2a_ascii<4>> in Unit <main> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <main> on signal <h2a_ascii<3>>; this
signal is connected to multiple drivers.
Drivers are:
Output port doA<3> of instance <hex2a/Mrom_ascii> of inferred macro ROM
Signal <h2a_ascii<3>> in Unit <main> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <main> on signal <h2a_ascii<2>>; this
signal is connected to multiple drivers.
Drivers are:
Output port doA<2> of instance <hex2a/Mrom_ascii> of inferred macro ROM
Signal <h2a_ascii<2>> in Unit <main> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <main> on signal <h2a_ascii<1>>; this
signal is connected to multiple drivers.
Drivers are:
Output port doA<1> of instance <hex2a/Mrom_ascii> of inferred macro ROM
Signal <h2a_ascii<1>> in Unit <main> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <main> on signal <h2a_ascii<0>>; this
signal is connected to multiple drivers.
Drivers are:
Output port doA<0> of instance <hex2a/Mrom_ascii> of inferred macro ROM
Signal <h2a_ascii<0>> in Unit <main> is assigned to GND



Where do is assign h2s_ascii to ground ?

Best regards
Thorsten

h2s_ascii is neither an input nor is it assigned anything .. it is a
floating undefined net .. that is your problem.

Mike

 

[KJ]

"backhus" <nix@nirgends.xyz> wrote in message
news:g403su$soj$1@news.hs-bremen.de...

Hi Rob,
Besides the bus widths issue, here's what you can do for initialisation
without need for a function.

snip

_____________________

Thus the registers become initialized to the constant value on Reset.
And if Reset is tied to a constant inactive value, the initialisation
values should still be used by XST as power-on init values (not 100% sure)
, while the reset network is ripped away.

This is in no way equivalent to assigning an initial value. While it is
generally better from a design perspective to reset things with a reset
signal rather than counting on intial value assignments, what you've
described with tying reset to a 'constant value' will end up either not
initializing anything on reset since the code inside the "if Reset = '1'
then" will never be executed (assuming Reset is tied to a constant '0') or
the code inside the "elsif rising_edge(clock) then" will never be executed
(assuming that Reset is tied to a constant '1'). In either case, you won't
get what you want.

Kevin Jennings

 

[KJ]

"KJ" <kkjennings@sbcglobal.net> wrote in message
news:tZS8k.1343$np7.1219@flpi149.ffdc.sbc.com...

Slight correction to previous, I missed the word 'inactive' in your sentence

"And if Reset is tied to a constant inactive value..". This means then the
latter part of my post was not correct, but the first part still is.

In any case, the code inside the "if Reset = '1' then" portion will be
synthesized away, and no assignments having to do with 'init_vector' will
occur, ever...not a very good replacement for an initial value assignment.

Kevin Jennings

 

[Joseph H Allen]

In article <mfW9k.30790$ZE5.14811@nlpi061.nbdc.sbc.com>,
hlao <hlao@nowhere.net> wrote:

I created a simple Verilog-2001 test-module:

When I ran this module through Xilinx Webpack 10.1, it synthesized
as a "addsub" macro...

But I tried the same top.v module in Altera Quartus-II.

When I synthesize to (Cyclone-II 2C20), Quartus-II creates an adder unit,
plus a bunch of separate muxes in front of port 'inb.' I've found that the
LUT consumption is TWICE the amount (34 vs 17) as a straight adder-only.

Yes Altera LE-based FPGAs work like this. Pretty much the entire LUT is
used as a full adder, there is not enough left for an optional
ones-complement of the B input to generate selectable subtractor.

This is changed beginning with the Stratix-II ALM design.

But why do you care? How many selectable adder/subtractors are you going to
have in your design? Even if it was a lot, Cyclone-II FPGAs have plenty of
LUTs.

You would only really care if it made a timing difference. The only way to
know this is to run your entire design through each vendor's tools.

There's a good chance that Altera would win this due to a less obvious
feature of their 4-input LUTs: namely that the input to output delay depends
on which pins are used: some are slow and some are fast (unlike Xilinx which
are all even). The tool maps timing critical pins to the fast inputs.

If you want something more significant to compare between X and A, compare
Xilinx LUT-RAMs with Altera M4Ks available in Cyclone-II. The combinatorial
read port on the LUT-RAMs (and SRL16s) is sometimes very convenient.

--
/* jhallen@world.std.com AB1GO */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0%79-77?1:0<1659?79:0>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}

 

[Symon]

<phxagent@gmail.com> wrote in message
news:0232ce5e-f1e0-4c0e-b11b-0d850c622ce6@d19g2000prm.googlegroups.com...

I have the resources to write VHDL/Verilog, netlist it and do the
layout(incl. routing), but how do I program this fpga?

Very carefully!

Go and do some reading. My advice is to start with the website of the FPGA
vendor you've chosen. Alternatively, as you seem to work for Intel, get them
to send you on an expensive course.

HTH, Syms.

p.s. http://catb.org/~esr/faqs/smart-questions.html

 

[Hal Murray]

I have the resources to write VHDL/Verilog, netlist it and do the
layout(incl. routing), but how do I program this fpga? I guess this is
something I am not too clear about. Thanks folks

Look in the data sheet. There will be a section on that area, maybe
called Configuration.

The compiler will give you a pile of bits. Typically, you feed them
serially to the FPGA with clock and data pins. You can bit bang it from
a small CPU. In a different mode, the FPGA can probably wiggle the
clock to load itself from a serial ROM. (Then you have to program the ROM.)

You can usually load them via JTAG.

The vendor probably provides a tool to do it.

It's probably simplest to get one of the low cost starter kits
and follow the directions for one of their demos. Or just
read their documention to see how it's done.

--
These are my opinions, not necessarily my employer's. I hate spam.

 

[Ben Jackson]

On 2008-07-02, phxagent@gmail.com <phxagent@gmail.com> wrote:

So going back to my original question, if I did design an FPGA with
LUTs and SRAM, how can I program this FPGA to do a particular
function? Do I write the software? If so, is that an easy thing to do?

For proof-of-concept you should be able to generate a bitstream that hooks
a few gates to a flop from inputs to outputs. Since you designed the FPGA,
you'd know how to do that.

If you want to generate that from a high-level description there will be
significant software involved. You may be able to take a frontend like
Icarus Verilog and write a new backend for your project, but it will take
considerable software expertise.

--
Ben Jackson AD7GD
<ben@ben.com>
http://www.ben.com/

 

[HT-Lab]

<jsreenivas.naidu@gmail.com> wrote in message
news:5dbbb591-7892-4905-9e69-74c6924b5b5e@34g2000hsf.googlegroups.com...

Hi,

I am presently writing Testcases and Test benches for my Communication
control modules which are used in Boeing spoilers.

I need the code for checking (validate and verify) a Message format of
my RCOM (remote electronic unit Communication). The message format is


StartBit> <Header Word><1-29 data word><checker word(odd
vertical parity)

Here each word is 32-bit in data word
Header word is 5-bit

It would be a great helpful if any one gives clear steps for verify
this format

If this is not a student project then I would suggest you look into
assertions (used with a formal tool and not a simulator). This is the only
way to test something exhaustively. PSL/SVA are not complicated languages
but I would still recommend going onto a course even if it is only 1 day.

In the meantime I will join Mike on Airbus

Hans
www.ht-lab.com

Thanks,
Sreeniv.

 

[Stephan van Beek]

"Zhane" <me75@hotmail.com> wrote in message
news:2086f732-c988-42fa-b94d-e56af2454b72@p39g2000prm.googlegroups.com...

Im trying to make use of the fifo in my Spartan3E starter kit


i've added the component declaration and instantiation template as
instructed in the vho file. but im getting the following error when i
try to implement the design

ERROR:NgdBuild:604 - logical block 'FIFO' with type
'fifo_generator_v3_3' could
not be resolved. A pin name misspelling can cause this, a missing
edif or ngc
file, or the misspelling of a type name. Symbol
'fifo_generator_v3_3' is not
supported in target 'spartan3e'.

Ive also added "Library XilinxCoreLib;" at my top module, which refers
to the fifo component.

am I missing something?

Hi,

this error indicates that the design hierarchy is not complete
most likely there is also an ngc file generated which is the actual content
of the core for ISE
is this file in the same folder as your ise project?
if not you could set the macro search path to include the folder in
searching for all required files

Regards,
Stephan