EDK : FSL macros defined by Xilinx are wrong

"Kolja Sulimma" <ksulimma@googlemail.com> wrote in message
news:8e8331f2-d305-40db-8b97-fd0c2c8ba02d@x35g2000hsb.googlegroups.com...
On 18 Jun., 16:29, "HT-Lab" <han...@ht-lab.com> wrote:

Doh!

set StdArithNoWarnings 1
set NumericStdNoWarnings 1

LOL.
How about:
set NumericStdNoWarning 'X'
If you give that command than Modelsim will automatically un-install, delete
your license file and block any emails to support@..... Of course this only
works in version 6.3, 4.7 to 6.2 simply deletes your partition table.
Version 6.4 (expected soon) will also send an email to your boss to get you
fired,

Hans
www.ht-lab.com

 
"austin" <austin@xilinx.com> wrote in message
news:g3b5pt$sra1@cnn.xsj.xilinx.com...
http://www.xilinx.com/ise/logic_design_prod/webpack.htm

RTWP*,

Austin

* try 'reading the web pages'
RTFM would have been appropriate, here, but I understand that your position
mandates some self control.

8}

Bob
--
== NOTE: I automatically delete all Google Group posts due to uncontrolled
SPAM ==
 
"austin" <austin@xilinx.com> wrote in message
news:g3b5pt$sra1@cnn.xsj.xilinx.com...
http://www.xilinx.com/ise/logic_design_prod/webpack.htm

RTWP*,
Some suggest support for SXT; some say there is no such support.
Which is correct?
 
"austin" <austin@xilinx.com> wrote in message
news:g3bhpv$ss01@cnn.xsj.xilinx.com...
Pete,

Do you have a specific part number?
I was going to develop using the ML506, so that would be
the XC5VSX50T FFG1136. Although the actual product
might use the FF665C.

http://www.xilinx.com/ise/logic_design_prod/webpack.htm
mentions support for SXT, but
http://www.xilinx.com/publications/prod_mktg/pn0010867.pdf
doesn't.

I will look into it for you.
Thanks,

Pete
 
"austin" <austin@xilinx.com> wrote in message
news:g3bhpv$ss01@cnn.xsj.xilinx.com...
Pete,

Do you have a specific part number?
I was going to develop using the ML506, so that would be
the XC5VSX50T FFG1136. Although the actual product
might use the FF665C.

http://www.xilinx.com/ise/logic_design_prod/webpack.htm
mentions support for SXT, but
http://www.xilinx.com/publications/prod_mktg/pn0010867.pdf
doesn't.

I will look into it for you.
Thanks,

Pete
 
Is it important to not use an initial condition controlled by a global
reset? In FPGAs this is typically free, or almost free to use it
properly. In ASICs I guess it is a different matter.
Metastability.

--
These are my opinions, not necessarily my employer's. I hate spam.
 
In article <a068485f-0e9d-4a93-beb6-cd825ada14e5@j22g2000hsf.googlegroups.com>,
rickman <gnuarm@gmail.com> writes:

Anyone know where this configuration is stored? How do I turn it off
permanently?
Permanently? :)

You are a hardware geek. Right?

The classical solution is wire cutters at the speaker terminals.

--
These are my opinions, not necessarily my employer's. I hate spam.
 
In article <a068485f-0e9d-4a93-beb6-cd825ada14e5@j22g2000hsf.googlegroups.com>,
rickman <gnuarm@gmail.com> writes:

Anyone know where this configuration is stored? How do I turn it off
permanently?
Permanently? :)

You are a hardware geek. Right?

The classical solution is wire cutters at the speaker terminals.

--
These are my opinions, not necessarily my employer's. I hate spam.
 
Jeff Cunningham wrote:
Speaking of FPGA alternatives, this recently caught my eye. Don't know
much about it, but it sure looks cool:

http://www.tilera.com/products/processors.php

-Jeff
Jeff,
Where have I seen that before?
Ah yes, http://en.wikipedia.org/wiki/Transputer
Syms.
 
This leads to a tradeoff between how many bits you use in the
hardware vs. how closely the real hardware
filter matches your desired response.

My input bits width is 16
coefficient bit width is 16
output width is 40
Use the fixed_pkg VHDL package....it has all you need, to whatever arbitrary
precision you may require.

KJ
 
"rickman" <gnuarm@gmail.com> wrote in message
news:ea4b9ffd-5b67-45d5-afc3-a47bfcb07fbe@x35g2000hsb.googlegroups.com...
On Jun 19, 1:20 am, hal-use...@ip-64-139-1-69.sjc.megapath.net (Hal
Murray) wrote:
In article
a068485f-0e9d-4a93-beb6-cd825ada1...@j22g2000hsf.googlegroups.com>,

rickman <gnu...@gmail.com> writes:
Anyone know where this configuration is stored? How do I turn it off
permanently?

Permanently? :)

You are a hardware geek. Right?

Well, I am a *geek*, I don't know that I would constrain that to
hardware...


The classical solution is wire cutters at the speaker terminals.

Yes, that is indeed permanent... but not very selective. There are a
few sounds that come from the PC that I don't object to and even a few
that I like. I would hate to lose those.

I was thinking more on the lines of a way to make the option change in
Simplify more permanent.

The ironic part is I think that I turned it on in the first place. I
thought it might be a good idea. I just didn't know how annoying this
particular beep could be!


Rick
Hello Rick,

Does the fact that you are now down to worrying about the beeps mean that
you are a bit happier with the Lattice software now?
I ask because I've been using it a while (2 years) and find it pretty good
(compared with X which i used before).
I never had you issues with Aldec v ModelSim because I have had fully paid
up separated Aldec HDL for ages.

Michael Kellett
 
MikeWhy wrote:
"Dave" <dave@comteck.com> wrote in message
news:f008$485ae84d$40b83d5e$25934@COMTECK.COM...
Jeff Cunningham wrote:

Speaking of FPGA alternatives, this recently caught my eye. Don't
know much about it, but it sure looks cool:

http://www.tilera.com/products/processors.php

Availability? Price?

Nvidia. Google.

Yes. Cheap.
MikeWhat?
 
MikeWhy wrote:
"Symon" <symon_brewer@hotmail.com> wrote in message
news:g3esnp$l2b$1@aioe.org...
MikeWhy wrote:
"Dave" <dave@comteck.com> wrote in message
news:f008$485ae84d$40b83d5e$25934@COMTECK.COM...
Jeff Cunningham wrote:

Speaking of FPGA alternatives, this recently caught my eye. Don't
know much about it, but it sure looks cool:

http://www.tilera.com/products/processors.php

Availability? Price?

Nvidia. Google.

Yes. Cheap.

MikeWhat?

Second cousin.

(Full initials. Also a pronunciation aid. You get my age and you'll
find the dimunitive inappropriate also.)
I thought your second cousin might explain what Nvidia had to do with
Tilera. I see another branch of the thread has cleared that up! :)
Cheers, Syms.
 
Steve wrote:
Hi,

After reading over the documentation for DDR2 and the SSTL signalling
standard, I have a question about the role of termination in DDR2.

It appears to me that in addition to the usual termination function,
the resistors provide some sort of biasing function around the Vref
(1.8v/2) point. Is it the case that the IO on the DDR2 modules can
"swing" around that midpoint without the presence of termination
resistors, or are these necessary for correct operation (even using
On- Die Termination). What I would like to know is whether, in
addition to the unidirectional signals (Address, etc...) that do not
have ODT, it is necessary to terminate the Bidirectional signals
(even with ODT)?

Thanks for your assistance,

Stephen
Hi Stephen,

Have a look at Sheet 13 of this:-

http://www.xilinx.com/support/documentation/boards_and_kits/ml50x_schematics.pdf

There are no terminations on the ODT signals to the DDR2 SODIMM, because the
ODT takes care of it.

HTH., Syms.
 
<andy730215@gmail.com> wrote in message
news:133f00df-2331-4cb0-b99d-75d988044592@h1g2000prh.googlegroups.com...
hi all:
I have a question about stratix II .An oscillator must drive a
constant clock frequency to an FPGA pin. The maximum frequency limit
depends on the speed grade of the FPGA. Frequencies of 50 MHz or less
should work for most boards.If my oscillator is less than 50 MHz ,how
to work about this system ?
If about PLL ,I want to know how dose PLL work.
1. Does PLL function automatically or need manual configure to initial
PLL in the system?
2. Dose PLL reference anything or any paremeter to lock the frequency?
What is the paremeter?
Thanks in advance.


Altera technical answer:-

http://www.altera.com/literature/hb/stx2/stratix2_handbook.pdf

READ - then - DIGEST

I suppose you want your arse wiping as well?
 
In article <LOd3k.9642$Ri.1039@flpi146.ffdc.sbc.com>,
Vladimir Vassilevsky <antispam_bogus@hotmail.com> wrote:
rickman wrote:

I couldn't figure out how to do a lot of things and I ended up
installing Win2000 over it.

So what exactly is better about Linux?

I second your opinion regarding Linux. It is a toy of students and
enthusiasts who are enjoying the process of configuring the computer
instead of getting the actual job done hard and fast.
The OP has not so much on opinion about Linux as wel as bad
experiences, and is willing to learn.

The only hindrance to getting my job done on Linux is
when I meet deliberately created incompatibilities and
deviations from standards originating from you know who.

BTW, why do you prefer Win2k rather then XP?


Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com
Haven't we met? (I'm the guy of the ESO optical delay line
in Paranal Chile, meeting the requirements of 14 nanometer
deviation RMS.)

--
--
Albert van der Horst, UTRECHT,THE NETHERLANDS
Economic growth -- like all pyramid schemes -- ultimately falters.
albert@spe&ar&c.xs4all.nl &=n http://home.hccnet.nl/a.w.m.van.der.horst
 
In article <e4bae6ce-2596-4010-83a2-1e8790d98478@b1g2000hsg.googlegroups.com>,
rickman <gnuarm@gmail.com> wrote:
On Jun 7, 12:13 am, Randy Yates <ya...@ieee.org> wrote:
rickman <gnu...@gmail.com> writes:
[...]
But if I want a laptop, I won't have much choice but to run Win XP
(for the next few weeks) or Vista. I only wish I had a choice.

You do. I have successfully installed Fedora 8 on an HP Pavillion
DV9620US.

However one thing to be careful of in running linux on laptops is
Broadcom's stubborn refusal to open up their wireless card
specifications so that open source drivers can be developed. Translated:
don't buy a laptop with a Broadcom wireless card (or chipset) if you
want to run linux on it. Atheros I've heard is very good and supported
by madwifi.org.

But, even though Broadcom is stubborn, I have still been successful at
getting the card to work on my home network. Unfortunately the reverse
engineered drivers (b43-fwcutter...) do not seem to support the Master
modes used in public hotspots.

I knew someone would mention Linux. Linux is still an alien platform
to me and there is any amount of software that is not supported under
it... or I should say that there is any amount of software that is
only supported on specific versions of Linux. If I run Fedora 8,
maybe vendor X gives me support and vendor Y doesn't. I run Redhat
and vendor X gives me support and vendor Z doesn't... etc, etc, etc.
Officially Dutch tax forms runs only under certain brands of linux,
not my brand. Guess what? The windows software is reasonably cross-
platform (withing windows that is).
Bottom line, the *windows* version of the tax forms installed and run
under wine on my Ubuntu 64 bit 7.03. (12 Megabyte to fill in 12 zero's
in a a form, but anyway). Including sending the completed form over
a safe channel.

The reason that I still run windows at all is because for me, it is
the only option. Currently Win2000 is the best that runs the minimum
required set of software. If I want a laptop, my only choice
currently is to buy a machine running XP which I can do for the next
few weeks. After that there will be no choice on a new machine except
for Vista. With a number of vendors not supporting that still, I will
not have the option of buying a new laptop with an installed OS that
runs the software I need.
My guess:
Windows package intended for XP run better on Ubuntu/wine than
one Windows Vista.
At least you can check it out at no cost.


--
--
Albert van der Horst, UTRECHT,THE NETHERLANDS
Economic growth -- like all pyramid schemes -- ultimately falters.
albert@spe&ar&c.xs4all.nl &=n http://home.hccnet.nl/a.w.m.van.der.horst
 
techG wrote:
Hi all,
I have a camera and a Virtex-5 FPGA, and i would like to store frames
in FPGA Block Ram.
In my design (that worked with Spartan-3E) i need to double camera
clock frequency, in order to get all data, because camera send data on
both clock edges.
The problem is the following: I can't use DCM, because camera clock
frequency is about 163 ns (~6 Mhz), and when I'm trying to generate
DCM (selecting Maximum Range Mode) , Xilinx Clock Wizard says that
"DLL Low Frequency Mode Range is: 19-32 Mhz, and DFS Low Frequency
Mode Range is 1-40 Mhz".
How can I avoid this problem? Do you think that I could use component
DCM of Unisim Library? Moreover, isn't there a VHDL 2X Clock
Multiplier that works fine?

Giulio
Hi Giulio,
So, your input frequency is 6MHz. The wizard tells you that "DFS Low
Frequency Mode Range is 1-40 Mhz". Notice how 6 is between 1 and 40. Perhaps
you should use your DCM in DFS Low Frequency Mode.
HTH., Syms.
p.s It's Hz not hz.
 
Hauke D wrote:
On Jun 22, 10:48 pm, "Symon" <symon_bre...@hotmail.com> wrote:
Hi Giulio,
So, your input frequency is 6MHz. The wizard tells you that "DFS Low
Frequency Mode Range is 1-40 Mhz". Notice how 6 is between 1 and 40.
Perhaps you should use your DCM in DFS Low Frequency Mode.
HTH., Syms.
p.s It's Hz not hz.

I believe the problem is that the clock doubler is one of the DLL (not
DFS) outputs, where the minimum input frequency, even in low frequency
mode, is 19 MHz.

Regards,
-- Hauke D
I see your point. I suggest multiplying by 4 and then dividing by two using
clock enables in the fabric.
Cheers, Syms.
 
Peter Alfke wrote:
On Jun 22, 5:05 pm, techG <giuliopul...@gmail.com> wrote:
I think the DDR method, or "my" frequency doubler are better
solutions.
Peter Alfke
Hi Peter,
The DDR method makes the logic more complicated. You have to deal with two
samples every clock cycle.
As for "your" frequency doubler, in the right hands it can be a useful tool.
However, with a simple synchronous solution available using a DCM, I
wouldn't recommend this path, especially for beginners.
YMMV, Syms.
 

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