EDK : FSL macros defined by Xilinx are wrong

<cpld.fpga.asic@gmail.com> wrote in message
news:80fc5390-d10b-43a9-89c7-0c2770a996b5@k13g2000hse.googlegroups.com...
Automotive Temperature +100 deg C+ FPGA's -- who's parts are available
from Distributor stock?

Am really interested in -40 to +125 deg C solutions that are
Automotive grade or Similar --
Click to expand...
A quick trawl reveals Digikey have all these Altera parts in stock - I4
suffix - which are guaranteed -55C +125C parts

EP2S60F1020I4
EP2S60F1020I4N
EP2S60F484I4
EP2S60F672I4
EP2S90F1020I4
EP2S90F1508I4

probably a load more but can't be arsed to look.

Icky
 
MikeWhy wrote:
"Symon" <symon_brewer@hotmail.com> wrote in message
news:g2r74u$bbm$1@aioe.org...
Spelling 'what' as 'wat' apparently "makes you look like a
semi-literate boob" to save one entire keystroke, especially as you
piss away the saving by using three question marks when one will do
just fine.

Ironically, it is precisely that which keeps me from writing him off
completely. There's an outside chance he's some jr. high school kid
feeling his way into the deep end. But, as you say, I'm still waiting
for the right questions.

Hi Mike,
Click to expand...

OK, that's cool, I see the point you are making.

OTOH, (you knew this was coming!) I see you are relatively new here, and I'd
be delighted to be told of someone who started off on this newsgroup as
'slightly irritating' and progressed as far as being 'not quite as
irritating as you used to be'. In my sad middle aged cynicism, even the
usenet nutters aren't what they used to be!

Cheers, Syms.
 
On May 19, 11:24 pm, Peter Alfke <al...@sbcglobal.net> wrote:


My situation is that ....the "30MHz" doesn't mean it is 30MHz, it mean
that the min time different between two signal will be =( 1/30Mhz). In
income signal don't have a clock domain, it just "Happen".
Click to expand...
Remember the Nyquist sampling criterion. If the minimum "pulse width" is
33ns (= 1/30MHz), that is roughly equivalent to a 15MHz maximum signal
frequency, so 40MHz sampling is OK.
 
Jim Granville <no.spam@designtools.maps.co.nz> wrote:
aleksa wrote:
I'm currently using GALs (16V8-18V8-22V10),
but my current board requires 4 GALs and
I would like to replace them with one CPLD
which would also replace 4 other general ICs.

I've never had the guts to try CPLD because I thought
they were complicated to learn, hard to solder and
most of all, impossible to programm without some $$$.

What do you program the GALs with now ? - many pgmrs also
pgm CPLDs (so you just need an adaptor)

Or, you can use the JTAG ISP

Now I think different, but am unsure...

I've choosen xilinx's XC95-36-72-108 to work with.

There are also Atmel ATF150xASL series, in PLCC, but lower
power than XC95xx.

Note that PLCC is now somewhat trailing-edge, and newest
families are TQFP only.
Click to expand...
Note also that XC95xx has smaller logic operation capabilities against
XC95xxXL or XC95xxXV and has higher prices.
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
 
Pat,
I am learning Verilog as well, my guess is that you may not handle correcly
NLP/FLP stuff, that's the reason the interface seems down.

Take a look here:

http://www.fpga4fun.com/10BASE-T0.html

"Keeping the link alive
Even if no packets are sent on a 10BASE-T cable, a pulse has to be sent
periodically (called the "Normal Link Pulse" or "NLP"). It is used to keep
the connection "alive". A pulse needs to be sent every 16ms or so.

The NLP can also be replaced by a "Fast Link Pulse" (FLP) burst, during a
process called "auto-negotiation". The FLP carries information about the
capabilities of the sender, so that the hardware at both end of a cable can
negotiate the link parameters, like the speed and the half/full duplex
status."

Giuseppe Marullo

giuseppe.marullo.nospam@iname.com
 
Pat,
I am learning Verilog as well, my guess is that you may not handle correcly
NLP/FLP stuff, that's the reason the interface seems down.

Take a look here:

http://www.fpga4fun.com/10BASE-T0.html

"Keeping the link alive
Even if no packets are sent on a 10BASE-T cable, a pulse has to be sent
periodically (called the "Normal Link Pulse" or "NLP"). It is used to keep
the connection "alive". A pulse needs to be sent every 16ms or so.

The NLP can also be replaced by a "Fast Link Pulse" (FLP) burst, during a
process called "auto-negotiation". The FLP carries information about the
capabilities of the sender, so that the hardware at both end of a cable can
negotiate the link parameters, like the speed and the half/full duplex
status."

Giuseppe Marullo

giuseppe.marullo.nospam@iname.com
 
"faza" <fazulu.vlsi@gmail.com> wrote in message
news:53fad5d8-9989-4089-82be-cf57588c9b34@u36g2000prf.googlegroups.com...
Hai,

I am facing problem while synthesis of Fixed point data type.I cannot
change the synthesis tool.Is there any method which can convert fixed
point to integer before hand and perform computation and convert back
to fixed point without affecting the precision.?

In my FIR filter design i will sample the input and perform
computation,produce result with control signal and then i will sample
the next data..ultimately i will waiting for the o/p control signal
before sampling the data..now my question is how this logic will be
implemented as hardware..do i need to store my input samples in ROM or
i should depend on the software to do this?

pls clarify.

regards,
faz



Dude .. give us some background ..

Are you a student? What year? Is this a project or an assignment?

Mike
 
"faza" <fazulu.vlsi@gmail.com> wrote in message
news:53fad5d8-9989-4089-82be-cf57588c9b34@u36g2000prf.googlegroups.com...
Hai,

I am facing problem while synthesis of Fixed point data type.I cannot
change the synthesis tool.Is there any method which can convert fixed
point to integer before hand and perform computation and convert back
to fixed point without affecting the precision.?

In my FIR filter design i will sample the input and perform
computation,produce result with control signal and then i will sample
the next data..ultimately i will waiting for the o/p control signal
before sampling the data..now my question is how this logic will be
implemented as hardware..do i need to store my input samples in ROM or
i should depend on the software to do this?

pls clarify.

regards,
faz



Dude .. give us some background ..

Are you a student? What year? Is this a project or an assignment?

Mike
 
Bytheway
How good is that book, is it a good way to learn VHDL for programmable logic
in general ?

Thanks
EC


"ghelbig" <ghelbig@lycos.com> ???
??????:493281cd-f7a2-4139-a6d2-981b086dfb43@s21g2000prm.googlegroups.com...
On Jun 16, 10:49 am, Mike Treseler <mike_trese...@comcast.net> wrote:
RealInfo wrote:
It comes with the WARP cpld design software for cyperess cplds .

Future Electronics CY3120R62CD

Mike:

The Future Electronics web site reports that part # as non-existant.
There was a 6.3 release (CY3120R63), but that search turns up empty
also.

To the OP:

Cypress no longer makes CPLDs. Unless you are supporting an old
design (like the CPLD on the FX2 Eval card :) the Warp package is only
useful for SPLDs.

Warp runs "just fine" on Windows 2000, it should work on XP as well.
It has a good uninstall, so just go ahead and try it.

G.
Click to expand...
 
If some people could help me in this, I would be very grateful :)
Click to expand...

Have a look at the FTDI vinculum, it takes most of the work out of
accessing USB sticks.


Nial
 
"Dave" <dhschetz@gmail.com> wrote in message
news:33883490-2aa7-440e-94ae-9316659ad854@t54g2000hsg.googlegroups.com...
http://biz.yahoo.com/ap/080617/cadence_design_mentor_graphics.html
Click to expand...
Worrying.....:-(

Hans
www.ht-lab.com
 
In article <33883490-2aa7-440e-94ae-9316659ad854@t54g2000hsg.googlegroups.com>,
Dave <dhschetz@gmail.com> wrote:
http://biz.yahoo.com/ap/080617/cadence_design_mentor_graphics.html
Click to expand...
EDA monopoly! But in the long run I think the real competition is going to
be freeware.

--
/* jhallen@world.std.com AB1GO */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
 
RealInfo <therightinfo@yahoo.com> wrote:

Hi all

What are the limitations of the free Xilinx Webpack ?

Does any one know ?

Thanks
EC
Click to expand...
Did you search for that on teh Xilinx website?

--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
 
http://biz.yahoo.com/ap/080617/cadence_design_mentor_graphics.html
Click to expand...
John Cooley has posted a copy of Fister's letter to Rhines:
http://www.deepchip.com/wiretap/080617.html

I wonder whether this will wake Synopsys up?
 
http://biz.yahoo.com/ap/080617/cadence_design_mentor_graphics.html
Click to expand...
John Cooley has posted a copy of Fister's letter to Rhines:
http://www.deepchip.com/wiretap/080617.html

I wonder whether this will wake Synopsys up?
 
The last FIR I implemented, I scaled the data and coefficients so that they
were all in range:
-1 <= number < +1
Note lack of equality in upper bound, therefore need trap for -1 * -1
case.

It worked well enough.



P.S. If you don't like hard work, go into marketing...
 
The last FIR I implemented, I scaled the data and coefficients so that they
were all in range:
-1 <= number < +1
Note lack of equality in upper bound, therefore need trap for -1 * -1
case.

It worked well enough.



P.S. If you don't like hard work, go into marketing...
 
"Brian Drummond" <brian_drummond@btconnect.com> wrote in message
news:bt4i541q56gf2ukbbgbtvahq6nrlt0jo31@4ax.com...
On Wed, 18 Jun 2008 04:57:04 -0700 (PDT), Kolja Sulimma
...
There are options in some libraries (numeric_std for one) in Modelsim to
suppress these warnings; but this carries the risk of suppressing real
information. So I don't think that's a good idea either.

I just ignore them... (actually I pay a LITTLE attention to reducing
their number, but it's not important) ... but wouldn't it be nice to
tell the simulator to suppress these errors for the first XXX ns, then
report them.

I expect a simple TCL script would do it...

suppress Numeric_Std invalid value warnings;
run 250 ns;
enable Numeric_Std invalid value warnings;
run;
Click to expand...
Close,

set StdArithNoWarnings 1
set NumericStdNoWarnings 0
run 0 ns;
set StdArithNoWarnings 0
set NumericStdNoWarnings 0
run ....

or if you want to suppress the warnings until reset is negated you can use
something like this:

when -label enable_StdWarn {reset_s == '1'} {echo "Enable StdArithWarnings"
; set StdArithNoWarnings 0 ;}

Hans
www.ht-lab.com


but haven't taken the time to learn enough TCL to try
(my testbenches are entirely VHDL and that keeps me busy enough!).

- Brian
Click to expand...
 
"HT-Lab" <hans64@ht-lab.com> wrote in message
news:5P86k.6335$aE7.5929@newsfe16.ams2...
"Brian Drummond" <brian_drummond@btconnect.com> wrote in message
news:bt4i541q56gf2ukbbgbtvahq6nrlt0jo31@4ax.com...
On Wed, 18 Jun 2008 04:57:04 -0700 (PDT), Kolja Sulimma
..
There are options in some libraries (numeric_std for one) in Modelsim to
suppress these warnings; but this carries the risk of suppressing real
information. So I don't think that's a good idea either.

I just ignore them... (actually I pay a LITTLE attention to reducing
their number, but it's not important) ... but wouldn't it be nice to
tell the simulator to suppress these errors for the first XXX ns, then
report them.

I expect a simple TCL script would do it...

suppress Numeric_Std invalid value warnings;
run 250 ns;
enable Numeric_Std invalid value warnings;
run;

Close,

set StdArithNoWarnings 1
set NumericStdNoWarnings 0
run 0 ns;
set StdArithNoWarnings 0
set NumericStdNoWarnings 0
run ....
Click to expand...
Doh!

set StdArithNoWarnings 1
set NumericStdNoWarnings 1
run 0 ns;
set StdArithNoWarnings 0
set NumericStdNoWarnings 0
run ....

Hans
www.ht-lab.com
 
"Kolja Sulimma" <ksulimma@googlemail.com> wrote in message
news:8e8331f2-d305-40db-8b97-fd0c2c8ba02d@x35g2000hsb.googlegroups.com...
On 18 Jun., 16:29, "HT-Lab" <han...@ht-lab.com> wrote:

Doh!

set StdArithNoWarnings 1
set NumericStdNoWarnings 1

LOL.
How about:
set NumericStdNoWarning 'X'
Click to expand...
If you give that command than Modelsim will automatically un-install, delete
your license file and block any emails to support@..... Of course this only
works in version 6.3, 4.7 to 6.2 simply deletes your partition table.
Version 6.4 (expected soon) will also send an email to your boss to get you
fired,

Hans
www.ht-lab.com

Kolja
Click to expand...
 
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