EDK : FSL macros defined by Xilinx are wrong

[Greg Brown]

Hi Mordehay:

Go to www.xilinx.com/edk

On the lower right, under documentation, select the Embedded Design
Examples. In the table of examples, you will find MB - ChipScope Design.

-Greg

me_2003@walla.co.il wrote:

Hi John,
Thanks for the answer, is there anywhere where I can get a reference
design or appnote
that describes such a design (CS + MDM) ?
Thanks, Mordehay.

 

[Simon Peacock]

That would be a hardware reset .. not software .... but it depends on
what you call a hard reset

Simon

"John Williams" <jwilliams@itee.uq.edu.au> wrote in message
news:43E985C4.8010303@itee.uq.edu.au...

Simon Peacock wrote:
Jump to the reset vector ?

You need to generate an OPB reset signal, otherwise your peripherals are
not reset.

A single-bit GPIO driven through a pulse widening state machine , with
its output tied to the OPB_Rst signal, is one simple way.

John

 

[Zara]

On Tue, 07 Feb 2006 09:28:47 -0600, "Karel" <karel@gemidis.be> wrote:

Hey all,

I was wondering how to write a software reset in C-code for
the Xilinx Microblaze.

Regards

Karel

pseudo-code:
disable interrupts
jump to address 0
assembly:
mts MSR,R0
bra R0


REgrads,

Zara

 

[Jim Granville]

fpga_toys@yahoo.com wrote:

Jim Granville wrote:

Please do, we can agree there is an effect, my antennae just question
how much of an effect at DC ?.

You still have to satisfy ohms law, so any push effects that favour
flow, have to model somehow as mV(uV) generators....
To skew Ball DC currents 7/8 or 15/16, frankly sounds implausible, and
maybe the models there forgot to include resistance balancing effects ?
[ ie do not believe everything you are 'told' ]


The problem is that there may not be ANY DC component.

Two issues there:
i) This discussion ( with Austin) was explicitly about DC current spread
and what splitting effects there may, or may not be, and their values.

ii) You have seen the latest FPGA data sheets ?
I see the 90nm device from lattice, can draw 1.5 AMPS, at 105'C Tj
That's just static Icc.

Thus, the latest FPGAs are a long way from your classic CMOS...
DC current is there, and at not insignificant levels...

-jg

 

[Michael Laajanen]

HI,

Leow Yuan Yeow wrote:

Thanks for all your patience! I have never used the command line before, and
the gui seems to only allow a project to have files of the same type: vhdl
source files, schematic, edif, or ngc/ngo.
Is this what I should be doing?
1. compile vhdl file into ngc file >> say myngc.ngc
2, "nbdbuild myedif.edf myngc.ngc" to combine the edif file and the ngc
file into a single .ngd file
3. use xst on the ngd file?

I have looked at the XST manual for command line...but it looks like greek
to me. Am I supposed to learn how to do it my trial and error and figure it
out myself here or is there any some better tutorial out there?
Thanks!
I would suggest that you use the ISE GUI and its workflow.

/michael

 

[Jon]

Hi there,

As far as I know (and I may be wrong, though I've never really
investigated this) getting a vcd file with bus value changes instead of
individual bit changes isn't possible. Check the modelsim documentation
to be sure...

You could write a program to parse the VCD file and translate
individual bit changes into changes on a bus. Parsing the file isn't
difficult, but if you're in a hurry this might not be the best way to
spend your time!

As for an option in the GUI in modelsim to generate vcd files, I've not
seen one either... You may find that the FPGA vendor tools you are
using will do this for you though - I think there's an option in Xilinx
ISE to generate a ".do" file for modelsim with the vcd stuff included.

Sorry I haven't been very specific, but I hope that's useful.
Jon

 

[eehinjor]

Thank you.Ian Muncaster.
By the way,
In the spec:the length of CLK is 2.5inches +-0.1inch.
if there is a qs3861 or resistor between connector and fpga,how can I
calculator the length of PCB-trace?

 

[Ian Muncaster]

RIGHT this is some calculation:

Wouldn't advise using a resistor?

For the QS381 the maximum propagation is 250ps, using a signal propagation
of 1ns equals 12inches for lightly loaded line or 3inches for a loaded line
(using bus switch most likely means lightly loaded) we can work out the
equivalent trace length the bus switch would represent.

Doing this you would find that this fails the PCI spec, we have seen no
problems if you just make sure your clock trace is longer than your worst
case for the rest of the bus. This means that the setup and hold times are
met.



"eehinjor" <eehinjor@163.com> wrote in message
news:1139485190.614959.181580@o13g2000cwo.googlegroups.com...

Thank you.Ian Muncaster.
By the way,
In the spec:the length of CLK is 2.5inches +-0.1inch.
if there is a qs3861 or resistor between connector and fpga,how can I
calculator the length of PCB-trace?

 

[Brannon]

1. compile vhdl file into ngc file >> say myngc.ngc
2, "nbdbuild myedif.edf myngc.ngc" to combine the edif file and the ngc
file into a single .ngd file
3. use xst on the ngd file?

Concerning your step two, you have to declare one of the two as a black
box in the other. You can do this in EDIF by just having an interface
declared with no contents section. The object containing the black box
will be the top-level object. Send that top-level file to ngdbuild with
the other file in the same folder. ngdbuild will automatically merge
them. You'll see it in the log.

I usually use ngc2edif to make an ngc file a black box in my EDIF; I
just take the output of the ngc2edif and chop it down to the (cell ...
(interface ....) declaration, put two parenthesis on the end, and then
paste that into my EDIF file.

 

[richard]

The "real" problem lies in that the folks who manage and those who
generate software tools are seldom folks who have extensive experience
with using tools of that genre. I've often had the unfortunate
experience of dealing with software "engineers" who insist on putting
in features not required for the product to work as specified, "stubs"
for future unspecified features, etc. and yet have omitted features
without which the product was useless.

I think a proper treatment for software generators and their bosses
would be to lock them in a room with their product and a task
assignment, and not allow them to leave the room for any reason,
including bathroom breaks, until (1) their work was fully verified
against the objective specification, (2) they had completed their
task, in this case, perhaps, generation, verification, and
implementation of a 2M-gate FPGA which required the use of each and
every claimed gate in the FPGA (maybe locking a marketing manager in
with them would help, so they'd have something/someone to eat) on a 16
MHz '386 with the minimum of RAM and HDD space. You might as well weld
the doors shut, because that would never happen.

What puzzles me is how they can take such a giant step backward. Sure,
there were some bugs. Their support people always denied that they
were bugs, but they were. Whenever it internally interprets a simple,
A=>A, B=>B, signal routing as A =>B, B =>A, it's obviously a bug. They
deny it and try to sweep it under the rug, but it's a bug. It just
reproduces under the rug and becomes a colony of them.

Richard

 

[Leow Yuan Yeow]

Thanks for all your patience! I have never used the command line before, and
the gui seems to only allow a project to have files of the same type: vhdl
source files, schematic, edif, or ngc/ngo.
Is this what I should be doing?
1. compile vhdl file into ngc file >> say myngc.ngc
2, "nbdbuild myedif.edf myngc.ngc" to combine the edif file and the ngc
file into a single .ngd file
3. use xst on the ngd file?

I have looked at the XST manual for command line...but it looks like greek
to me. Am I supposed to learn how to do it my trial and error and figure it
out myself here or is there any some better tutorial out there?
Thanks!

YY

"Duane Clark" <dclark@junkmail.com> wrote in message
news:zhtGf.23106$Jd.21261@newssvr25.news.prodigy.net...

Leow Yuan Yeow wrote:
Hi, may I know whether there is any free program that is able to convert
a vhdl file to a .edf file? I am unable to find such options in the
Xilinx ISE Navigator. I have tried using the Xilinx ngc2edif convertor
but when I tried to generate a bit file from the edf file its says:

ERROR:NgdBuild:766 - The EDIF netlist 'synthetic2.edf' was created by the
Xilinx
NGC2EDIF program and is not a valid input netlist. Note that this
EDIF
netlist is intended for communicating timing information to
third-party
synthesis tools. Specifically, no user modifications to the contents
of
this
file will effect the final implementation of the design.
ERROR:NgdBuild:276 - edif2ngd exited with errors (return code 1).
ERROR:NgdBuild:28 - Top-level input design file "synthetic2.edf" cannot
be
found
or created. Please make sure the source file exists and is of a
recognized
netlist format (e.g., ngo, ngc, edif, edn, or edf).

Any help is appreciated!

Xilinx's XST can be told to generate edif instead of ngc, though since
ngdbuild can understand the ngc format, I am not sure what you expect to
gain by doing it. You can combine ngc and edif files with ngdbuild, and it
should combine them fine.

Anyway, XST takes an "-ofmt" parameter, which can be set to "NGC" or
"EDIF". However, the gui does not provide a method for doing that, so you
would need to execute XST from the command line.

 

[John Williams]

Simon Peacock wrote:

That would be a hardware reset .. not software .... but it depends on
what you call a hard reset

OK, I'll give you that my reading of the question was "how do I
initiate a reset from within software".

In Linux land we call it "shutdown -r now"

John

 

[austin]

Yes,

Austin

Isaac Bosompem wrote:

Hi guys, I've been reading through the Spartan3 architecture embedded
multipliers app note and I can't seem to find out how long (in terms of
clock cycles) the sync multipliers in the Spartan3 will take. Can I
safely assume that after I have asserted the inputs to the module, I
will get the output back in the following clock cycle?

Thanks,

Isaac

 

[Paul Hartke]

Do you know what caused the issues with compiling busybox and sh? Is it
a build script issues, a cygwin issues, or a gcc issue?

"11.now you get core dump whild building busybox and sh, those need to
be pulled out and compiled out of tree and then injected back
12.the busybox and sh need to be in place in the build tree and the
makefile adjusted to skip them durin main build"

Antti wrote:

I am ! happy and smiling, I got finally fully working MicroBlaze
uClinux image built fully from GPL sources on WinXP without the use of
any linux machine or linux emulation.

here is short intro how todo this:

http://help.xilant.com/UClinux:MicroBlaze:Win32Build

I wish I could have time to add more detailed docu about the process
but I need to prepare some demos for the Embedded in Nurnberg what
starts next tuesday

Antti

 

[Rene Tschaggelar]

Sky wrote:

In a project I use the Altera EPM3256ATC144-10.
Now I have the necessity to make some changes to the project, but I don't
have enough macrocells in the actual devices.
Alteras doesn't have a pin-to-pin compatible EPLD with the EPM3256ATC144-10
but with more macrocelles (about +40%).
What of you knows a devices that could resolve my problem? Unfortunately I
cannot modify the PCB, but I could replace the Altera EPLD with any other
CPLD.

Depending on the required speed you may connect wires to the 144
pads... and connect then to an external box containing whatever.
Yes, I'm aware the wires are very fine. Thus, I'd rather
1) do a new pcb
2) squeeze a reduced functionality in the existing part.

Rene
--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

 

[Noway2]

That sounds like a wonderfull recipe for field failures if carried to
production. I might say that it would be workable for a prototype, but
I wouldn't go much farther than that.

You indicated in your original post that you are not able to modify the
PCB. Is there a real reason for this or is it just a case of where MGT
doesn't WANT to modify the PCB? Quite frankly, often times I have
found that far more enegy is spent attempting to take a short cut
around something and failing than would have been spent to do it right
the first time.

 

[Marlboro]

Isaac Bosompem wrote:

Hi guys, I've been reading through the Spartan3 architecture embedded
multipliers app note and I can't seem to find out how long (in terms of
clock cycles) the sync multipliers in the Spartan3 will take. Can I
safely assume that after I have asserted the inputs to the module, I
will get the output back in the following clock cycle?

Thanks,

Isaac

No asumption is safe, IHMO, run a simple simulation to verify it,
sometimes that's quicker than digging in the docs jungle.

 

[Albert Chang]

Hello Michael,

All simulation library files necessary for an Altera FPGA
functional/post-fitting simulation are installed automatically with the
Quartus II software. The simulation library files, in Verilog and in
VHDL, are located in the <Quartus II Installation
directory>/eda/sim_lib directory.

For more information on Altera functional library files, please refer
to
http://www.altera.com/support/software/nativelink/quartus2/eda_ref_presynth_lib.html

For more information on Altera post-fitting library files, please refer
to
http://www.altera.com/support/software/nativelink/synthesis/dc/eda_ref_dc_postsynth_lib.html

When performing post-fitting simulations, the netlist is generated in
the <Quartus II project directory>/simulation/<tool name> directory.
You can create your simulation libraries in this directory.

I'm not sure which simulation tool you are using, but we do have more
detailed information in our Quartus II handbook chapters:

Mentor Graphics ModelSim Support
http://www.altera.com/literature/hb/qts/qts_qii53001.pdf

Synopsys VCS Support
http://www.altera.com/literature/hb/qts/qts_qii53002.pdf

Cadence NC-Sim Support
http://www.altera.com/literature/hb/qts/qts_qii53003.pdf

I hope this helps,

Albert Chang

Altera Corporation
Senior Applications Engineer




Michael Laajanen wrote:

HI,

I am very new to Quartus(5.1 Solaris) and looking for simulation
libraries for both Verilog and VHDL, vhdl seams to be found in the
install tree but verilog?

When I used Xilinx I always started compiling a simulation libraries
once for all into the installation tree for each simulator to use, how
is this done i Quartus?

cheers

Michael

 

[Rene Tschaggelar]

Sky wrote:

Guys,
This is a long history. The project doesn't only include the EPLD, but also
many other expensive components.
Unfortunately the change will interest a lot of board already sold.
To change the PCB is certainly possible and I believe that this is the best
solution, but it is not acceptable for the marketing.
Someone has advised to look at the Lattice or Actel. products. I will look
for there also.
The solution proposed by Rene would be a true folly, also for a prototype.

Unfortunately some of the pins have a fixed assignment,
they usually are the programming pins TCLK, TMS, TDI,
TDO and CLK plus the power pins. At least Altera has
no system as to assigning these pins over the families.
Meaning in most cases the footprint is not upgradeable.
And since the manufacturer do not talk to each other
in the interest of the customers, you cannot expect a
competitor product to fit into the footprint what
the fixed pins concerns.

Rene
--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

 

[Carl Smith]

In article <yS5Hf.4488$9G6.474@tornado.fastwebnet.it>, dev2-
renato_noSpam@usa.net says...

The solution proposed by Rene would be a true folly, also for a prototype.
Thanks

How about an adapter PCB? Put a "bigger" part on the board and
mount the board in place of the old part. Kind of like those
adapter boards that let you adapt an SMT part to a DIP socket or
other footprints.