EDK : FSL macros defined by Xilinx are wrong

[Sylvain Munaut]

Jeff Shafer wrote:

Thanks for the idea Sylvain. That would work for the test program I
described, but that was written only to illustrate the problem. In reality,
we'd like to have this shared scratchpad readable and writable by both
PowerPCs. So while registering and inverting the clock would work for the
writes, I think it would corrupt reads by that processor....

It depends of the controller. If you can modify it to tolerate more
pipeline (i.e. the read data doesn't appear at T+1 but T+2 (or T+3,
depdnds if your timing margin requires u to re-register dout or not)).

But the two processors are not equal ... one has less latency ...

Thanks,

Jeff


"Sylvain Munaut" <com.246tNt@tnt> wrote in message
news:43e3b444$0$13886$ba620e4c@news.skynet.be...

As I understand, you use 1 port always for read and another always for
write.

So you could clock the write port on the negative edge even while
keeping the two processors and their plb bus on the same clock. Let's
says clk is your main clock. Instead of feeding di,dip and wren directly
to the BRAM, register them in the clk domain, then connect the output of
these registers to the respective port of the BRAM and feed "not clk" to
the wrclk ping of the BRAM.


Sylvain

 

[Mike Treseler]

shawnn@gmail.com wrote:

When doing development using microcontrollers/processors, you can often
find ICEs and ICDs that allow you to set breakpoints. You can stop the
code in execution and view the contents of registers, state of input
pins, etc.
Suppose I want to do something similar with an FPGA-based design. What
are my options? I know I can output internal signals to output pins and
sniff them using a logic analyzer, but I'm hoping there is a more
elegant solution. I'd like to stop everything at some point and view
all inputs, outputs, registers, etc.

If you learn an HDL, modelsim will allow
you to trace your code and set breakpoints
during a simulation. Much more elegant
than a logic analyzer.

-- Mike Treseler

 

[Hal Murray]

Once one has done the compiling,
How fast can one program
an fpga anyway?

Look in the data sheets. There will be a max clock rate
and a table of number-of-config bits vs chip size.

--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.

 

[Falk Brunner]

Austin Lesea schrieb:

What I claim is that the force of the third added wire will be less than
that of the first wire, and the force of the first on the same side of
the glass wire will be somewhat less, but will not be 1/2. In fact with
the BART rail spacing, it would be 2/3 and 1/3.

At DC.

Guess what? Current creates a field, a field tells current how to flow.

I think Faraday discovered this?

;-) This is really funny. A very basic effect of physics is "forgotten"
by the highly trained specialists.

Maybe I can jump in and help to enlight the non-belivers. The effect in
question is called Lorentz-Force (Lorentz-Kraft in german). Its the
effect that makes every electrical engine spin. Just have a look at
those small toy motors, they use a permanent magnet to greate a static
magnetic field and a DC current inside the rotator loop. OK, the current
gets reversed by the commutator every fraction of a revolution, but this
is not the point. Another example is the good old CRT TV set. A (quasi)
magnetic field is used to deflect a electron beam (moving charge carriers).

This works by the way for superconducting wires, resistance has no part
in this. R does not appear in the equations to show this is true.

QED for this "Gendanken" Experiment...

"Gedanken"Experiment. Just a small typo. (yeahh, germans are known to be
real pedantic ;-)

Regards
Falk

P.S. To be onest I never thought of the magnetics stuff before when
looking at the GND/VCC balls on a package. Interesting!

 

[Petter Gustad]

"Martin Schoeberl" <mschoebe@mail.tuwien.ac.at> writes:

I've used quartus_pgm in a makefile successfully some time (and perhaps
some Quartus version) ago, but now I get a strange error:

Info: Command: quartus_pgm -c ByteBlasterMV -m JTAG -o p;quartus/cycconf/cyc_con
f_init.pof

I usually have a chain description file, i.e.

quartus_pgm -c ByteBlasterMV -m JTAG chain.cdf

The cdf files describes order of the jtag chain as well as the name
and location of the pof file.

Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

 

[Falk Brunner]

austin schrieb:

Just think how surprised those Westinghouse Engineers were when they had
10,000 trains....and 6 empty train blocks light up on the 10 meter by 3
meter map display!

Hmm, but why didn't they have a small prototype for testing? Or did they
think this is sooo trivial no need for testing?

Regards
Falk

 

[Paul Hartke]

MontaVista does not have a strangle hold on the anymore than RedHat has
a strangle hold on x86 Linux. MontaVista developed the OS adapters for
the Xilinx peripheral cores and has submitted them to the appropriate
open source repositories. They do provide commercial support and extra
benefits by working with them. However, everything required is
available open source.
Earlier this week I yet again compiled Linux from scratch for the
Virtex2Pro PowerPC405 from the excellent Howto hosted by UIUC:
http://www.crhc.uiuc.edu/IMPACT/gsrc/hardwarelab/docs/kernel-HOWTO.html

The same is largely true for Microblaze uclinux. It is an open source
project and Petalogix (http://www.petalogix.com/) is available to
provide commercial support/services should that be of interest to you.

In terms of performance, the only difference between Linux and uClinux
is the former requires a Memory Management Unit (MMU) while the latter
does not. For all intents and purposes that doesn't affect performance
directly. The lack of memory protection support can in theory make
software more difficult to debug but there are tons of products shipping
using uClinux so plenty of folks have figured this out.

In contemporary FPGAs, a hard-core processor such as the PowerPC405 will
operate at 300MHz whereas a soft-core processor such as Microblaze
operates around 100MHz. However, overall application performance is
dependent on many factors besides just the processor core operating
frequency.

As for multi-processor designs, neither the PowerPC405 nor Microblaze
directly supports cache coherency. However, there are many ways to
partition a problem so that more than one processor contributes to the
application solution. These issues are discussed here periodically.

A final note. The exciting part about processors in FPGAs is that so
many design parameters are flexible--both the hardware and software
architectures can be adapted to the problem at hand. Many more
opportunities but also much more rope to hang yourself with.

Exciting times!

Paul

Anonymous wrote:

Thanks for all the feedback recently on linux on Xilinx. I think I
understand it now:

PPC linux is faster and technically superior but monte vista has a strangle
hold on the source and tools which discourages anybody from using it.

uClinux/microblaze is slower but more open source and easier to get a system
up and running with.

Is that about the picture?

Also, I was wondering if anybody has a multi-processor flavor of Linux
running on xilinx? Seems like an obvious next step since there are multiple
PPC cores in the chips.

Thanks,
Clark

 

[John McCaskill]

Anonymous wrote:

Thanks for all the feedback recently on linux on Xilinx. I think I
understand it now:

PPC linux is faster and technically superior but monte vista has a strangle
hold on the source and tools which discourages anybody from using it.

MontaVista provides some sort of design environment, and paid support.


You can also get a free Linux distribution and design environment from
Denx:

http://www.denx.de/en/News/WebHome

This was what came with an Avnet V2Pro development card that we bought,
and it has worked fine for us. It was the 2.4 version of the kernel.

Is there anyone here that has used MontaVista that would care to
comment on their experiences?

I spent about an hour on the phone with someone from MontaVista a while
back trying to figure out what they are offering. I asked to have
someone technical call me. The person that did call could tell me the
price of everything, but could not tell me much more than they provided
a design environment and paid support by the "incident". She had no
idea what qualified as an incident.

I asked if they would be providing Linux drivers for the Xilinx cores
in the EDK. She did not know, but said she would call me back with an
answer. I never heard from them again. I wrote my own drivers for what
I needed, and did not bother trying to call them again.

uClinux/microblaze is slower but more open source and easier to get a system
up and running with.

Is that about the picture?

Also, I was wondering if anybody has a multi-processor flavor of Linux
running on xilinx? Seems like an obvious next step since there are multiple
PPC cores in the chips.

While there are two PPCs in many of the Xilinx chips, they do not
support cache coherency which you really want if you want to run an SMP
single image kernel. You could run two independent copies of the
kernel.

Thanks,
Clark

 

chessaurus@yahoo.com wrote:

1) It needs to have a simple, nonproprietary logical architecture,
similar to the "sum of products" architecture of many PALs
2) It needs to have a well-documented architecture, i.e., I need to
know how each configuration bit relates to the device's internal
configuration.

The bit streams for XC4000 and Virtex devices are pretty well
documented,
as you can extract most of the info from the configuration guide of
Virtex
parts, the fpga editor, and JHDL's router/bitstream tools. There are a
few
otherwise hidden bits, but outside what you would normally program from
what I understand. Readback/column programming gets you 98%???

3) It needs to be high density (as high as possible given hard
requirements 1 and 2, above).

I'm not an expert on current product offerings, but it seems to me that
today's high-density programmable devices (CPLDs and FPGAs) have become
more complex & proprietary. Given my needs, am I stuck with the PLA
devices of the 80s?

Depends just how much you are willing to be flexible on 2.

 

[Peter Ryser]

PPC linux is faster and technically superior but monte vista has a strangle
hold on the source and tools which discourages anybody from using it.

Not true. Support for Xilinx PowerPC is available in the linuxppc open
source repository which is picked up by various distributions.
MontaVista Linux is one such distribution.

uClinux/microblaze is slower but more open source and easier to get a system
up and running with.

Bringing up a Linux system is always a complex task. Linux for
MicroBlaze and PowerPC are open source.

Also, I was wondering if anybody has a multi-processor flavor of Linux
running on xilinx? Seems like an obvious next step since there are multiple
PPC cores in the chips.

The PPCs in Virtex-II Pro and Virtex-4 do not support bus snooping to
maintain cache coherency. With that you cannot run the two PowerPCs as
an SMP system. However, you can run an instance of Linux per PowerPC.

- Peter

 

[Peter Ryser]

DCR bus stands for device control register bus. It can be used to
control devices. In EDK the PLB2OPB, the OPB2PLB and the INTC have a DCR
interface (the INTC is also available as an OPB version). The PPC has a
native DCR master interface while the MB does not have a DCR interface
at all, however, there is an OPB2DCR bridge.

The DCR is a very simple bus. It is not high-performance and really
intended to be used for control operations.

To learn more about the DCR interface have a look at the PowerPC
Processor Block Manual [pg. 100ff]
(http://www.xilinx.com/bvdocs/userguides/ug018.pdf).

- Peter


me_2003@walla.co.il wrote:

Hi ,
I would realy appreciate it if someone could explain the possible usage
of a DCR bus (with PPC or MB).
Thanks in advance, Mordehay.

 

[rickman]

al99999 wrote:

Hi,

Has anybody ever designed anything to decode and display GPS NMEA data
coming out in ascii form from a UART?

Any ideas of where to start or how to go about decoding comma delimted
ascii strings?

I think this would typically be done using a processor rather than an
FPGA. Even a small, single chip MCU would have enough horsepower to
handle the 4800 bps data rate and control a display. But of course
that depends on the interface to the display. Generating a VGA signal
would take a bit more than sending a serial bit map to a small LCD.

If you really want to do this in an FPGA you would need to construct
state diagrams for the logic that will parse the input stream and
generate binary numbers from the characters. This will take some
significant logic since it involves muliplications. Then you need to
design a circuit that will draw lines in your display based on your
current and last position, again, this can be a lot of logic to figure
out.

I think if I was told to do this in an FPGA, I would construct a CPU in
the FPGA (or use one of the CPUs provided by the FPGA vendors) and find
C code to draw the display. The rest of the work is easy in software.

 

Thanks Peter,
So if I understand you correctly, the DCR is to be used mainly in PPC
designs and not in MB.
I have another question if possible - I would like to know if it is
possible to debug a MB design with both sw debug (MDM) and hw debug
(chipscope), the reason for this question is that both of this modules
are working via JTAG.
Thanks in advance, Mordehay.

 

[John Williams]

Hi Clark,

Anonymous wrote:

Also, I was wondering if anybody has a multi-processor flavor of Linux
running on xilinx? Seems like an obvious next step since there are multiple
PPC cores in the chips.

As other posters have said, V4FX/V2Pro PPC and MicroBlaze both lack
cache coherency support. So, it's not really feasible to implement SMP
Linux on either architecture.

We've sketched out plans for a MicroBlaze cache snoop unit and protocol,
but ultimately you still require some software-intrusive stuff - slow
slow slow.

It's also not very scaleable, a 4-way cache snoop architecture would
quickly consume logic gates that would be better used doing real work.

SMP is a compromise. It makes sense if you have to optimise an
architecture across as many use-cases as possible - ie fixed silicon.
In FPGA-land, we should be designing custom architectures to suit each
application, and SMP will rarely be the best architecture for any
particular problem.

That said, I do have an implementation of dual mb-uclinux kernels
running from the same memory. It works fine, you can use either shared
memory or FSL or even ethernet to communicate between them. However,
it's not SMP.

Regards,

John

 

[John Williams]

me_2003@walla.co.il wrote:

I have another question if possible - I would like to know if it is
possible to debug a MB design with both sw debug (MDM) and hw debug
(chipscope), the reason for this question is that both of this modules
are working via JTAG.

Yes, they can work together. You can even do tricky stuff like connect
the chipscope and MDM triggers together, so that you get a bus trace of
the previous NN cycles prior to a CPU trap, that sort of thing.

Unfortunately it doesn't work in V4 ES (early silicon) parts due to a
silicon bug. I assume it was fixed for production silicon.

John

 

[Sylvain Munaut]

You have two choice :
- Keep the 1 line prefetch architecture and use Distributed RAM. 128x8
will take you 16 Slices but you then need a 4:1 mux to select between
pixels
- Continue with the block ram and fetch 8 lines at a time, then you
can use the asymettric port width features of the BRAM to select
between pixels.

 

[Michael Schöberl]

bjzhangwn schrieb:

thanks,can i have a look at your document or source files?

I'm sorry I can't disclose any source ...
the documents you will need can be found at www.t13.org


bye,
Michael

 

[Dave]

Jonathan Schneider wrote:

For making fine modifications to PCBs, which of Tefzel and Kynar
insulated wired are best to use ?

Jonn

Tefzel strips easily, but the insulation isn't so rugged - tends to melt
easily

Kynar can be interesting to strip, but will withstand a soldering iron touch
etc

Sometimes 'enamel' (actually polyurethane) coated wire is the right thing to
use, because you can tin the end without having to apply a force to strip it
! It is also easier to bend into an awkward corner. Obviously it is not as
strong ...

Tack it down afterwards with hotmelt or cyano

Dave

 

[Sylvain Munaut]

er ... 32 slices not 16 ...

but as John pointed out, the 128x1 macro might not work in
spartan3/virtex4 ...

 

[Antti Lukats]

<shawnn@gmail.com> schrieb im Newsbeitrag
news:1139247241.938636.127450@g44g2000cwa.googlegroups.com...

Thanks for the replies everyone, they have been very helpful.

Does Lattice provide a vendor-specific monitoring library like Xilinx
and Altera??


shawnn@gmail.com wrote:
Hello,

When doing development using microcontrollers/processors, you can often
find ICEs and ICDs that allow you to set breakpoints. You can stop the
code in execution and view the contents of registers, state of input
pins, etc.

Suppose I want to do something similar with an FPGA-based design. What
are my options? I know I can output internal signals to output pins and
sniff them using a logic analyzer, but I'm hoping there is a more
elegant solution. I'd like to stop everything at some point and view
all inputs, outputs, registers, etc.

Can someone point me in the right direction?

yes, included for free ispTrace

Antti