EDK : FSL macros defined by Xilinx are wrong

Gabor wrote:
The usual problem here is hold time violations going from the
fast process to the slow one. If your (expression) in the slow process
uses any outputs of the fast process, then you can have hold time
violations due to the slowclk delay. Note that the skew times in
your timing report are within each clock domain and don't indicate
skew between the two clocks.
Click to expand...
I see. Thanks the for explanation Gabor. Perhaps I'm better off using
John's idea.

Regards,
Paul.
 
"Isaac Bosompem" <x86asm@gmail.com> wrote in message
news:1139254458.451186.266750@z14g2000cwz.googlegroups.com...

<snip>

I am not pushing the SRAM to its maximum speed. The SRAM on my board
has a 20ns access time, so I get a little less than 50Mhz when taking
setup and hold times into account. I might be able to use a lot more of
the BlockRAM using that speed but that would require me to utilize the
2nd port making it unavailable to external entities. The framebuffer
reader will stay ahead of the raster counters.

I will try and see if a clock multiply will help, thanks for the tip
with the DCM. If you had not told me that I would have used the
original signal for the parts that run at 25Mhz.
Click to expand...
The multiply makes life much easier. You can even run the entire design at
50 MHz but use a clock enable every-other clock to get 25 MHz processing
downline. With the clock-enabled configuration, it might become more
obvious how you can still use the BlockRAM at 50MHz without using the second
port to do it.
 
You could look at the BYU work on this.

http://splish.ee.byu.edu/projects/LinuxFPGA/index.htm


ramesh wrote:
Hi All,
Iam new to xilinx platfrom.

I was trying to port open source linux on Ml403 board. i tried to
follow the instructions in the below link.
http://www.klingauf.de/v2p/index.phtml
i was getting errors when i was running bZimage. the .elf file was not
getting created.

Is there an alternative way of acheiving my goal.
Kindly suggest.
Thanks in advance.

Ramesh
Click to expand...
 
gnathita wrote:
Hello,

I ported linux 2.4_devel to the ml403 board.

Feel free to ask me about what I did if you need help.
Paula
Click to expand...
We are about to undertake this effort as well. I would greatly
appreciate it you could do a quick write up for this thread regarding
your process. Specificlly detailing which document(s) and/or
instructions you followed to do the port, URLs for where these can be
found, and most importantly where you departed from the starting
points, and/or stumbled.

We talked to Timesys and MonteVista both about this. The former sounds
promising, and if they had an existing port for ML403 as a starting
point we would probably just pay for their subscription service. The
later did not offer a business model that was compatible with our
needs. The business model can make sense for a lot of customers. We
are both an ODM and a Design for Hire shop, and the model would work
for some but not all of our customers/engagements. I do not intend to
comment further on this. Please talk to MonteVista directly if you
want to understand the business model, as I do not want to risk
misadvising.

We are also considering doing this without using an outside service, so
your comments will be of value to me in our decision making process.

If there are any consultants that have done a Linux 2.4 port to a
Xilinx platform (either V2pro or V4FX, located in the greater Boston
area, please feel free to drop me an email, and we'll chat offline. We
might consider using an outsider to bring some of my guys up to speed,
and help with our port and/or drivers.

We are excited about the possibilities of Linux on V4FX. We are
presently using the ML403 board as the basis for our compute platform,
and intend to use Linux. I, like others, am not interested in
reinventing the wheel.

We are doing the initial development on our projects with ML403 and
custom daughterboards. We will then build the completely custom
systems. The ML403 is a very well thought out platform. Previously,
we would build custom hardware before even starting the application
development.

For the past four years our compute platform was based on V2/microBlaze
and/or V2pro/PPC with homebrewed DOS file system, and no OS. But now
that we need to incorporate TCP communications and much more
complicated applications support, an OS (specifically Linux) is the
direction we are headed.


Regards,
Erik.


---
Erik Widding
President
Birger Engineering, Inc.

(mail) 100 Boylston St #1070; Boston, MA 02116
(voice) 617.695.9233 x207
(fax) 617.695.9234
(web) http://www.birger.com
 
Alan Myler wrote:
Cyclone is not compatible with PCI 5v, the voltage transients
exceed 5v and will damage the device.

You will need to use IDT Quickswitch or similar device to
limit the input voltage to your Cyclone in a 5v scenario.

Google for PCI and quickswitch, you should find a Xilinx
app's note on the subject.
Click to expand...
.... or look a the schematics for the Altera Cyclone PCI development kits.

-hpa
 
Thanks,can i have your msn,and I have some question to ask!
Why should i need the Power-on and hardware reset protocol and the Bus
idle protocol,I think only i just need are the
- PIO data-in and data-out command protocol
- Ultra DMA read/write of a block
Do the registers transfer use the pio protocal?
 
MUo is small, at 4*pi*10e-7 weber/amp-meter
( that's why you need many turns, and small air gaps, in a motor )
Click to expand...
You can get motion from single turns as long as you use a enough current.

The Exploratorium has (had?) an exhibit with several 1 inch dia wires
running vertically reasonably close to eachother. They were attached
at top and bottom but not constrained in between. 6 or 8 feet high.
You step on a switch and it dumps a lot of current into the wires.
They move.

(I forget the details. It's been a few years since I saw it.)

--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.
 
Where can I find the ata device bus function model for
simulation?Thanks!
 
Hi ,
Do you have any kind of documentation or any URL where i can find how
to port linux on ML403?

Ramesh
gnathita wrote:

Hello,

I ported linux 2.4_devel to the ml403 board.

The zImage. that you get is fine for loading into the Virtex4 ppc. The
only thing you need to do is "cp" it to another directory with the .elf
extension.

I integrated it with my download.bit into an .ace file and it works ok
both for the reference design and for my custom design (a basic one).

Feel free to ask me about what I did if you need help.
Paula
Click to expand...
 
Simon you're right.
To solve this problem it is suggested to upgrade to the Designer 6.
The other option is, to install xilinx ise 7.1 which is the option i
chose.

Nils
 
Dolphin wrote:

I would like to have the Microblaze fetching code from the SPI flash. The
problem is that I have to use the OPB SPI interface for this and this
interface is not a 'real' memory interface.
Click to expand...
Even if you manage to hide that (behind a gazillion wait states) it's
going to be painfully slow.

You need to either implement pre-fetch and caching in BRAM, or more
likely segment your code into various modules with a routine that loads
and unloads them from BRAM as neeeded.
 
<ALuPin@web.de> wrote in message
news:1139308332.626061.130260@f14g2000cwb.googlegroups.com...
WHY do Verilog users post in this newsgroup ?

Rgds
Andrés


Why do responders keep the full cross-post list?

- John_H
 
Dolphin wrote:
Hello,

I have the following system:
- A Spartan 3E 500 FPGA
- Some internal BRAM memory
- An external SPI flash

The external SPI flash contains the instruction code. However I can't use
a bootloader because the internal BRAM memory is not big enough for all
the code.
We don't use an external memory because price is important for this design
(every $ counts).

I would like to have the Microblaze fetching code from the SPI flash. The
problem is that I have to use the OPB SPI interface for this and this
interface is not a 'real' memory interface.
Click to expand...
If your 100MHz MicroBlaze fetches it's instruction directly from the Flash,
this will require 64 clock cycles at 20MHz for each 32b instruction. This
reduces the MicroBlaze instruction rate to about 330kHz.

If the instruction cache is enabled then the speed should improve by 10-100
times, depending on code.

Memory management is needed as the code exceeds the available memory. For a
small application this is most simply done in software. For example, if
your user interface is much larger than the application core, split it into
a number of modules.
Compile the user core and first level menu of the user interface into the
base code memory area. Determine the free system code space. Compile the
user interface modules to each fit into this space.
On selecting an item on the configuration menu, copy the required overlay
into the shared code memory area.

Has anyone had a similar problem? How did you solve it?
Click to expand...
I'm developing a processor which reads code 'phrases' from serial flash to
improve performance further, without using a general cache. This is to
target very small, or 'zero power' requirements.

hth Jan Coombs.
--
murray-microft ltd slidapro at <my-domain>
 
The timing spec you want in the I2C bus specification is called
tHD (data hold time after falling edge of SCL). Minimum spec is
0 ns (like your first picture) maximum depends on whether you are
driving SCL or not. For a master just be sure to meet the setup
time to the next rising edge of SCL. For a slave, you need to observe
the maximum for the clock rate used, because you can only control
the rising edge of SCL if you implement clock stretching. For 100 KHz
devices, the max is 3.45 uS. for 400 KHz it is 900 nS.

The best practice is usually to sense that the SCL line has fallen
using feedback from the pin, and then allowing the data to change.

Regards,
Gabor

hyankijitu@gmail.com wrote:
hi!
i am developing i2c master in FPGA. suppose ia m transmitting 1.
i have doubt whether data transition should be at mid edge of
scl when it is low or at the falling edge as in the below waveform.

scl -------------- ----------------------
| |
|
/ here
| / or |
|
------------------
----------------------------
|-------------------
| here |
SDA ----------------------
|------------------------------------
Click to expand...
 
HI,

Leow Yuan Yeow wrote:
Hi, may I know whether there is any free program that is able to convert a
vhdl file to a .edf file? I am unable to find such options in the Xilinx ISE
Navigator. I have tried using the Xilinx ngc2edif convertor but when I tried
to generate a bit file from the edf file its says:

ERROR:NgdBuild:766 - The EDIF netlist 'synthetic2.edf' was created by the
Xilinx
NGC2EDIF program and is not a valid input netlist. Note that this EDIF
netlist is intended for communicating timing information to third-party
synthesis tools. Specifically, no user modifications to the contents of
this
file will effect the final implementation of the design.
ERROR:NgdBuild:276 - edif2ngd exited with errors (return code 1).
ERROR:NgdBuild:28 - Top-level input design file "synthetic2.edf" cannot be
found
or created. Please make sure the source file exists and is of a
recognized
netlist format (e.g., ngo, ngc, edif, edn, or edf).

Any help is appreciated!
YY


Hmm is it possible to embedd VHDL constructs in EDIF really?
Click to expand...

Then who will do the syntheses?

/michael
 
al99999 wrote:

PicoBlaze should handle it if it's not too complex. You may run out
of instruction space (the 8-bit PicoBlaze for Spartan 3 is limited to
1K instructions if memory serves me right). This does not require
the EDK and is published as a reference design with source.



Is there a C compiler for PicoBlaze?
Click to expand...
:) - No, not at that code size / core resource ....
These are tiny cores, intended for simple SW assisting tasks..

There are assemblers, and the AS MacroAssembler now supports both the
Xilinx PicoBlaze, and the open source Lattice Mico8.

See
http://john.ccac.rwth-aachen.de:8000/as/download.html

-jg
 
On Tue, 07 Feb 2006 16:20:49 -0800, Brian Davis wrote:

Sylvain Munaut wrote:

I wanted to submit a webcase but when I login into the webcase system
all I get is "Internal Server Error" ...

I've been having similar problems trying to look up an old webcase
for a couple of weeks now, and either :

a) can't log in

or

b) can log in, search, and find the webcase title; but when I click
on the webcase link: "The page cannot be displayed"

Brian
Click to expand...
Sounds like, after having released 8.1, they sent the programmers to the
Bahamas or something. ;-)

Thanks!
Rich
 
On the ML403 you could start with the .config file in the reference
design at
http://www.xilinx.com/products/boards/ml403/files/ml403_emb_ref_ppc_71.zip
..

- Peter

> I'd like a copy of your .config file?
 
For example the Users Guide for ML403, pg37:
http://www.xilinx.com/bvdocs/userguides/ug082.pdf

- Peter

ramesh wrote:

Hi ,
Do you have any kind of documentation or any URL where i can find how
to port linux on ML403?

Ramesh
gnathita wrote:


Hello,

I ported linux 2.4_devel to the ml403 board.

The zImage. that you get is fine for loading into the Virtex4 ppc. The
only thing you need to do is "cp" it to another directory with the .elf
extension.

I integrated it with my download.bit into an .ace file and it works ok
both for the reference design and for my custom design (a basic one).

Feel free to ask me about what I did if you need help.
Paula
Click to expand...
 
al99999 wrote:
Thanks for all the advice. I have a Xilinx spartan 3 starter kit that
i'd like to use to implement this, but not EDK. Any suggestions for a
simple CPU to use on the FPGA?
Click to expand...
Actually, I think I would give a try to doing it as a state machine
before I tackled the complexity of adding a CPU with memory and IO then
trying to get a program written, compiled or assembled, loaded into the
memory and finding a way to debug the whole thing. If you had a
working CPU with toolset that was fully integrated, that would be
different. But the sequence you are parsing should be pretty simple to
do in a FSM (finite state machine).

What you do to update the display, that is a different matter. But
then that might not be easy in software either. What is your display
task like?
 
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