EDK : FSL macros defined by Xilinx are wrong

[David Brown]

Antti wrote:

ROTFL - I ended up looking with google for SCNR

well, I hope Andre (will be 4 on 5 May this year) is bright, but its
kinda hard to tell as he isnt talking so much, to the extent that makes
us to worry already. 3 words sentences do come(in 2 languages), but

If he is being raised bilingually, it is perfectly normal to be a slow
starter at speaking. The kid has to learn two different languages at
the same time, and that takes a bit longer to sort out. If the two
languages use very different sets of phononyms, it's even harder, as it
also takes longer for the brain to train the ears. Another influence is
if he is getting on with life fine without saying much, then there is
less incentive to learn. It can all add up and make a great difference
- my first kid was extremely fast to learn to speak, while our second
was almost worryingly slow.

thats about it. But he has its own view how to build things and has
great joy in drawing and painting, and does teach his daddy how to make
pann-cakes (this is no joke). As of that model airplane, well my wife
helped me to get it together - the weights at the front fuselage had
strip off glue for fixing (I assumed they are magnetic and can be used
to adjust the balance what happened to be wrong assumption). Andre was
just plaing with it afterwards and was close to be late into the
kindergarten - the doors close there at 0900 sharp no exceptions.

Antti

 

[MM]

KDE is fine with me, however before starting any new group we should
probably make sure there is some substantial interest/support for this... I
personally am in a permanent board level design cycle which forces me to
switch from one tool/activity to another every 2-3 months... Right now I am
in my FPGA phase, but I might be out of it in a couple of months until next
time... So, unfortunately I can't be relied upon in organizing and
maintaining this kind of thing...


/Mikhail


"Chris Gammell" <Chris.Gammell@gmail.com> wrote in message
news:1140021323.752139.284100@o13g2000cwo.googlegroups.com...

Well, we could always start a user group on google. However, I would
predict within the hour there would be a Xilinx FAE trying to sell us
on some new product. Perhaps we could call it something tricky like KDE?

 

[Peter Alfke]

Chris Gammell wrote:

Well, we could always start a user group on google. However, I would
predict within the hour there would be a Xilinx FAE trying to sell us
on some new product. Perhaps we could call it something tricky like KDE?

Chris, do you have any proof for that (insulting) statement?
I think this ng tries to be informative and helpful, and keeps
commercials to a bare minimum.
If you advocate the absence of Xilinx and Altera voices, I hope you are
alone.
Peter Alfke

 

[Symon]

"Brian Davis" <brimdavis@aol.com> wrote in message
news:1140059573.932785.146270@g44g2000cwa.googlegroups.com...

Following up on John Providenza's question about the DIFF_OUT
buffer feature, I've put together a small example which builds a
complementary clock input buffer out of two normal IBUFGDS's.

Also for reference, I've copied my original notes about this handy
feature of the V2 & S3 families.

Brian

Hi Brian,

I'm struggling a little to see why I'd require a complementary clock. The
DDR output IOBs have inversion control on both clock inputs, so why not just
connect the normal clock to both pins and invert the appropriate one? Are
you saying that a local inversion affects the skew? I have seen big clock
nets' mark/space get affected by a lot of loads, is this the problem you're
addressing? IFAIK, all the clocked resources have programmable inversion so
what am I missing?
Cheers, Syms.

 

[Tim]

Symon wrote

I'm struggling a little to see why I'd require a complementary clock. The
DDR output IOBs have inversion control on both clock inputs, so why not
just connect the normal clock to both pins and invert the appropriate one?
Are you saying that a local inversion affects the skew?

from XAPP462, page 37:

The CLKx clock signal precisely triggers the DDR flip-flop's C0 input at the
start of the clock period. Similarly, the CLKx180 clock signal precisely
triggers the DDR flip-flop's C1 input halfway through the clock period. The
cost of this approach is an additional global buffer and global clock line,
but it potentially reduces the potential duty-cycle distortion by
approximately 300 ps..

 

[Symon]

"Tim" <tim@rockylogiccom.noooospam.com> wrote in message
news:dt1sdk$pll$1$8300dec7@news.demon.co.uk...

from XAPP462, page 37:

The CLKx clock signal precisely triggers the DDR flip-flop's C0 input at
the start of the clock period. Similarly, the CLKx180 clock signal
precisely triggers the DDR flip-flop's C1 input halfway through the clock
period. The cost of this approach is an additional global buffer and
global clock line, but it potentially reduces the potential duty-cycle
distortion by approximately 300 ps..

Hi Tim,

OK, I guess that's why I've not had problems with using just one clock. Even
at >600Mbps I've got enough slack in my timing budget to cope with 300ps.
Thanks for the reference!
Cheers, Syms.

 

[Jude Wu]

Dear MIrgorodsky:
After many experiments, I think the back-annotation command will copy
the pin/LE/memory/PLL placements into the .qsf file as the location
assignments, so after that you can see many location assignments in the
Assignment Editor. Then if you re-compile the project, the location
constraints will work and the Placement result will be the same.

For Incremental Compilation, the pro-fitting or pro-synthesis netlist will
be kept so there is no need to back-annotate the assignments. But you can
still use back-annotation with LogicLock feature, because LogicLock feature
can not preserve the netlist or Fitting result.

Regards,




<v_mirgorodsky@yahoo.com>
??????:1140002958.853166.259940@o13g2000cwo.googlegroups.com...

I think I have sufficient knowledge in English, but still had troubles
understanding what back-annotation is used for in Quartus II software.
I have an assumption, that feature is designed to allow designer to
compile certain piece of project the same way many times, even if you
add some more functionality to the project.

Let's say, you created a module with very tight margins on setup/hold
timings, frequencies, etc. Adding more functionality will definitely
change the layout of the whole chip and may affect your critical block
timings. To protect your critical part of design you may create a
back-annotation file, which will guide Quartus II about exact way how
to layout the module to achieve the same performance during next
builds.

During my experiments I failed to get it work properly. Maybe I don't
know how to read, or Quartus II help system omits some critical
rules/restrictions. Don't understand the difference between this
feature and LogicLock feature. For me, both are doing the same.

To Alan Myler: always hate people, who respond your way to the
questions in the news-group. If you don't have to say anything about
the topic, just ignore the post. You don't have to respond in the
group if you don't like the question, neither obligated offend
original poster.

With best regards,
Vladimir S. MIrgorodsky

Alan Myler wrote:
Try using the Help menu, select index, search for back annotation.

Hope that gets you going in the right direction.

Alan


Sophie Liu wrote:

Hi, Dears:

I am using QuartusII now. I am not clear to back-annotate. What is
back_annotate? and what's the use of back-annotate?

Thank you!



Jude

 

[Brian Davis]

Tim wrote:

from XAPP462, page 37:
snip
The cost of this approach is an additional global buffer and global
clock line, but it potentially reduces the potential duty-cycle distortion
by approximately 300 ps..

Thanks for pointing out that link.

One caution on XAPP462 v1.1 : the novice at Xilinx who wrote the
"Skew Adjustment" section (pp 32-34) got the descriptions and figures
completely backwards, and confused the terms 'skew' and 'delay'.

Pages 4-5 of XAPP259 give a much better description of the delay
element.

------

DESKEW_ADJUST = SYSTEM_SYNCHRONOUS :

Inserts a delay into the DCM FEEDBACK path, which makes the
output clock happen EARLIER. ( not later, as depicted in XAPP462 )

This increases setup, guarantees zero hold, and adds a temp
and VCCAUX affected delay element into the DCM deskew path.

DESKEW_ADJUST = SOURCE_SYNCHRONOUS :

Removes delay element from the DCM FEEDBACK path, which makes
the output clock happen LATER. ( not earlier, as depicted in XAPP462 )

This reduces setup time, increases hold time, but results in a
smaller overall input sampling window.

------

For DDR input applications, or for cascaded DCM's, you generally
want to be in SOURCE_SYNCHRONOUS mode (the latest few
revisions may do that automatically for DCM cascades)

See also Answer Records 12406, 18079

Brian

 

[Chris Gammell]

Hey Peter,

While I agree that the Xilinx and Altera peeps that lurk on these
boards with us are helpful, I was more referring to their companies,
with constant updates and poorly tested releases. I think the FAEs and
such who explain all of these downfalls to us are just as much a victim
to the problem as the rest of us.

But hey, I'm just a dumb kid trying to make my way. I'll muddle through
the EDK regardless. Why? Because I have to.

See ya.

Chris

 

[Gabor]

mughat wrote:

I have a problem width my CPLD-SPI_flash configuration system.

I have made a configuration interface for my Spartan 3 FPGA involving a CPLD
(CoolRunner 2) and SPI flash (M25P32).

My FPGA is set up to serial master configuration mode. The FPGA is
generating the clock for the CPLD and the CPLD transfers the data from the
SPI flash to the DIN pin on the FPGA. I use the application notes and source
code xapp800 from Xilinx.

I monitor the CPLD and it steps through states (1-4):
1 STATE_RESET
2 LOAD_READ_OPCODE
3 LOAD_READ_ADDRESS
4 READ_DATA
5 WAIT_STATE

The CPLD stays in state 4 where it waits for the FPGA to indicate
configuration done by pulling the DONE pin high.

The hardware seams to work. I can see the data on the DIN pin of the FPGA
but the FPGA never indicates configuration done by pulling the DONE pin
high.

I think the problem may be the process of converting the .bit file to a
format that can be written to the serial flash.

Anyone that have any suggestions on how to find the problem?

The first thing I always check is the bit order within bytes. Make
sure the SPI isn't swapping your bits, or try swapping bits when you
create the SPI flash image.

Andreas Beier
Computer Systems Engineer

 

[Peter Alfke]

Markus, I do not know much about Stratix PLLs ;-)
But the traditional way to implement your function is called Direct
Digital Synthesis (DDS) aka Phase Accumulation.
You build a long ( 34 bit?) accumulator and clock it at your 100 MHz
(200 MHz would be better). The MSB is your output, and it easily has
the requested frequency resolution. It also has a max jitter of one
clock period (10 ns or 5 ns). If that is too much, you can use the PLL
to reduce it.
That's what I would do. Since the PLL's filter does not cover 0.01 Hz,
you will have some frequency wander, but that is unavoidable in your
case.
If anybody knows a trick to avoid it or reduce it, I am all ears...
Peter Alfke, Xilinx

 

Have you tried DSP with FPGA by Meyer. That gives a good introduction
in VHDL DSP design.

Paul

 

[Gabor]

I don't usually use the .bit file directly. I use Impact to generate a
PROM file in HEX format (or use promgen if you prefer a command
line interface). This is a very simple format with just the bitstream
and no header. Then I use a simple C program to turn this back
into binary for storage in flash.

Impact or promgen gives you the choice of swapped or not swapped
bits when generating the .hex file. Then if your embedded firmware
gets the bit order wrong, you can just re-build the .hex file using
the opposite swap mode rather than changing the firmware.

A note of warning. Impact 8.1i sp1 (and maybe sp2?) GUI always
sets the swap bits mode when generating .hex files, so you need
to run promgen from the command line to generate unswapped
..hex files.

mughat wrote:

Do you use any special software tools for reading the .bit file and flash
image?

"Gabor" <gabor@alacron.com> wrote in message
news:1140108297.431410.245210@z14g2000cwz.googlegroups.com...

mughat wrote:
I have a problem width my CPLD-SPI_flash configuration system.

I have made a configuration interface for my Spartan 3 FPGA involving a
CPLD
(CoolRunner 2) and SPI flash (M25P32).

My FPGA is set up to serial master configuration mode. The FPGA is
generating the clock for the CPLD and the CPLD transfers the data from
the
SPI flash to the DIN pin on the FPGA. I use the application notes and
source
code xapp800 from Xilinx.

I monitor the CPLD and it steps through states (1-4):
1 STATE_RESET
2 LOAD_READ_OPCODE
3 LOAD_READ_ADDRESS
4 READ_DATA
5 WAIT_STATE

The CPLD stays in state 4 where it waits for the FPGA to indicate
configuration done by pulling the DONE pin high.

The hardware seams to work. I can see the data on the DIN pin of the FPGA
but the FPGA never indicates configuration done by pulling the DONE pin
high.

I think the problem may be the process of converting the .bit file to a
format that can be written to the serial flash.

Anyone that have any suggestions on how to find the problem?

The first thing I always check is the bit order within bytes. Make
sure the SPI isn't swapping your bits, or try swapping bits when you
create the SPI flash image.


Andreas Beier
Computer Systems Engineer

 

[Antti Lukats]

"Antti" <Antti.Lukats@xilant.com> schrieb im Newsbeitrag
news:1140004004.835579.16060@g47g2000cwa.googlegroups.com...

News from Embedded World News, Nurnberg 14.02.2006

some fixes updates to my onw posting

Lattice
=======

ECP2 pricing is 50% of ECP, so smallest ECP2
has an pricetag of 3 USD. Smallest members
of ECP2 family are however last on the roadmap
the first member to be available is the largest
ECP2-70 with smallest ones following.

fix: ECP2-50 is first device, ECP2-12 follows
with all members expected to be sampling in Q2

SiLabs
======
5) CP2201 Evalution Kit, no info ??? what is it?

CP2201 is Ethernet MAC+PHY, packaged in QFN28, TQFP32
2 different parallel interfaces, will be officially launched on March 6th.

Xilinx
======
To have a rest I did sit down for a live

[snip]

if my commentary about Xilinx presentation has been qualified as
funny in bad sense, well I have been a REAL PAIN IN THE ASS
all my life at all presentations. The few small errors the Xilinx speaker
did during the presentation, well we all do mistakes. And as I said
I was never been good at simple math, and have done mistakes
a la 1 + 1 = 2 in the math class, so the 3 x 17 error at the
Xilinx presentation I should not have pushed onto it.

That I did not find anything new for me at the Xilinx booth that is
also quite understandeable from simple reason that I already did
know everything, and there was nothing that Xilinx announced
specially at Embedded as some other companies did. It doesnt
mean that I did not find nice Xilinx products at other booths
the Zefant S3e modules are pretty cool, and PLDA had working
4 lane PCIe demo with FX60 to name a few.

Antti

 

[vssumesh]

Thank yo very much john for the replay.... I agree with your findings.
I wrote a program which converts individual bits to hex values....
Also there is no GUI to genrate vcd file in the model sim.

 

[Brian Drummond]

On Fri, 17 Feb 2006 19:14:31 -0500, "MM" <mbmsv@yahoo.com> wrote:

I am just guessing here. Are your constraints by any chance included in
between the following lines?

#PACE: Start of Constraints generated by PACE
.....
#PACE: End of Constraints generated by PACE

I would expect PACE to respect only whatever is outside of these lines...
But I don't really know how it works in practice...

/Mikhail

As of 6.1, the floorplanner certainly didn't respect area constraints.

At least it wouldn't preserve them in any UCF it wrote back out.
Maybe related, maybe not.

- Brian

 

[Luc]

Try opencores.com

this will work.

Regards,

Luc

On 16 Feb 2006 23:05:37 GMT,
pbdelete@spamnuke.ludd.luthdelete.se.invalid wrote:

Anyone know what happened to opencores.org ..?

The last trail is 2005-May.

 

[cwoodring]

In 7.1 I was editing the assigned pins. PACE would overwrite my existing UCF
file about half way through and basically made it useless. It would leave
out existing constraints and hack up others by breaking them in two. I think
it has a parsing issue with long lines or comments. I ended up copying my
original ucf file, going in to PACE to do the pin assignments I wanted to
add and then closed PACE. I'd then go and edit the ucf in the text editor
and add the lines from my original ucf file that got destroyed. Something
is definitely broken here?

Chuck

----- Original Message -----
From: "Roger" <enquiries@rwconcepts.co.uk>
Newsgroups: comp.arch.fpga
Sent: Friday, February 17, 2006 1:28 PM
Subject: Xilinx UCF area constraints disappearing

I have a design with an Aurora RocketIO core and in the UCF file I've
added the following lines:

INST Inst_rio0_top/Inst_rio0/lane_0_phase_align_i/phase_align_flops_r*
AREA_GROUP="PHASE_ALIGN_0_GRP";

# Place RIO0 lane_0_mgt_i at location X0Y1
INST Inst_rio0_top/Inst_rio0/lane_0_mgt_i LOC=GT_X0Y1;

AREA_GROUP "PHASE_ALIGN_0_GRP" RANGE=SLICE_X14Y152:SLICE_X15Y153;

When I use PACE to modify a pin assignment or something equally trivial
and save the UCF, the AREA_GROUP "PHASE_ ..........;" line has
disappeared. Although the Aurora core does still seem to work, I thought
that the placement of the phase alignment FFs was important and was
explicitly indicated for good reason. Can anyone tell me what's going on
here please? Even if there's some setting somewhere that's telling the PAR
to ignore this type of constraint, why does it disappear? Is it something
to do with the fact that except for the pin assignments, all the UCF file
has been added textually i.e. not via PACE or the Constraints Editor?

TIA,

Rog.

 

[Allan Herriman]

On Sat, 18 Feb 2006 06:23:28 -0600, "maxascent"
<maxascent@yahoo.co.uk> wrote:

The system I am designing is a pc scope. I guess I will know the trigger
point. What I dont really understand is how you can generate precise
offsets from the trigger if you want to sample in the GHz region as you
are talking about picosecond values. I guess I dont fully understand the
procedure

One solution for triggering is to have a fast, continuous time trigger
comparator start an analog ramp voltage (like in a monostable). This
ramp voltage is then digitised with an ADC similar to the ones
digitising the input voltages.

Inspecting the values of the digitised ramp voltage will allow you to
estimate the trigger point with respect to the sample instants.

The accuracy is limited by the comparator jitter, which might be as
low as some picoseconds.

Regards,
Allan

 

[Paul Hartke]

Since you are writing this from a University email address, I'll suggest
you contact the Xilinx University Program (XUP) at
http://www.xilinx.com/univ/ to inquire about a donation of the ISE
Simulator to your University.

They are usually quite generous.

Paul

Hendra wrote:

What is the price for ISE Simulator? There is no mention of it in
Xilinx Online Store. How does it compare to ModelSim Xilinx Edition
III?

Hendra