EDK : FSL macros defined by Xilinx are wrong

[Jim Granville]

Sky wrote:

Guys,
This is a long history. The project doesn't only include the EPLD, but also
many other expensive components.
Unfortunately the change will interest a lot of board already sold.
To change the PCB is certainly possible and I believe that this is the best
solution, but it is not acceptable for the marketing.

That's fine, they always ask for that

What you do then, is what Philips suggests, and create a carrier PCB,
that underneath/on edges looks like a TQFP144, and on the top,
has whatever package/device/psu fits.
Maybe a BGA MachXO, MAX II if the IO voltages will allow.

Then, give them the price for that option.
Nothing like some $$ to sharpen their focus

-jg

 

[John Adair]

Chaitu

The two biggest suppliers of FPGAs Xilinx and Altera both have free software
for their lower end device families Spartan and Cyclone respectively.
Spartan-3 and Cyclone2 are the latest. Between them they have something like
80-90% of the FPGA market so good to have experience of for finding jobs
after graduation.

If you are looking to add a chip to one of your own circuits then you will
want to look for a package that is easy to mount on a board. None of the
modern packages are an easy solder onto a circuit unless you have profession
kit especially BGA packages. If you just want to buy a board to use a number
of vendors including ourselves have low cost products for students. We even
have student based pricing under our UAP scheme.

John Adair
Enterpoint Ltd. - Home of Raggedstone1. The Low Cost Spartan-3 Development
Board.
http://www.enterpoint.co.uk


<chaitu11311@gmail.com> wrote in message
news:1139664844.963424.156820@g47g2000cwa.googlegroups.com...

hi, i am new to this field and studying my under graduate course on
FPGAs. to perform experiments practically i am planning to buy one
chip. so please suggest me which one among the available FPGAs suit me
so that i get in touch with it and also suggest me any softwares
available to interface the same with my pc.
thanks in advance
waiting for responce,
bye
chaitu

 

[Herman Dullink]

You also might want to look at the T-Rex C1 Development Kit
http://www.terasic.com.tw/english/fpga_01.htm
For starting, all it needs is an USB port (power via USB).

 

[Thomas Entner]

Hi Karel,

I cannot comment on Microblaze, but we do this with our ERIC5-processor
(also in S3E 250/500 design). For better performance, we use 1 BRAM as
cache, and the SPI-flash-interface is optimized for sequential accesses.
BTW: The ERIC5 needs much less resources than Microblaze, so maybe you could
get away with a S3E 250 (if every dollar counts ;-).

Regards,

Thomas

www.entner-electronics.com

"Dolphin" <Karel.Deprez@gemidis.be> schrieb im Newsbeitrag
news:eaydnWynH7c3IXXeRVn-rQ@giganews.com...

Hello,

I have the following system:
- A Spartan 3E 500 FPGA
- Some internal BRAM memory
- An external SPI flash

The external SPI flash contains the instruction code. However I can't use
a bootloader because the internal BRAM memory is not big enough for all
the code.
We don't use an external memory because price is important for this design
(every $ counts).

I would like to have the Microblaze fetching code from the SPI flash. The
problem is that I have to use the OPB SPI interface for this and this
interface is not a 'real' memory interface.

Has anyone had a similar problem? How did you solve it?

Thanks and best regards,
Karel

 

[Thomas Entner]

Oops, I hit the wrong button somewhere, here for the newsgroup:

I cannot comment on Microblaze, but we do this with our ERIC5-processor
(also in S3E 250/500 design). For better performance, we use 1 BRAM as
cache, and the SPI-flash-interface is optimized for sequential accesses.
BTW: The ERIC5 needs much less resources than Microblaze, so maybe you
could get away with a S3E 250 (if every dollar counts ;-).


What MHz can you stream from the SPI at, in sequential mode.
I see there are now ~70MHz SPI device.

I wonder when we'll see DDR SPI devices ?
They could do that with another read opcode..

-jg


I used 40 MHz in that project, I know of 50MHz devices, I think I have to
take a second look for the 70MHz ones ;-) The ERIC5 architecture has short
opcodes of 8 or 9 bits, this helps of course.

The 70Mhz one I spotted was here, at 8MBits. I think ST mentioned 66MHz
http://www.atmel.com/dyn/products/datasheets.asp?family_id=616

However, a change of flow always has a huge penalty because the complete
address (+ the dummy-byte for fast read-out) has to be transmitted.

Of course, but that could change the core design a little, or even the
SW Tools (or mindset) for creating the Code.
After all, with Serial Flash, the Code becomes dirt cheap, so you trade
off compactness, for blocks that fit the cache.

At 70MHz, you get close to 9MBytes/s of (linear) BUS bandwidth, which is
pretty good. Quite a few 8 bit uC are
around there...

On present trends, that speed could increase a little more - it is not
quite at FLASH access ceiling yet.
The smart thing to do, would be to (optionally) flip the HOLD pin, so it
can pause the FPGA streaming,
on page boundaries - that would get much more MHz out of the system

regards
Jim G.

 

[Antti]

I *might* be around on wednesday too, so just drop by at the same time,
if I am there Im there

Antti

 

[Uwe Bonnes]

Antti <Antti.Lukats@xilant.com> wrote:

this week Embedded in Nurnberg, Halle 12, Standnummer: 12-338 (TQC):

FPGA module with MicroBlaze uClinux on display, not much to see but
it has some MicroWindows demos loaded

Antti
PS I will be around that stand, hm 1500 on tuesday if someone wants to
say hello

What a pitty. I will be there wednesday...

--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

 

[siva.velusamy@gmail.com]

microblaze_nbwrite_datafsl = non blocking write
microblaze_bwrite_datafsl = blocking write

On a non-blocking write the processor sets the control bit if the fsl
bus is full. On a blocking write the processor waits until the FSL bus
has space. More details can be obtained from the documentation (look
for the put instruction and its variants).

/Siva
Xilinx, Inc.

 

[Hal Murray]

Lastly, I have noticed that simple designs seem to download more
reliably than larger designs. Not sure why, as the programming file
should be of equal length either way (though there may be a lot of zero
padding in the smaller files)

Have you tried a scope on the clock/data lines?

Is this the same byteblaster you used back when it worked?
A newer PC might be a bit faster or there might be just a bit
more crosstalk on the cable or ...


--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.

 

[Stephane]

Hi Bertrand,

did you have a look at the discussion "Xilinx legal" posted here by
Austin Leslea on 30.01.2006 ?
You won't be allowed to perform bitstream creation...

Stephane


Bertrand Rousseau wrote:

Hi everyone,

I'm trying to understand how the frame addresses have to be decoded for
a Virtex-4 FPGA from Xilinx. So far I could find documentation about
the configuration for VI and VII FPGAs, but there seem to be small
modifications between these models frame addresses and the new
Virtex-4.

Has anyone already tried to understand frame addresses in Virtex-4?

Thanks

Bertrand

 

[Bertrand Rousseau]

Damn! You're totally right. That's incredible I just couldn't see it!

Thanks a lot, I should read more carefully.

Bertrand

 

[Matt Clement]

sorry the title is not quite what i ended up asking.

matt


"Matt Clement" <clement@nanotechsys.com> wrote in message
news:0slIf.3561$Lr.3543@trnddc01...

Hello

Is there a way to setup a bit to be tri-stated so that it can be on a bus
multiplexed with other signals and only becomes active low when being
driven low by the process? How can I setup the bit to be tri-stated or at
least handle it such that it never goes low (and pulls the whole bus low)
while not being driven by my CPLD??

Thanks
Matt

 

[GaLaKtIkUs™]

Strange! I didn't understand any thing. Perhaps is it because I have
influenza (Yesturday I had 40 degrees celcius) and I'm tired. Try to
use short sentences. Provide a small piece of code or example plz.
I also had another answer to you question when I read the title. But
after reading the core of your message I'm lost.

Mehdi

Matt Clement wrote:

Hello

Is there a way to setup a bit to be tri-stated so that it can be on a bus
multiplexed with other signals and only becomes active low when being driven
low by the process? How can I setup the bit to be tri-stated or at least
handle it such that it never goes low (and pulls the whole bus low) while
not being driven by my CPLD??

Thanks
Matt

 

[GaLaKtIkUs™]

Did you repartition your hard drive before reinstalling? if yes you are
lost.
If no, this means that you reinstalled windows in a different drive
than before. The starter license uses the serial ID of the partition on
which Windows is installed.
There are ways to change the serial ID of a partition using disk
utilities (like partition magic for example).
Mehdi

Sonali wrote:

I am using xilinx Tool Ver 6.3.
And Modelsim 5.8.
Due to some reasons I uninstalled modelsim.
After I installed it again I faced a problem related to license .
ModelSim is installed. and While running it asks for license.

At licensing Wizard of ModelSim,
I choose a license file which was there previously( we kept a copy of
license file before uninstalling).

but gives following error msg:
---------------------------------------------------------------
Driver/Hostid is correctly configured.

License HostID detection report:

ERROR : The hostid type -Disk Serial Number- was referenced in the
license file
but does not match the value found on this machine.
-the license file value for Disk Serial Number is: e0ee2059
-the actual value for Disk Serial Number is: 200e5645
---------------- and -----------------
XE Starter simulator license (xe-starter)
The hostid of the license does not match the hostid for this machine.
One of the following is likely:
-The license is intended for another machine.
-A dongle is not plugged into this machine.
-The dongle driver is not installed or is not functioning properly.
-The hostid mechanism has been changed or removed from this machine.
---------------------------------------------------------------

So I go for submit license request where they ask for Disk serial no.
There is a warning that one mistake in serial no. cost u $395 for
re-licensing.
I didn't know what is disk serial no. for Full VHDL.

I also have a latest copy of ModelSim where also i have to go for
licensing Wizard.

What is the way to come out from this?

"Is there any other Simulation tool which is free downloadable and
compatible with Xilinx 6.3 Tool ?"

Regards,
Sonali

 

[Kolja Sulimma]

Sonali schrieb:

---------------------------------------------------------------
Driver/Hostid is correctly configured.

License HostID detection report:

ERROR : The hostid type -Disk Serial Number- was referenced in the
license file
but does not match the value found on this machine.
-the license file value for Disk Serial Number is: e0ee2059
-the actual value for Disk Serial Number is: 200e5645

Change the volume ID back using this tool:
http://www.sysinternals.com/Utilities/VolumeId.html

This reminds me of a great phone conversation with an Insight Memec
representative who refused to register 20 licenses of FPGA Express to
volume ID 1111-1111. (We used to use volume ID 0000-0000 for all our
drives, but a bug in FlexLM prohibits that)
We ended up registering only a single license, used that on all machines
and kept the other licenses unregistered.

Stupid.

Kolja Sulimma

 

[radarman]

Hal Murray wrote:

Lastly, I have noticed that simple designs seem to download more
reliably than larger designs. Not sure why, as the programming file
should be of equal length either way (though there may be a lot of zero
padding in the smaller files)

Have you tried a scope on the clock/data lines?

Is this the same byteblaster you used back when it worked?
A newer PC might be a bit faster or there might be just a bit
more crosstalk on the cable or ...

Unfortunately, the project that the board was originally used for has
long since ended. The PC was leased, and has since been returned, and I
have no idea where the byteblaster we used then went.

That does remind me, though - we originally had a Byteblaster II, not a
Byteblaster MV. The original byteblaster used a slower '244 - LS family
I think. That *shouldn't* be a problem, but I can try swapping the
chip.

I will try looking at the signals on a scope. I'm kind of flying blind
without a scope at home, but I can take it to work and check out the
signals.

 

[Aurelian Lazarut]

radarman wrote:

Check the data sheet for your part. Some parts will allow for true
*internal* tri-states, while others do not. For example, a Xilinx 4000
series FPGA will do true internal tristates, while neither the Virtex
nor Spartan series FPGA will not.
Actually they do have.

Spartan2 spartan2E virtex and virtexE they all have BUFT (or TBUFS)

parts without BUFTs: virtex2/pro virtex4 spartan3/3E

Aurash

For parts that do support it, you will need to add a line like this
(for VHDL):

TSTATE_BUS <= My_bits when Enable = '1' else (others => 'Z');

Note, you can still do this even in later families, but the compiler
will turn it into a mux - so be careful. If you aren't aware of that
behavior, you can be surprised on large designs with low LUT margins.

Note, I have seen some IP cores that use an 'OR'ed bus structure to
solve this problem. With an OR type bus, you just drive zeros when not
enabled:

arcitecture rtl of sample is

-- To simplify the OR logic, make these the same width. Your
compiler/synthesizer should optimize away bits you don't need - while
still making the correct connections. Just load the registers you DON'T
need with a constant value.
signal My_Bus_1_d, My_Bus_1_q : std_logic_vector( BUS_WIDTH_MINUS_1
downto 0 );
signal My_Bus_2_d, My_Bus_2_q : std_logic_vector( BUS_WIDTH_MINUS_1
downto 0 );

-- Don't worry too much about the My_Data_n busses - you can pad the
bus when you feed it to My_Bus_n_d;
signal My_Data_1 : std_logic_vector( 3 downto 0);
signal My_Data_2 : std_logic_vector( 15 downto 0);

begin

-- You need one of these per *readable* register/entity
My_Bus_1_d <= My_Data_1 when Enable_1 = '1' else (others => '0');
My_Bus_2_d <= My_Data_2 when Enable_2 = '1' else (others => '0');

-- To keep your combinational logic path to a minimum, register each
"My_Bus". This isn't necessary, and does add an additional clock of
latency, but if your timing is marginal, this will help.

S_Regs : process( Reset_n, Clock )
begin
if( Reset_n = '0' )then
My_Bus_1_q <= (others => '0');
My_Bus_2_q <= (others => '0');
elsif( rising_edge(Clock) )then
My_Bus_1_q <= My_Bus_1_d;
My_Bus_2_q <= My_Bus_2_d;
end if;
end process;

-- Then, you need _only_ one of these somewhere in the code to "mux"
the bus together.
for i in BUS_WIDTH_MINUS_1 to 0 loop
OR_BUS(i) <= My_Bus_1_q(i) or My_Bus_2_q(i);
end loop;

end rtl

This is fairly resource intensive, but it is fast, and explicit. To
improve performance, I would suggest registering My_Bus_n as shown -
unless your design has few readable registers - or you can tolerate the
long combinational paths. BTW - if you look closely, you will see that
this only handles the READ portion of your bus. Use a separate bus for
handling writes. Not only will this improve performance, since you
don't have to simulate bus turnaround, but you don't need any muxing at
all for a WRITE bus - just clock enables on the registers. Saves a lot
of grief in the long run.

Good luck!

 

[agi]

sir i wrote codings for capacitive sensor while compiling i got a fatal error like

Fatal: (vsim-3421) Value 1.#INF is out of range 1e+308 to -1e+308. # Time: 0 ns Iteration: 1 Process: /capasens_calc/line__137 File: C:/FPGAdv61/Modeltech/casens

sir how can i overcome this also i got the error in this line

fvoltage0:=(fcharge/fparacap1)*((a-fgamma)/fp);

this is my coding

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all;

entity capasens_calc is port(area: in real; dist:in real; charge:in real; paracap:in real; capacitance:inout real; gamma:in real; paracap1:in real; p:inout real; alpha:in integer; Vcharge: in real; Vthreshold:in real; gm:in real; voltage0:inout real; capaload:in real; Ts:inout real; voltageut real; voltage1: out real; outputut bit);

end capasens_calc;

architecture behavioral of capasens_calc is signal p1:real; signal p2:integer;

function capa_calc(signal farea:real;fdist:real) return real is constant Eo : real:=8.159; variable fcapacitance : real; begin fcapacitance:=(Eo*farea/fdist); return fcapacitance; end capa_calc;

function volt_calc(signal fcharge:real;fcapacitance:real;fparacap:real) return real is variable fvoltage:real; begin fvoltage:=(fcharge/(fcapacitance+fparacap)); return fvoltage; end volt_calc;



function saout_calc(signal fcharge:real;fparacap:real) return real is variable fvoltage1: real; begin fvoltage1:=(fcharge/fparacap); return fvoltage1; end saout_calc;

function p1_calc(signal fcapacitance:real;fparacap:real) return real is variable fp1:real; constant a :real:=1.0; begin fp1:=(a+(fcapacitance/fparacap)); return fp1; end p1_calc;

function p2_calc(signal falpha:integer) return integer is variable fp2:integer; constant a :integer:=1; begin fp2:=(falpha+a); return fp2; end p2_calc;

function p_calc(signal fp1:real;fp2:integer) return real is variable fp:real; begin fp:=fp1**fp2; return fp; end p_calc;

function charge_calc(signal fp:real;fgamma:real;fcharge:real;fparacap1:real) return real is variable fvoltage0:real; constant a :real:=1.0; begin fvoltage0:=(fcharge/fparacap1)*((a-fgamma)/fp); return fvoltage0; end charge_calc;



function schtrigger(signal fVcharge:real;fVthreshold:real;fgm:real;fvoltage0:real) return real is variable fTs:real; begin if(fVcharge>fVthreshold)then fTs:=(fVcharge*fVthreshold)/(fgm*fvoltage0); return fTs; else fTs:=0.0; return fTs; end if; end schtrigger;

function capasens_calc(signal fcapaload:real;fTs:in real) return bit is variable foutput:bit; begin if(fcapaload >=5.0) and (fTs <=5.0)then foutput:='1'; return foutput; else foutput:='0'; return foutput; end if; end capasens_calc;

begin capacitance<=capa_calc(area,dist); voltage<=volt_calc(charge,capacitance,paracap); voltage1<=saout_calc(charge,paracap); p1<=p1_calc(capacitance,paracap); p2<=p2_calc(alpha); p<=p_calc(p1,p2); voltage0<=charge_calc(p,gamma,charge,paracap1); Ts<=Schtrigger(Vcharge,Vthreshold,gm,voltage0); output<=capasens_calc(capaload,Ts); end behavioral;

 

[Alan Myler]

Try using the Help menu, select index, search for back annotation.

Hope that gets you going in the right direction.

Alan


Sophie Liu wrote:

Hi, Dears:

I am using QuartusII now. I am not clear to back-annotate. What is
back_annotate? and what's the use of back-annotate?

Thank you!



Jude

 

[Falk Brunner]

Antti schrieb:

PS my best gift item prize goes to perforce
http://www.perforce.com/
for a real balsa-wood model air-plane !
now having Andre (my 4 years old sun) as a pride owner

Your 4 years old s_u_n must be a bright kid, isn't it?

SCNR ;-)

Regards
Falk