EDK : FSL macros defined by Xilinx are wrong

Hi Antti,
Thnaks for your reply
I checked this excellent site : http://www.ulrichradig.de from Ulrich Radig

And there is there a video showing SMD IC soldering :
http://www.ulrichradig.de/gfx/video/SMD_einloeten.wmv

Some points are unclear for me t : what kind of glue does one put on the IC
pads at the beginning ?
And how does one put the solder ? directly as it seems from the video ?




"Antti Lukats" <antti@openchip.org> wrote in message
news:dq3l31$oo8$1@online.de...
"Jerome" <nospam@nospam.fr> schrieb im Newsbeitrag
news:43c54fb6$0$11500$636a15ce@news.free.fr...
Hi Antti,
Do you use special tool(s) to solder a BGA pulled IC ?
Or only a magnifying glass ?

no tools and no magnfier either :)

1.27mm BGAs are pretty easy to handle, but it balls up
solder the GND at the corners then some VCCINT
and VCCAUX, the JTAG some IO pins and eval board
is ready ! I had some pictures of one such board online
sometimes ago but at the moment I cant find them

1mm BGAs are harder, and with 0.8mm is better not
to try it at all. I tried once to solder the PCI interface
pins of the TI's TMS6205 DSP in 0.8mm BGA and
there I failed, maybe was too impatient.

Antti
Click to expand...
 
Zara wrote:
BTW, someone from Xilinx told me some time ago that EDK 8.1 will, at
last!, support C++. I hope it will.
Click to expand...
C++ works for me in 6.3 and 7.1 What doesn't work?
I had to add extern "C" to a few header files. I don't use many C++
features, however.

Alan Nishioka
 
DerekSimmons@FrontierNet.net wrote:
Have you looked at Altera's HardCopy device? It allows you to migrate a
FPGA (Startix/Cyclone) design to a HardCopy device. It is suppose to
have some of the advantages of ASIC device (price was one of them).
Click to expand...
Stratix/Stratix II, rather. The HardCopy devices are definitely high
end. Definitely seems like a nice migration program, though.

-hpa
 
Christopher Cole schrieb:
I like the new Xilinx Webpack 8.1i interface under Linux, it works great.
I am running the Webpack under Gentoo Linux with a 2.6.14 kernel.
Click to expand...
AFAIK, the Win32 version of the Webpack contains Modelsim. Does the
Linux version contain it too?

Bye Tom
 
Hi
Just use level shifters between the PCI and FPGA .... Have made that my
slef and works fine ... Send me an email for schemtics

Regards,
p

Hello,

I have to design a board with a PCI interface which shall be compliant
with
a larg range of PCI versions !
3.3V 32bits / 33Mhz
5V 32bits / 33Mhz
3.3V 64 bits / 66 Mhz

The board should use V2P xilinx FPGA so what bothers me is the 3.3V and
5V
compliance.
Is there a simple solution to achieve this ?

Thanks.

Stéphane.
Click to expand...
 
Sean Durkin wrote:
[snip]
There's a configuration switch you can set to "Allow unmatched
LOC"-attributes which would allow you to finish the flow despite of the
error, but that's not what you want since obviously there's something
wrong with your design which you otherwise wouldn't notice.

cu,
Sean
Click to expand...
Actually this can be quite useful, since you'll have the reports that
follow the "translate" process. This can show you whether your clock
has actually been removed from the design or somehow got re-named
so it didn't match the LOC constraint. A look at the pad report can
show this problem.

Godd luck,
Gabor
 
Zara wrote:
On 11 Jan 2006 22:22:55 -0800, "Alan Nishioka" <alan@nishioka.com
wrote:

Zara wrote:
BTW, someone from Xilinx told me some time ago that EDK 8.1 will, at
last!, support C++. I hope it will.

C++ works for me in 6.3 and 7.1 What doesn't work?
I had to add extern "C" to a few header files. I don't use many C++
features, however.

Whenever I use templates, chaos begins...
Click to expand...
I see. Not something I use. I assumed that it would work since it is
gcc, but I guess more stuff needs to be ported.

Alan Nishioka
 
Hi Colin,

In the Assembler settings tab, select 'Always enable input
buffers' and recompile the design.

Hope this helps,
Subroto Datta
Altera Corp.
 
Hi Colin,

In the Assembler settings tab, select 'Always enable input
buffers' and recompile the design.

Hope this helps,
Subroto Datta
Altera Corp.
 
backhus wrote:
wuyi316904@gmail.com schrieb:
Hi,in my project,i need some bufs to delay some signals,but after
synthesising,the code:#20 does't have any affects.Is there some way to
keep the delay?For example,some constraint for synthesis or other.

Hi,
The verilog # operater and the vhdl after statement are not
synthesizable and (as you already observed) therefore ignored during
synthesis.

As mentioned before by cationebox, Flipflops/registres are a proper way
to delay signals by n clock periods (n = number of serialized ffs ).
Click to expand...
Probably worth mentioning DCMs/PLLs as well here - these allow you to do
fine phase shifting on a clock, which can then be used (assuming clock
domain boundaries are crossed correctly) to clock flip-flops with
different timings than your original clock.

Jeremy
 
Thomas Reinemann <Thomas.Reinemann@masch-bau.uni-magdeburg.de> writes:
AFAIK, the Win32 version of the Webpack contains Modelsim.
Click to expand...
No, it's a separate download.

Does the Linux version contain it too?
Click to expand...
The Xilinx edition is only available for Windows.

AFAIK Webpack includes ISE Simulator on both Windows and Linux.
 
Hi Ludwig,

Have you considered using two XUPV2Ps each with its own VDEC1 board?
The VDEC data from one board could be sent to the other over a SATA
cable connected between the boards. The "Using High Speed Serial MGTs
with the Aurora IP" Quickstart at http://www.xilinx.com/univ/xupv2p.html
is a good example to start with.

Paul

Ludwig Lenz wrote:
Hello,

I want to use a second Digilent VDEC videodevice at one time with another on
the Vertex II Pro Developmentsystem board. Because this board has only one
highspeed Digilent Connector (J37), I need to construct an adapter for the
lowspeed Connector (J5 - J6).

Does someone know, where I can get an Hirose FX2 connector (in
germany/europe)? Can I use J5 - J6 with the signal-clock, which is
necessary for a Digilent VDEC videodevice (54MHz)?

Thanks,
Ludwig
Click to expand...
 
On Fri, 13 Jan 2006 09:29:24 +1300, Jeremy Stringer <jeremy@_NO_MORE_SPAM_endace.com> wrote:

backhus wrote:
wuyi316904@gmail.com schrieb:
Hi,in my project,i need some bufs to delay some signals,but after
synthesising,the code:#20 does't have any affects.Is there some way to
keep the delay?For example,some constraint for synthesis or other.

Hi,
The verilog # operater and the vhdl after statement are not
synthesizable and (as you already observed) therefore ignored during
synthesis.

As mentioned before by cationebox, Flipflops/registres are a proper way
to delay signals by n clock periods (n = number of serialized ffs ).

Probably worth mentioning DCMs/PLLs as well here - these allow you to do
fine phase shifting on a clock, which can then be used (assuming clock
domain boundaries are crossed correctly) to clock flip-flops with
different timings than your original clock.

Jeremy
Click to expand...
SRL16s are also good for adding easily selectable delays to signals.
 
On Sat, 07 Jan 2006 08:51:49 -0800, "Mike Treseler"
<mike_treseler@comcast.net> wrote:

John Larkin wrote:

I don't have time to learn an HDL. I read the Xilinx book, draw
schematics (on paper!), and hand them to a minion to enter and
compile.

Ah! The academic solution.
Where have all the minions gone?
Long time passing ...
Click to expand...
When will they ever learn,

When will they ever learn?


John
 
Thanks for all of you,the device what i programme is SPARTAN 2,and i
can't use more clock for delay flip_flop,is there other way for this
problem?
 
Thank for ur suggests,Is there independent Impact for download and what
the Impact version u used?
 
wuyi316904@gmail.com wrote:
Hi,I have a problem that i can't use ISE4.2 download design in CPLD or
FPGA with win2000 SP4 system.The iMPACT of ISE4.2 accessories can't
find the download cable.I think this is the software problem,because
with ISE6.2 all is OK.What is the solution of confict between ISE4.2
and win2000 SP4.
Click to expand...
If ISE6.2 works, why do you need to use 4.2?
I can understand the need to compile with an earlier version, but why
do you need to download with an earlier version?

Alan Nishioka
 
wuyi316904@gmail.com wrote:
Thanks for all of you,the device what i programme is SPARTAN 2,and i
can't use more clock for delay flip_flop,is there other way for this
problem?
Click to expand...
There are other ways - some nasty, some not too bad. What are you
trying to do?

Jeremy
 
Hi -

If the system you're designing is a one-off, there's no harm in trying
various things to see what works. But if you plan to make multiple
copies of this design, there's no substitute for timing analysis. And
you don't need fancy tools: use Excel if you have it, paper and pencil
if you don't.

Without the timing analysis, it's just guessing.

Bob Perlman
Cambrian Design Works

On Wed, 11 Jan 2006 07:42:47 -0600, "Pouria" <pouria@hotmail.com>
wrote:

HI Everybody!

I'm having a timing problem interfacing with my SDRAM bank. I'm using
256Mb MT48LC16M16 SDRAM from Micron, and want to operate them at 100 Mhz.
So far I have only been working at 40 Mhz.

I'm using two DLLs (inside my VirtexII) one for clocking the FPGA and one
for clocking the SDRAM. The design works if I DON'T use the external
feedback from SDRAM_Clk to one of the DLL, but it fails as soon as I use
the feedback (Which according to Xilinx should be the correct way to
terminate clock Skew).

The feedback to the other DLL is taken from clock output of it self, and I
have used IBUG/OBUF/BUFG so that is not the problem.

Hope some one can help me .
Best regards,
/P
Click to expand...
 
Thanks for saving me a lot of time. Allthough putting it right is going
to take lots more!

Unfortunately the firmware has been formerly released by a third party
in the US and I have to prepare it for volume manufacture in the far
east and I work in the UK.

I will go and check, but I think that all the "errors" were stuck at
ones. Is the result that should be expected?

Allthough you have saved me some considerable time could you tell me
where the designer should have found this info. If it's very obvious
then I will have a quiet word with him. If it's not in a very obvious
place (and I have spent longer than I feel I should have looking) then
perhaps you could have a quiet word with your technical authors.

Regards

Colin
 
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