EDK : FSL macros defined by Xilinx are wrong

wuyi316904@gmail.com wrote:
Thank for ur suggests,Is there independent Impact for download and what
the Impact version u used?

Release version 4.2i
Click to expand...
Application version E.35

I don't recall exactly where it came from: possibly one of the Xilinx
FAE's on this group can help?
 
Ycan create small delays on signals by passing the signal through a LUT
configured to act as a buffer. Here it is in VHDL

LUT_DELAY: LUT1
generic map(
INIT => X"10")

port map(
O => signal_in_delayed,
I0 => signal_in);


<wuyi316904@gmail.com> wrote in message
news:1137053886.979267.61360@g14g2000cwa.googlegroups.com...
Hi,in my project,i need some bufs to delay some signals,but after
synthesising,the code:#20 does't have any affects.Is there some way to
keep the delay?For example,some constraint for synthesis or other.
Click to expand...
 
I have solve this problem,the most important is a system file named
windrvr.sys.When this file version is 6.03,the impact doesn't work
correctly in win2000 sp4,but the version is 5.05,all is ok.
 
Brad,

It works fine with instantiated RAMB16 primitives instead of coregen.
The Virtex4 primitives are a little easier to use than the old Virtex2
memory primitives because with the V4 ones, it is one primitive for all
aspect ratios. Well at least for a parameterized component where the
memory depth is dependent on generic parameters. I vaguely recall there
being an issue with the coregen memory generator for V4, but I'll be
darned if I can find it now. I generally do not use coregen because of
a combination of less than stellar experience with it, an accumulated
library of equivalent functions, and no visibility into what it is doing
or more importantly the lack of hooks to make minor changes to fit a
particular application better.

Anyway, try using a generate statement to instantiate the RAMB16
primitives and you should be fine. This is a fairly simple macro to
write, and one that you will undoubtedly use quite a bit going forward.


Austin,
See that's the trouble with the current Xilinx handling of issues like
this. Yeah, you publish solutions but unless you know exactly what you
are looking for and know that there is an issue you are very unlikely to
find it. I looked at the three answer records you posted, and I don't
believe any of them address his situation. Answer 22029 is a non-answer
that is specific to NCSIM. Brad specifically stated he is using
Modelsim. Answer 21848 is a release note for the fifo coregen, which I
don't think applies to Brad's question (and certainly doesn't address
the more serious issues with the FIFO16 primitive). Answer 19959 is
installation instructions and release notes for ISE 6.3i, again, not all
that relevant as far as I can see. I'm sure there is probably something
more relevant in the Answers database, but without the exact magic
incantation to get to it, it will likely lie buried for eternity. While
the answers data base is a good idea, it is badly crippled by poor
organization and a picky search engine that more often than not only
finds irrelevant stuff. The answers data base is certainly not the
whole answer either, and is an area that Xilinx very much needs to improve.

Austin Lesea wrote:
Brad,

Answer Record # 22029: LogiCORE Dual Port Block Memory v6.3 - Mismatch
on both DOUTA and DOUTB for the DPBLKMEM for V-4 using NCSIM
... dual, port, block memory, block RAM, BRAM, ramb16, dp ... blkmem,
dout, douta, doutb,
ncsim, simulation, timing issue ... Memory v6.3, targeting the Virtex-4
family and ...
- 24k - Cached

Answer Record # 21848: LogiCORE FIFO Generator v2.2 - Release Notes and
Known Issues for FIFO Generator Core
... asynchronous, synchronous, common, clocks, memory, BRAM, RAMB16,
FIFO16 ... When using
Virtex-4 FIFO16 type ... recommended that you use Structural simulation
model. ...
- 26k - Cached

Answer Record # 19959: 6.3i Install - ISE Service Pack 3 Release
Notes/README
... 19853) (SP1) 6.3i NetGen, Timing Simulation - Simulator errors ...
II PAR - Placer check
rejects valid 512x36 BRAM vs ... Answer 19922) (SP1) 6.3i Virtex-4 PAR -
Router ...
- 51k - Cached

Did you check these three tech answers? using
http://www.xilinx.com/support/library.htm

It isn't the best way to communicate, but it does exist, and we are
diligent about reporting and updating stuff...

Perhaps someone else can comment as well.

Austin
Click to expand...
 
steven wrote:

Ycan create small delays on signals by passing the signal through a LUT
configured to act as a buffer. Here it is in VHDL

LUT_DELAY: LUT1
generic map(
INIT => X"10")

port map(
O => signal_in_delayed,
I0 => signal_in);




This is a very small delay, maybe about 1 ns on Spartan 2. One way
Click to expand...
I have used to make a much longer delay on a 95xx CPLD that had no
continuous clock was to pass the signal out an output pin and back into
a different input pin. I put a resistor (about 1.5 K Ohm, in that case,
for about 20 nS of delay) between the two pins. This, of course, eats
up two whole pins for one delay. I needed to make something happen
a safe delay after an I/O strobe went away, and this did the trick. Of
course, where a fast clock is available, there are much more reliable and
predictable ways to do this.

Jon
 
Brad, it is your addressing. For the wider data widths, the lsbs of the
address should be held at zero. You should use bits 14 downto whatever
is appropriate for the aspect ratio you are using (in your case the 36
bit should leave the 5 lsbs '0').



Brad Smallridge wrote:

Thanks for words of encouragement Ray.

I went back to double check if all the simulation
and libraries were downloaded and installed. It
seems as if they are. All from the download page
that Xilinx is advertising on the home page right
now for the 8.i software. Three packages in all,
the ISE, ModelSim III, and it's library.

I am still not getting any output from the RAMB16
p
Click to expand...
 
Tobias Weingartner schrieb:
No, I'm not talking which pins to toggle how fast and when, but is
there any 600K+ gate (roughly) FPGA available which also gives the
layout and programming information for their bitstreams/etc?
Click to expand...
Xilinx has JBits. It does not give you the bitstream information but it
allows you to quickly modify details of a bitstream on the fly.

Think of it as controlling the FPGA editor by a Java programm.


Kolja Sulimma
 
Subhasri,
you should of course always design according to the worst-case rules.
But you should also know what's behind them.
The refresh rate is dictated by the leakage current that might drain
enough charge away from (or add charge to) a storage capacitor to make
the stored bit invalid. The longer you wait, the more there is a chance
to have a bit (or many bits) flip.
But leakage current is a strong function of temperature. At a
temperature below the specified worst-case number (is that 70 or 85
degrees C?) it will take longer to flip a bit. Leakage current doubles
for every 10 degrees. That means, at 10 degrees lower temperature, you
can, most likely, double the time between refreshes. But nothing is
guaranteed...

I do not advocate sloppy design, but it helps to know "the enemy".
Peter Alfke, Xilinx, from home.
===================================
Subhasri krishnan wrote:
Hi all,
There is a situtation in my controller when tRAS(max) is exceeded. My
controller starts to read out from some row but I am not sure exactly
which one. Does anyone know what row will be opened under this
situation?
Thanks
Subhasri.K
Click to expand...
 
"bjzhangwn" <bjzhangwn@126.com> wrote in message
news:1137423677.818816.281490@g43g2000cwa.googlegroups.com...
I want to implement an ata controller in the fpga,the controller use
the ultra dma mode to read and write datas,and I want to know if it is
difficult to implement it.Can some one give me some advice.

I advise you to put the subject of your post into a search engine, perhaps
Click to expand...
Google would be a good start, and see where that takes you.
Also :- http://groups.google.com/groups?as_q=ata+controller+fpga
I hope Google works in China?
HTH, Syms.
 
Antti Lukats wrote:
"qtommy" <qingwang_1978@hotmail.com> schrieb im Newsbeitrag
news:O-SdnWCndoFhB1beRVn_vQ@giganews.com...
Dear all,

This may sound stupid to ask, but I am very frustrating now as my
deadline is approaching. I want to make use of the VGA generator
example on www.xess.com. How could I write/read data to the specific
address of the SRAM?
I would have to have a SRAM controller that writes and reads data to
the SRAM? How should that be implemented in VHDL? What else do I
need? I am planning to hard code the data to SRAM. Thank you very
much!!!


HI, I just also do the same work. I have the same problem. And have you
resolve the problem? I would like to discuss it with you! Hier is my email
address: qingwang_1978@hotmail.com.



The xess demo only reads from the SDRAM, for write access you need to make
some statemachine based arbiter that will allow write access the SDRAM,
there is no demo for that unfortunatly, I did a quick dirty thing once it
only wrote a small image from camera in the SDRAM
Click to expand...
Actually, this is no longer true. We have a new VGA generator
application that allows the image data to be updated in the SDRAM while
the VGA generator is operating
(http://www.xess.com/appnotes/an-103005-vgagen.html). This is done
using a dual-port module that fits onto our SDRAM controller and allows
you to have multiple, independent channels in and out of the external
SDRAM.

--
Antti Lukats
http://www.xilant.com
Click to expand...
 
<devb@xess.com> schrieb im Newsbeitrag
news:1137427117.144265.241180@o13g2000cwo.googlegroups.com...
Antti Lukats wrote:
"qtommy" <qingwang_1978@hotmail.com> schrieb im Newsbeitrag
news:O-SdnWCndoFhB1beRVn_vQ@giganews.com...
Dear all,

This may sound stupid to ask, but I am very frustrating now as my
deadline is approaching. I want to make use of the VGA generator
example on www.xess.com. How could I write/read data to the specific
address of the SRAM?
I would have to have a SRAM controller that writes and reads data to
the SRAM? How should that be implemented in VHDL? What else do I
need? I am planning to hard code the data to SRAM. Thank you very
much!!!


HI, I just also do the same work. I have the same problem. And have you
resolve the problem? I would like to discuss it with you! Hier is my
email
address: qingwang_1978@hotmail.com.



The xess demo only reads from the SDRAM, for write access you need to
make
some statemachine based arbiter that will allow write access the SDRAM,
there is no demo for that unfortunatly, I did a quick dirty thing once it
only wrote a small image from camera in the SDRAM

Actually, this is no longer true. We have a new VGA generator
application that allows the image data to be updated in the SDRAM while
the VGA generator is operating
(http://www.xess.com/appnotes/an-103005-vgagen.html). This is done
using a dual-port module that fits onto our SDRAM controller and allows
you to have multiple, independent channels in and out of the external
SDRAM.
Click to expand...
sorry, I did not know - it does pay off to look at XESS website from
time to time to get new stuff!!

independant channel support is really nice thing to have

Antti Lukats
http://www.xilant.com
Click to expand...
 
"Antonio Pasini" <removethis_pasini.a@tin.it> schrieb im Newsbeitrag
news:43cd66bc$0$1087$4fafbaef@reader1.news.tin.it...
I already saw the message from Antti about '|' char on German keyboard. So
I installed WebPack 8.1 with some trepidation...

Sadly, *seems* that on XP SP2 with Italian keyboards almost NO control key
works.

Can some other guy verify this ?

I cannot write '@', '#', '[', ']', '{', '}'.. Imagine write verilog
code! CTRL-F doesn't work, also...

It doesn't work even in "float mode". Tried on three different machines,
at work and at home. Machines used different keyboards, and different
levels of update of XP.

Probably someting very stupid is going on... otherwise, Webpack 8.1 editor
(even with SP1) is useless, for an Italian user.

If this it's real... really makes me think Xilinx should honestly
re-examine its internal development process.

I noticed also many other annoying little things:

- "Ctrl" keys doesn't work also: forget about Ctrl-F to find some text.
- In float mode, "Replace" IS in the Edit menu (but NO quick icon), and
Ctrl-H doesn't work
- In float mode, "Find" is IS NOT in the Edit menu (but IS present as an
icon), and Ctrl-F doesn't work.
- Menu windows are sloooooooow... before appearing, a black filled
rectangle appears, then text comes. This on all the machines I tried. Fast
machines.
- TAB sequence is screwed in the "New Source Wizard"... try writing a pin,
the press TAB to enter the following one... surprise! need to grab the
mouse.

All of this in the first ten minutes of playing. Very sad.

Sometimes I wonder if Xilinx developers really try to USE what they do, or
are they "just" using blind regression testing scripts in search of the
last 1% of performance.

Performance is important, yes, but first address the "mundane" tasks!

Xilinx, usually your support is really second to none. It's one of the
reasons I prefer Xilinx over the A guys.

Please release an hotfix.... do not ask us Italian guys to wait months for
the next service pack...

Meanwhile, back to 7.1SP4, waiting for the next 3 service packs for 8.1 to
reach an "honest" level... Sigh.
Click to expand...
Hi

after verifying the hot keys in 'flaot mode' I was a bit 'breathing' as it
is a workaround, until I tried the

|

in float mode - and that doesnt work in float mode either - so we can say it
is confirmed the ISE 8.1 built in editor is useless for non US keyboard
users :(

well I still use my notepad.exe trick to copy the | into clipboard when I
need it, but I guess others are defenetly not willing to use this kind of
workarounds

Antti
 
Xilinx CPLDs, Spartan-3 FPGAs, Platform Flash PROMs, development
boards, etc. are available directly from the Xilinx online store. The
online store may not always have the absolute lowest price for a given
device but it's generally similar.
http://www.xilinx.com/store

These same items, and much more, are available from the various Xilinx
Sales Partners.
http://www.xilinx.com/company/sales/ww_disti.htm
---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/-3E FPGAs
http://www.xilinx.com/spartan3e
---------------------------------
The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.
 
Steve Knapp (Xilinx Spartan-3 Generation FPGAs) wrote:
Xilinx CPLDs, Spartan-3 FPGAs, Platform Flash PROMs, development
boards, etc. are available directly from the Xilinx online store. The
online store may not always have the absolute lowest price for a given
device but it's generally similar.
http://www.xilinx.com/store
Click to expand...
...except, if you want the CR2 CPLDs, in either XC2C32A or XC2C64A sizes,
then they simply do not exist in the online store. 128 & 256 do show.

Is this a not-for-new-designs message ?

-jg
 
On Wed, 18 Jan 2006 09:08:43 +0100, "Antti Lukats"
<antti@openchip.org> wrote:

"Zara" <yozara@terra.es> schrieb im Newsbeitrag
news:39srs1pib0md5de88dnea8uds2gun9ba5i@4ax.com...
On Tue, 17 Jan 2006 23:00:54 +0100, "Antti Lukats"
antti@openchip.org> wrote:

"Antonio Pasini" <removethis_pasini.a@tin.it> schrieb im Newsbeitrag
news:43cd66bc$0$1087$4fafbaef@reader1.news.tin.it...
snip

Hi

after verifying the hot keys in 'flaot mode' I was a bit 'breathing' as it
is a workaround, until I tried the

|

in float mode - and that doesnt work in float mode either - so we can say
it
is confirmed the ISE 8.1 built in editor is useless for non US keyboard
users :(

well I still use my notepad.exe trick to copy the | into clipboard when I
need it, but I guess others are defenetly not willing to use this kind of
workarounds

Antti


I am using WebPack 8.1 with an Spanish keyboard, and have not found
yet any such problem (other problems, yes, but I have not rechecked
against SP1, so I will not disclose them).

Zara

lucky you!

the issues with the editor are the same SP1 or not, on my machine
the 'alternate ALT' key labelled
"Alt Gr"
does not work in ISE editor and as this key is used to make
|
then it makes difficulties
Click to expand...
Ok, yes you are right. Control combinations work, but Alt Gr don't, as
you say. The problem is I don't use | much, so I didn't notice it.

And I have just discovered a real nuisance/error: I have a "repository
project" (somewhre I have all cores designed for EDK, together with
thier test benches"): From the momet I added 15th VHDL module and 7th
VHDL Test bench, Check Syntax fails with nes Module without giving and
error identifying the lien of the error, and ModelSim is executed with
another different testbench from the last one added.

That much for new ISE's! Keeping up with Xilnx is a reall PITA.

Best regards,

Zara
 
On Wed, 18 Jan 2006 11:12:45 +0100, Johan Bernspĺng <xjohbex@xfoix.se>
wrote:

Zara wrote:
Isn't it still possible to define your own external (favorite) editor in
ISE as it was before? In 7.1 it was done in Edit/Preferences dialog.
That is, when double clicking on a file in the 'Sources in
Project:'-view the code was opened in your predefined editor. I've been
doing this for quite a long time since I never really liked the ISE
editor...

Another workaround could be to install the american keyboard layout
(which I'm using in my external editor since some common characters are
more accessable than on the swedish keyboard). A simple alt+left shift
in windows swaps the layout from your native one to the american one..

As for me I havn't installed ISE 8.1i yet since I'm waiting for EDK...


It is possible to define an external text editor...but it will not
work!. problems with file paths, I think.

Zara

Well, it works for me. I use, for instance, Crimson Editor. Thus I've
set the Editors preferences to Custom and the command line syntax to
cedt.exe $1. That opens any code file in my projects in that editor.
Click to expand...
I use (in 7.1) crimson editor, cedt $1 -l:$2.

But when I use it in 8.1, with files *outside* the main project path,
it fails, because the file name passed to editor is "project
path"\"file path"\"filename". File path is OK with a file in the same
folder as the project, because it is empty. On all other cases, file
path is an absolutte path,and the result is invalid, of the sort:

"c:\myproject\c:\myotherproject\musource.vhdl"

And I do like to use folders to classify information, I hate flat
"all-in-one-folder" projects.

Bets regards

Zara

PS: As soon as I have alittel time to do it, I intend to file a bug to
Xilinx. But time is scarce.
 
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