EDK : FSL macros defined by Xilinx are wrong

On Wed, 18 Jan 2006 10:34:45 +0100, Zara <yozara@terra.es> wrote:

<snip>

lucky you!

the issues with the editor are the same SP1 or not, on my machine
the 'alternate ALT' key labelled
"Alt Gr"
does not work in ISE editor and as this key is used to make
|
then it makes difficulties

Ok, yes you are right. Control combinations work, but Alt Gr don't, as
you say. The problem is I don't use | much, so I didn't notice it.

And I have just discovered a real nuisance/error: I have a "repository
project" (somewhre I have all cores designed for EDK, together with
thier test benches"): From the momet I added 15th VHDL module and 7th
VHDL Test bench, Check Syntax fails with nes Module without giving and
error identifying the lien of the error, and ModelSim is executed with
another different testbench from the last one added.

That much for new ISE's! Keeping up with Xilnx is a reall PITA.

Best regards,

Zara
Click to expand...
Murphy: As soon as I have coded a new FSM, I have needed | character.
Now I hate ISE 8.l1, too!

Zara
 
Hi,

Does anyone have a hint on how to get data2bram and coregen memory to
work together?

I have an SoC with some 32bit memory made up of four 8bit memories
generated with coregen, I've made a bmm file that defines the memory.
I can run data2bram with the bmm file and an .elf file and if I set the
output to verilog the init strings look resonable.
If I run the same bmm and .elf file on my bit file and use the updated
bit file to configure an FPGA DONE doesn't go high so I assume the bit
file is corrupt.

Is there a trick I should know about ?

data2bram does give me a warning the the memory is not LOC'ed, is there
a simple way to
get that info when the memory is generated with coregen?

(xc2v3000 and ISE5.1)

-Lasse
 
I used xilmfs once...

Did you use the mfsgen utility to make your file system? If so you
probably need to use mfs_init_genimage instead of mfs_init_fs.
Essentially they vary by adjusting some pointer a byte or two (or four
or whatever). I used mfsgen and then downloaded like you mentioned and
then did this in my main:

/* Set up the file system and cd to correct dir */
mfs_init_genimage(53200, (char *) MFS_BASE_ADDRESS, MFS_INIT_TYPE);
xilmfs_result = mfs_change_dir("my_fs");
xilmfs_result = mfs_get_current_dir_name(dirname);
if(xilmfs_result == 0) {
printf("Couldn't get current_dir_name.\r\n");
printf("Exiting...\n");
exit(1);
}

I don't recall if the 53200 is the value I got directly from mfsgen or
not... maybe have to adjust it a little? Like it could have been 53204
or something (again with the pointer adjustment). Sorry if I am a
little vague, it was a while ago that I set this up. The moral of this
story is try mfs_init_genimage.

Joey
 
<newsmailcomp5@gustad.com> schrieb im Newsbeitrag
news:kjuwtgxefpt.fsf@shardlow.dolphinics.no...
"Antti Lukats" <antti@openchip.org> writes:

you can connect Cable III to the JTAG and use impact, or I could

Can you play SVF files with impact? How?

yes you can play SVF files with impact, just add them :)
Click to expand...

antti
 
In case it helps anyone, you can get the list of pins driven by a net
just selecting the net and clicking Edit->Properties of Selected Items.
You can even view the delay from the net to each pin.

Now my problem is that I only find 2 non-clk nets:

C15.I, reported as an "output", which is the driver pin where dsp_clk_a
comes from, and BUFGMUX3P.I0 which is the clock that I export to an
output pad of the Virtex-2.

I don't see why ISE complains about a non-clk net, can anyone explain
me if I'm using BUFGMUX in a wrong way?

Thanks.
JL.
 
Thanks Syms, it actually helped. This warning could not be ignored
because it led my dsp_clk_a clock signal to be implemented as a local
net, instead of a dedicated clock net. This induced a huge skew in the
circuit. Now it works as expected (well, with other errors not related
to this one...) :)

Thanks again.
JL.
 
No, BUFGMUX is the component to the clock "enter" a global clock
distribution line.
Do you feed any output pin?
 
Benjamin Marpe wrote:

Hi Peter, John and all others !

Thanks a lot for your answers!

In analog technics, I already thought of using a VCTCXO with the desired
amount of frequency variation, driven by a DAC !

But if there are other pure digital methods: please keep on posting them !
Click to expand...
That is your best approach.
The FPGA can verify the frequency, by Freq Ctr, if you wish,
and simple PWM/PDM DACs can be made in the FPGA, if the dF precision
is not large : it probably is not, 5Hz is 5ppm, so you are unlikely
to want that to be 5.000ppm/4.999ppm etc
Using an external VCTXO will also give you a truly walking phase, with
no steps, which is probably more usefull.

-jg
 
"Antti Lukats" <antti@openchip.org> writes:

newsmailcomp5@gustad.com> schrieb im Newsbeitrag
news:kjuwtgxefpt.fsf@shardlow.dolphinics.no...
"Antti Lukats" <antti@openchip.org> writes:

you can connect Cable III to the JTAG and use impact, or I could

Can you play SVF files with impact? How?

yes you can play SVF files with impact, just add them :)
Click to expand...
I guess you mean XSVF files?

I can't find out how to play XSVF files in batch mode, there is a play
command but it does not seem to take a filename as an argument.

Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?
 
Is your library for the CRC generation available to others.

JOhn

On Wed, 18 Jan 2006, Antti Lukats wrote:

"John D. Davis" <johnd@stanford.edu> schrieb im Newsbeitrag
news:pine.GSO.4.44.0601172313190.29583-100000@elaine15.Stanford.EDU...

I have configured an XCV1000 as a data and instruction cache. It is
connected to a external hard core. I would like to be able to update the
contents of the caches without recompiling the file. I have been using
Data2mem, but it appears that the CRC bits for the bitstream are not
recalculated. They are always set to: 0xDEFC

When data2mem modifies a bit file, it apparently turns off CRC checking
by replacing the calculated CRC value with a constant 0xDEFC (which
apparently spells DEFault Crc value). 0xDEFC is apparently supposed to
tell the FPGA not to bother doing a CRC check on load because we were
apparently TOO LAZY to calculate a correct value to check against.

I found one (non-xilinx) web site that indicated that Virtex-II etc. will
work just fine without a valid CRC value, but not so for Virtex.

ngdbuild, or one of those tools near it, explicitly states that "-g
CRC:DISABLE" is a valid command line option for Virtex-II but not Virtex,
and indeed project navigator complains when I attempt "-g CRC:DISABLE" for
our part.

It seems clear at the moment that data2mem is not calculating CRC values
but is calculating a bypass value instead; and it's less clear, but all
signs seem to indicate, that that would work for Virtex-II and later parts
but won't work for Virtex.

I think there must be a way to get the CRC in the bitfile, hopefully using
data2mem, but I haven't found it yet.

Has anyone run into this problem and solved it? Here is a diff of the two
bit files.

hi John,

we are using internally libraries that read bitstreams and recalculate the
CRC,
it is currently being used to fix the oscillator optons for Spartan3e, but
with
no big mods it should be able to process virtex bitstreams as well.

so as one option is to have a simple command line tool that post-process
the bitstream and injects the proper CRC.

and you are right DEFC is DEFault Crc that is needed to be written
in place of real CRC and also in place of autoCRC, also the CRC
bypass bit in COR must be set.

and as noted not all familes support the CRC bypass

Antti
Click to expand...

John D. Davis
PhD Candidate
Computer Systems Lab Office # 1.650.723.6891
Stanford University Fax # 1.650.725.6949
 
* Impact does not work out of the box with kernel
version 2.6.15.1. I had to download linuxdrivers2.6.tar.gz
and compile it. Furthermore, I had to edit the configure
script in windrvr and make sure that UDEV was not used.
(The udev interface seems to have changed in later 2.6.x
series. The relevant symbols are also GPL-only now, so I don't
think a binary only module can be distributed using UDEV in later
2.6.x kernels.)
I wrestled similarly with windrvr. It apparently uses some class_simple
Click to expand...
functions removed Jun. 20 2005. I subscribe to the LKML and was easily
able to reverse patch it.

Project manager and some other window were converted to QT I think. All
other windows use the hideous WindU lib, so you can start the ise
executable without fooling with DISPLAY but you still need it set to
":0" for all those secondary programs. Other than the subpar hotkey
junk, the interface is much more natural.

Everything much more usable now. (Gentoo, 2.6.14-gentoo-r4 w/
class_simple unpatch, WebPack 8.1, Spartan-3 starter kit w/ parallel
cable III).
 
See http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=22648
for tar.gz link and instructions.
 
hi joey,
thank you for your response.

i tried using mfs_init_genimage as you suggested. and am able to change
to the directory and also able to read the name of the directory using
mfs_get_current_dir_name funtion. but when i try to open the file i am
not able to. i used the mfs_ls() funtion to get the directory contents
but am getting a lot of garbage like

....
mnt 0
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
... 00000000
00
.. 00000000
0000
mnt 00000000
... 00000000
00000000
.. 00000
00000000
......

but the image of the filesystem generated using mfsgen on my host
system is proper which i checked using the command below in the XMD:
$ mfsgen -tfv image.mfs
mfsgen
Xilinx EDK 7.1.2 EDK_H.12.5.1
Copyright (c) 2004 Xilinx, Inc. All rights reserved.

Directory mnt 4
1_1_0.mnt 3072
1_1_0d.mnt 3072
cd..
mfsgen done!

any suggestions/ideas where i might be going wrong.

Thank you,
Rajashekar

Joseph wrote:

I used xilmfs once...

Did you use the mfsgen utility to make your file system? If so you
probably need to use mfs_init_genimage instead of mfs_init_fs.
Essentially they vary by adjusting some pointer a byte or two (or four
or whatever). I used mfsgen and then downloaded like you mentioned and
then did this in my main:

/* Set up the file system and cd to correct dir */
mfs_init_genimage(53200, (char *) MFS_BASE_ADDRESS, MFS_INIT_TYPE);
xilmfs_result = mfs_change_dir("my_fs");
xilmfs_result = mfs_get_current_dir_name(dirname);
if(xilmfs_result == 0) {
printf("Couldn't get current_dir_name.\r\n");
printf("Exiting...\n");
exit(1);
}

I don't recall if the 53200 is the value I got directly from mfsgen or
not... maybe have to adjust it a little? Like it could have been 53204
or something (again with the pointer adjustment). Sorry if I am a
little vague, it was a while ago that I set this up. The moral of this
story is try mfs_init_genimage.

Joey
Click to expand...
 
Ben,
Write a clock divider having the divider as input signal (and not as
generic parameter).
==> in this divider, u count clk cycles , when count reaches divider, u
toggle divided clock
once again the divider is an input signal ( be careful to register it on clk
falling edge to avoid pbs...)

F' = F / (2*(1+k)) where k is the divider
if you have say F=48 MHZ , k = 23 gives you a 1.00 MHz clock , k = 22 a
1.0435 Mhz , k=24 a 0.96 Mhz clk etc...
.....k=24e6 --> F'= 1Hz....


"Ben Marpe" <Ben.Marpe@gmx.de> wrote in message
news:1137597178.426492.225110@z14g2000cwz.googlegroups.com...
Dear experts in this newsgroup,

in my diploma thesis i'm using a FPGA for baseband signal generation.
I'm interested in generating and varying a clock of 1Mhz which is
DOPPLER shifted +/- 5Hz due to movements between receiver and
transmitter.

The +/- 5Hz Doppler must be applied in a very "smooth" way, the step
resolution should be as fine as possible.

Any ideas how to do this on a (Xilinx) FPGA ?
The sine output of Xilinx LogiCore DDS isn't necessary and the step
resolution might be even a little bit finer for my application.

Thanks a lot for every single hint you can give to me !

Greetings, BEN
Click to expand...
 
Jerome, Ben wants to change the clock in smaller increments than 1 ppm
(I suppose something like 0.1 ppm, which gives him 50 steps up from
nominal 1 MHz, and 50 steps down from 1 MHz.)
I see no way to achieve that with digital divider stages from a <1 GHz
oscillator.
As already suggested, a pullable xtal oscillator (VXCO) is his best
bet.
Peter Alfke
 
Petter Gustad <newsmailcomp6@gustad.com> writes:

I can't find out how to play XSVF files in batch mode, there is a
play command but it does not seem to take a filename as an argument.
Click to expand...
The solution was to use addDevice to add the file and then use play:

setMode -bscan
setCable -port lpt1
addDevice -p 1 -part file.xsvf
play
quit

Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?
 
"Carl Smith" <cdsmith69NOSPAM@gmail.com> schrieb im Newsbeitrag
news:MPG.1e38bfdf3eafc9fc98968a@news.west.earthlink.net...
OK, I just have to vent a bit.

I am laying out a board with an XC9536. The schematic capture
program I am using is a major program, not some fly by night
outfit. They claim their component library is done by an ISO
9000 organization.

So my perfectionist tendencies didn't like the fact that they
used a different font for the pin names on the XC9536 schematic
symbol than they usually do in the libraries. I went into the
"Library Executive" to change the font and when I went to save
the part the program told me that the pin numbers in the
component pin list didn't match what was entered into the
schematic capture symbol.

So I checked the XC9536 data sheet and found out that their pin
numbers for the schematic symbol were ALL WRONG. I had to spend
about half an hour relabeling all the pins, and then moving
things around to make it look nice again.

So if I hadn't decided to change that font, I could have done a
board layout with all the pins connected wrong.

I'm starting to think it would be better if board layout
programs just shipped with no pre-made components. I just end
up fixing things on nearly every single part I use anyway.
Sometimes I think it would be better if I just did it all
myself.

my trust in CAD programs to be accurate is: 0%
Click to expand...

the schematic libraries are wrong the PCB components pads are wrong, etc..

always check ALL pin mapping in schematic libs, and the PCB symbols as well,
you may end up re-doing both of them !!

after having a wrong PCB symbol in PADS i never ever again
trust blindly any pre-made CAD library components

--
Antti Lukats
http://www.xilant.com
 
So if I hadn't decided to change that font, I could have done a
board layout with all the pins connected wrong.
Click to expand...
I never trust anything direct from the vendor library.

I keep my own set of libraries. When I need a new part,
I often start with pieces I find in the vendor libraries,
but everything gets checked. It's generally sane to get
a friend to double check things. It's too easy to fool yourself.

Most of the time, you can do a layer of sanity checking
at the board layout stage. You wired signal-foo up to pin
98 because it's in the top right corner... or you swapped
signals foo and bar because that made the board easier to
route.

After they have been used on a board with no problems I
become more trusting.

--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.
 
Incorrect footprints can also be very annoying, that has caught me out
once or twice.
Click to expand...
My straw man is to print the gerber layer out 1:1 and see if the
part fits cleanly.

You may have to tweak the scale factor to get things to print
at the right size. Check the board outline with a ruler or something
like that.

--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.
 
"Ulrich Bangert" <df6jb@ulrich-bangert.de> wrote in message
news:dqndk9$8g0$01$1@news.t-online.com...
No matter what scheme you will use: Keep in mind that a "normal" x-tal
oscillator has a tempco of app. 1*10E-6/K. So a normal x-tal oscillator
will
give you a 1 Hz variation per Kelvin @ 1MHz, well in the region of the
Doppler that you want to measure. This is a indication that a "better"
oscillator has to be used. Don't go for a TCXO, look out for a cheap OCXO.

Rgegards

Ulrich Bangert

OF COURSE, use an ordinary XTAL and control its temperature with the FPGA.
Click to expand...
Perhaps some pins driving resistors stuck to the XTAL case? Some other pin
driving a servo controlled can of freezer spray? If Ulrich's figures are
correct, +/- 5K gets you what you want! :)
Cheers, Syms.
 
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