EDK : FSL macros defined by Xilinx are wrong

[Jim Granville]

Ray Andraka wrote:

Mike,

It is like there is a limit on the number of files that can be open. I
jsut ran into it trying to open Xilinx ISE7. Memory usage was only at
around 790M out of 2GB. It just wouldn't let Xilinx project manager
open. Closing Synplify let me open Xilinx.

Does sound more like a files handles type issue - you could
do a simple recursive script, that opens a couple of hundred files,
and see where that falls over ?
That would confirm #Files ceiling, and you could run it on another
XP box ?
Has it always had the ceiling, from new ?

-jg

 

[Ray Andraka]

Jim Granville wrote:

Ray Andraka wrote:

Mike,

It is like there is a limit on the number of files that can be open.
I jsut ran into it trying to open Xilinx ISE7. Memory usage was only
at around 790M out of 2GB. It just wouldn't let Xilinx project
manager open. Closing Synplify let me open Xilinx.


Does sound more like a files handles type issue - you could
do a simple recursive script, that opens a couple of hundred files,
and see where that falls over ?
That would confirm #Files ceiling, and you could run it on another
XP box ?
Has it always had the ceiling, from new ?

-jg

Yes, it was a new box in November, and I did notice it pretty much from
the get-go. Anyone know if there is a file handles limit set somewhere
in XP?

 

[Subhasri krishnan]

Thank you so much!!!!!!

Joseph Samson wrote:

Subhasri krishnan wrote:
Thanks for the reply. But consider the following scenario. After the
power up sequence, I open a row in bank n followed by multiple
read/writes. The last read/write to the current bank has auto precharge
enabled. So when I want to activate a row in bank m for the first time,
should I issue an active command and is that meaningful because there
is no example showing read/write with auto precharge interrupted by
active command to another bank (or has this not been shown because
during row activation we dont care about the DQ's? ).

When the datasheet talks about interrupting, they mean that a read or
write burst is interrupted by another read or write cycle. Once the
precharge happens, you have to wait Trp time before issuing another command.

From page 10:
"The bank(s) will be available for a subsequent
row access a specified time (tRP) after the PRECHARGE
command is issued."

and

"Once a bank has been
precharged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued to
that bank."

enabled. So when I want to activate a row in bank m for the first time,
should I issue an active command
Yes, you have to issue an active command after a bank has been
precharged, but each bank can have a row open simultaneously - you don't
have to precharge Bank n in order to activate a row in Bank m.


---
Joe Samson
Pixel Velocity

 

[Austin Lesea]

Brian,

I am paid (in very small part) to watch this newsgroup, and comment.

As for 'absurd claim', it seems you have never served on a standards
body, as your comment has me laughing.

A 'standard' serves the interests of the companies that promoted it (as
well as providing a service to the industry). There is active work by
any standards committee to exclude/disadvantage/hobble as many
competitors as possible (legally).

I used to call it "making every participant equally disadvantaged in
order to level the playing field as much as possible prior to approval."

A great example of this is when an ASIC is developed, and the company
that has it, promotes it as a standard. In the process of getting it
approved, it is inevitable that the standard will require a respin of
the silicon in order that all vendors have a chance to participate. The
original vendor must also respin their chip, as they are not "standard"
until they do so.

I have seen this multiple times in my 13 years of sitting on multiple
ANSI/ATIS/IEEE/IEC standards committees.

Since you don't know this, I suggest you go and volunteer to chair a
committee, and learn something about the real world.

Austin

 

[Mike Treseler]

Ray Andraka wrote:

Mike,

It is like there is a limit on the number of files that can be open.

That sound plausible.
I remember in the DOS days, there were settings like:

FILES=50
BUFFERS=20

in a file called c:\config.sys
I expect there is such a setting/limit
somewhere in windows system control panel.

-- Mike Treseler

 

[Antti Lukats]

"maxascent" <maxascent@yahoo.co.uk> schrieb im Newsbeitrag
newsfmdnUpOU__8lljeRVn-uA@giganews.com...

Can you get samples from Xilinx, Altera or Lattice? Or where is the
cheapest place to buy small quantities?

Thanks

Jon

it is possible to get samples from: Atmel (FPSLIC), Actel, Altera, Lattice
and Xilinx however you are probably easier to just buy what you want, both
xilinx and altera have FPGAs in their online shops, prices start from about
10USD

optionally it may actually make more sense to buy some low low cost eval
board

avnet S3e board is 69USD

http://www.oho-elektronik.de/
89EUR spartan3 module

http://www.hardware-design.de/produkte.html

there are lattice cheap boards 60EUR or so

at 99-149 USD price there are many more

you can of course do the board yourself
http://xilant.com/content/view/35/2/

sometimes ebay has FPGAs are low low price, so I made my first 2Million Gate
FPGA board with 49USD pulled BGA what I got from ebay

its all up to you, if you have no FPGAs and no FPGA boards I suggest buying
the first eval board, either TREX C1 or then wait for the Xilinx Spartan3E,
of if your budget is below 100USD then choose from other offerings

--
Antti Lukats
http://www.xilant.com

 

[Joseph Samson]

Pouria wrote:

HI Everybody!

I'm having a timing problem interfacing with my SDRAM bank. I'm using
256Mb MT48LC16M16 SDRAM from Micron, and want to operate them at 100 Mhz.
So far I have only been working at 40 Mhz.

I'm using two DLLs (inside my VirtexII) one for clocking the FPGA and one
for clocking the SDRAM. The design works if I DON'T use the external
feedback from SDRAM_Clk to one of the DLL, but it fails as soon as I use
the feedback (Which according to Xilinx should be the correct way to
terminate clock Skew).

The feedback to the other DLL is taken from clock output of it self, and I
have used IBUG/OBUF/BUFG so that is not the problem.

As Gabor pointed out, register all signals in the IOBs and use fast slew
rate drivers. I highly recommend using the DDR IOB flipflop to generate
the SDRAM clock. That dramatically improved my SDRAM design, and now I
generate all external clocks that way. You might have good luck sending
an inverted clock to the SDRAMs. I don't use the clock feedback.

Once you get the design running, experiment with lowering the output
drive. The default is 12mA, but my layout allows me to go as low as 4mA.

---
Joe Samson
Pixel Velocity

 

[Mike Harrison]

On Wed, 11 Jan 2006 14:14:24 +0100, "Antti Lukats" <antti@openchip.org> wrote:

"Johan" <jvm.jr@pandora.be> schrieb im Newsbeitrag
news:ei7xf.93683$ZL.6095929@phobos.telenet-ops.be...
Dear hobbyists,

I need some advice on FPGA's. One of my projects involves VGA video
generation (with AVR microcontroller). I want to use FPGA's instead of MCU
to produce higher resolutions. The FPGA should read data from sram and
send it to a D/A converter. Wich FPGA can I use for this? Altera, Xilinx?
I suppose I need to write the code in Verilog? Wich of the two has the
best free of least expensive software?

Thanks in advance

Johan


pretty much all vendors have free sw that is sufficent for your purposes
you can also use any FPGA, its all up to you what to choose

you can write in verilog VHDL or design in schematics whatever you
like the best, there are plenty of VGA/display examples available
so its the best to get some sample code and check it out and then
start modifiying to your needs or write your own

www.fpga4fun.com has very simple pong game, well it is not
using any memory at all, but its very simple and easy

there are many more complex projects, just search the net

You could probably also do it in a CPLD (e.g. Xilinx 95xx series) if cost is an issue and you have
the time to optimise it to fit, but an FPGA will give you plenty of room to play with - e.g. Xilinx
Spartan-3 series.
Another advantage with FPGA is that you have some RAM to play with which may help buffering data to
and from the SRAM,a nd also allows room for things like fonts etc.

 

[Antti Lukats]

"Mike Harrison" <mike@whitewing.co.uk> schrieb im Newsbeitrag
news:lpaas1hmbai2h63a0ds04rmqhjatqt8u8b@4ax.com...

On Wed, 11 Jan 2006 14:14:24 +0100, "Antti Lukats" <antti@openchip.org
wrote:

"Johan" <jvm.jr@pandora.be> schrieb im Newsbeitrag
news:ei7xf.93683$ZL.6095929@phobos.telenet-ops.be...
Dear hobbyists,

I need some advice on FPGA's. One of my projects involves VGA video
generation (with AVR microcontroller). I want to use FPGA's instead of
MCU
to produce higher resolutions. The FPGA should read data from sram and
send it to a D/A converter. Wich FPGA can I use for this? Altera,
Xilinx?
I suppose I need to write the code in Verilog? Wich of the two has the
best free of least expensive software?

Thanks in advance

Johan


pretty much all vendors have free sw that is sufficent for your purposes
you can also use any FPGA, its all up to you what to choose

you can write in verilog VHDL or design in schematics whatever you
like the best, there are plenty of VGA/display examples available
so its the best to get some sample code and check it out and then
start modifiying to your needs or write your own

www.fpga4fun.com has very simple pong game, well it is not
using any memory at all, but its very simple and easy

there are many more complex projects, just search the net

You could probably also do it in a CPLD (e.g. Xilinx 95xx series) if cost
is an issue and you have
the time to optimise it to fit, but an FPGA will give you plenty of room
to play with - e.g. Xilinx
Spartan-3 series.
Another advantage with FPGA is that you have some RAM to play with which
may help buffering data to
and from the SRAM,a nd also allows room for things like fonts etc.

now when you mentioned PLD, there is 8 bit VGA project using small PLD and
SRAM chips
http://www.ulrichradig.de/index.html

seek PLD there is link to the design...


--
Antti Lukats
http://www.xilant.com

 

[Petter Gustad]

Antti.Lukats@xilant.com writes:

http://wiki.openchip.org/index.php/Altera:JTAG

MAXII is similar to Cyclone, I have verified that in silicon

Thanks!

BTW, is there a way to make quartus_pgm play SVF files (or convert SVF
into some other format I can play)? I would like to play the following
file:

SIR 10 TDI (007);
SDR 32 TDI (FFFFFFFF); ! or some other pattern

I would then expect to observe the USERCODE value being shifted out of
the maxii_jtag module from my user logic.


Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

 

"Antti Lukats" <antti@openchip.org> writes:

you can defenetly use jam/stapl with quartus, its a bit pain as it requres
CRC I think it can be ignored and after warning quartus programmer will
accept the file but its generically more pain than using SVF

Is there a way to convert SVF to JAM/STAPL using Qaurtus? I was hoping
I could just do something like

quartus_pgm --play-svf file.svf

or similar.

you can connect Cable III to the JTAG and use impact, or I could search my

I'll just make a jumper and use the JTAG Techologies BV software...
Thanks.

Petter

--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

 

[GaLaKtIkUs™]

Hi everybody,
I downloaded it at 250kb/s.

Regards
Mehdi

 

[Austin Lesea]

Brian,

I give up. Just when I get serious with you (and treat you like the
experienced designer you purport to be), you move onto another subject,
and pour forth more vehemence.

....

http://xgoogle.xilinx.com/search?getfields=*&btnG=Google+Search&output=xml_no_dtd&sort=date%3AD%3AL%3Ad1&ie=UTF-8&client=xilinx&oe=UTF-8&proxystylesheet=xilinx&filter=0&requiredfields=status%3Aactive&q=Virtex+II+DCI&submit2.x=28&submit2.y=9&submit2=Search&site=AnswersDatabase

is the link to the 117 answers on Virtex II DCI... (to counter your
"poorly documented" comment..."


I acknowledge you had a less than satisfactory experience (with Virtex
II DCI), and I am unlikely to change your mind about Xilinx, or their
business practices, or Xilinx honesty policy.

For that, I am truly sorry.

Austin

 

[Gabor]

Joseph Samson wrote:

Pouria wrote:

HI Everybody!

I'm having a timing problem interfacing with my SDRAM bank. I'm using
256Mb MT48LC16M16 SDRAM from Micron, and want to operate them at 100 Mhz.
So far I have only been working at 40 Mhz.

I'm using two DLLs (inside my VirtexII) one for clocking the FPGA and one
for clocking the SDRAM. The design works if I DON'T use the external
feedback from SDRAM_Clk to one of the DLL, but it fails as soon as I use
the feedback (Which according to Xilinx should be the correct way to
terminate clock Skew).

The feedback to the other DLL is taken from clock output of it self, and I
have used IBUG/OBUF/BUFG so that is not the problem.

As Gabor pointed out, register all signals in the IOBs and use fast slew
rate drivers. I highly recommend using the DDR IOB flipflop to generate
the SDRAM clock. That dramatically improved my SDRAM design, and now I
generate all external clocks that way. You might have good luck sending
an inverted clock to the SDRAMs. I don't use the clock feedback.

Once you get the design running, experiment with lowering the output
drive. The default is 12mA, but my layout allows me to go as low as 4mA.

---
Joe Samson
Pixel Velocity

That's a good point about using the IOB flip-flop. In Virtex II you
can use the
DDR flip-flop to output a clock at the same frequency that clocks the
flip-flop.
The timing will match clock-to-out on other IOB flip-flops that use the
single
output flip-flop (it's really the same hardware). If you use a single
clock in the
design you'll have hold-time issues at the SDRAM because your data,
address,
and control signals will coincide with the rising clock edge (0 hold
time). Use
a DCM to generate a delayed clock for everything other than the SDRAM
clock outputs. If the delay between clocks is small, just enough to
meet
SDRAM hold time requirements, you shouldn't have hold time issues on
your
input registers (but don't assign NODELAY to the input nets).

Also note that lowering the output drive increases the output clock to
Q time.
You can use this selectively to intentionally add skew between signals
if
necessary (but not a lot). I often drive clock outputs with higher
current to
slightly advance the timing with respect to other signals.

Good Luck,
Gabor

 

Run Window Task manager
View->Select columns.
Select USER and GDI Objects.
Now sort on them. If any process is consuming a lot , then it could be
problem.
There is a limit of 64K on them.
One such process is wisptis.exe which get lauched when running acrobat
on some WinXP systems.

Also you may need this patch forWInXP
"MFC applications leak GDI objects on computers that are running
Windows XP"
http://support.microsoft.com/?id=319740

 

[Brian Davis]

John_H wrote:

You're just more effective at pushing his buttons than most.

For me, posting about Cin/ DCI problems is all it takes to set him off.

Go read that thread I'd linked to as an example of his posting
etiquette, which went something like this:

Peter A. : Series DCI has zero additional system power
Brian : Except for the 200 mW/bank overhead
Austin : ( leap in with guns blazing )
Brian : ( return fire )

Along those lines, I love the riddle that leaves most
americans perplexed but non-Americans laughing:
"Q: What does an American do with a question?
A: He answers it."

Some questions are best left un

Conspiracy theory aside, have you been involved with standards development?

One step removed, working with the guy who's on the committee,

to build the T&M equipment needed for verification, or the equipment
needed to test the equipment needed for verification.

I don't doubt that there are compromises made that favor existing
silicon because the owners of that silicon (or those transmission systems)
want to revamp less of their technology. A good compromise is reached when
nobody's happy.

There are certainly politics, but claiming that a basic PCI electrical

loading specification is rigged specifically to exclude FPGA vendors
is a bit (insert non-offensive adjective of choice here).

Brian

 

[Brian Davis]

Ray Andraka wrote:

OK, I wasn't aware of those issues. So far, I haven't used DCI because
of die temperature concerns, so I haven't stumbled across the hidden
issues.

After last checking them in June '05, I summarized the poor state

of the DCI Power Answer Records over here:

http://groups.google.com/group/comp.arch.fpga/msg/f66ab4d7063f5c3f

Brian

 

[Brian Davis]

Austin,

Just when I get serious with you (and treat you like the
experienced designer you purport to be),

You've already called me a novice, no need to repeat yourself.

you move onto another subject, and pour forth more vehemence.

Check the message timestamps, I posted that response to you

about ten minutes BEFORE I replied to Ray.

http://xgoogle.xilinx.com/search?getfields=*&btnG=Google+Search&outpu...

is the link to the 117 answers on Virtex II DCI... (to counter your
"poorly documented" comment..."

Scattered, incomplete, and inaccurate Answer Records are not
proper documentation of such a serious problem as has V2 DCI.

We've had that discussion before, too.

I acknowledge you had a less than satisfactory experience (with Virtex
II DCI), and I am unlikely to change your mind about Xilinx, or their
business practices, or Xilinx honesty policy.

For that, I am truly sorry.

I don't want an apology for past documentation problems,
I want you (Xilinx) to fix those problems so others don't
bang into the same things on old & new parts.

It didn't really bother me that I hit those problems in
early 2003, three years after the V2 product launch.

Or that a months long webcase produced no solid answers.

Or that six months later, all the CR's I'd filed hadn't
corrected the documentation/Power Estimator/Xpower problems.

What really ticked me off is that when I personally took the
time and effort to summarize all those problems in that
"LVDS_25_DCI Top Ten List" post here in Oct. 2003, you launched
the first in a series of attacks on me, when I've mentioned
related Cin/DCI Power/FreezeDCI problems here on the newsgroup.

Brian

 

[Brian Davis]

Austin,

8 banks, time 200 mW = 1.6 watts. At 1.5 volts that would be one ampere.
A little exageration here? At 3.3 volts, that would be less amperes?

IIRC, 2A extra per board, or about 400 mA extra per chip @2.5V VCCO,

for both bank overhead and parallel termination error, five 2V250's,
about 20 LVDS_25_DCI per chip.

This has since been fixed in later families so that freeze is done better.

The latest family DCI is improved in these areas.

Documentation thereof can be found where?

Ah, finally we have some facts!

Funny how my facts of yesteryear have become your facts of today.

----------

[Austin_2004]:
Freeze DCI has nothing to do with it.

[Brian_2004]:
Using FreezeDCI in the V2 affects both the behavior and
repeatability (config-config & part-part) of static DCI power
consumption, both for per-bank overhead, and particularly
for per-input parallel terminators

[Austin_2006]:
Freezing it also stopped the reference resistor search,
which could (randomly) increase the ref resistor power (in V2).

----------

[Brian_2004]:
As each bank has its' own independent CCLK type oscillator
driving the tap adjustments, you end up with a random sampling
of the possible DCI adjustment states for each bank.

As I understood it, the newer devices having DCIUpdateMode
were going to cleanly stop the DCI updates in all banks at a
known state rather than randomly halting them as with FreezeDCI.

[Austin_2006]:
Standards which crossed a bank also had issues, as the controllers
were independent (one for each bank, not synchronized).

This has since been fixed in later families so that freeze is done
better

----------

[Austin_2004]:
DCI updating is only an issue when you cross between two banks,
and even then only with the parallel interfaces where it adds some
small amount of jitter

[Brian_2004]:
On the other hand, with FreezeDCI on, the resulting random
DC offset for the parallel terminators will probably cause
problems for the single ended standards with accurate
terminator VTT requirements (whether in one or multiple banks).

[Austin_2006]:
which led to some problems with specific applications (primarily
wide buses with extremely critical timing using HSTL or SSTL
parallel standards).

----------

Brian

References:
[Austin_2004]:
http://groups.google.com/group/comp.arch.fpga/msg/9c36b288d94edb99
[Brian_2004] :
http://groups.google.com/group/comp.arch.fpga/msg/4a7fa8984b3395db
[Austin_2006]:
http://groups.google.com/group/comp.arch.fpga/msg/46d9b8ff632b6e5f

 

[kdfake@spam.com]

thanks for the info.

C++ would be good to see.
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