EDK : FSL macros defined by Xilinx are wrong

[Mike Treseler]

Ray Andraka wrote:

Hard to tell, If I am at the computer it is because I am doing design
work, which means one or more of those apps is open. It doesn't seem to
be tied to any one of those apps though. I've seem MSword do it too
with a long document (50 page book chapter with about 50 drawings). It
is as though there is a memory leak, but it isn't showing up on the task
manager.

I expect than one of the windows system
files has been corrupted. I would try
an online update or a setup/repair from
the windows CD.

At work, I use one machine for sim and docs
and a second machine for synth/p+r, both
using the same file server for sources.

-- Mike Treseler

 

[Subhasri krishnan]

Thanks for the reply. But consider the following scenario. After the
power up sequence, I open a row in bank n followed by multiple
read/writes. The last read/write to the current bank has auto precharge
enabled. So when I want to activate a row in bank m for the first time,
should I issue an active command and is that meaningful because there
is no example showing read/write with auto precharge interrupted by
active command to another bank (or has this not been shown because
during row activation we dont care about the DQ's? ).

Joseph Samson wrote:

Subhasri krishnan wrote:
Hi all,
I am designing a memory controller and I want to use concurrent auto
precharge. I am using a micron SDR-SDRAM (
http://download.micron.com/pdf/datasheets/dram/sdram/64MSDRAMx32.pdf ).
The datasheet doesnot specify how to activate a row in bank m when the
current state is bank n. Is there a way I can specify the row that
should be activated? and which row will be activated (figure 24 in
pg:23) when current state of bank m is page active at T0 (same figure)
? Please tell me where I can learn more about this.
Thanks for any help.
Subhasri

Precharging means 'closing' a row so that a different row in that bank
can be opened. The auto precharge example in Figure 24 assumes that the
rows are already activated - remember, there can be several rows active
at the same time as long as each row is in a different bank. In Figure
24, there is a row active in Bank n and a row active in Bank m.
Figures 3 and 4 on page 12 show how to activate a row.

---
Joe Samson
Pixel Velocity

 

[John_H]

"bjzhangwn" <bjzhangwn@126.com> wrote in message
news:1136820555.537510.298830@g43g2000cwa.googlegroups.com...

Now I want a Tcam ,and the need is below,read must be completed in 1
cycle,Entry 2048,word length 32bits,If I can implemented it in the
fpga,can someone give me some advice.Thanks!

Is your cycle running at 1 MHz?

 

[Ray Andraka]

Morten Leikvoll wrote:

Instead of using INIT_XX=>"...." I would like to write like "INIT(W,A)=>D"
where W is the buswidth and D is the initial value (including parity bus) at
the port at adress A. This is a plain mapping function and maybe someone has
done this before me so I dont have to rewrite it?


You still need the init_xx= attributes , however you can put the

primitive inside a wrapper and write a set of functions to deconstruct
an integer array passed as a generic and generate the proper init_xx
attributes. You can even handle data split across multiple BRAMs this way.

Do it with a vhdl function (I am assuming you are using VHDL, this would
be really ugly with verilog) that accepts the data array (array of
integers, passed into your wrapper as a generic), an index which
corresponds to the XX in INIT_XX, and the msb and lsb of the slice the
function is to generate. From the widht of the field (msb:lsb) you can
infer the length of the output bit vector, as well as the address into
your integer array that holds the data. The output of the function is a
bit vector to match the generic on the BRAM primitive. You can write a
second function to convert the bit vector to the hex string needed for
the attribute.

 

[John_H]

"Nitesh" <nitesh.guinde@gmail.com> wrote in message
news:1136671134.056348.151120@g47g2000cwa.googlegroups.com...

I had posted earlier my issues with Fpga card.

http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/73534630e805751a/21f880630f20ca74?q=fpga+pci&rnum=1#21f880630f20ca74

The AMIRIX fpga card uses powerspan II pci bus switch fro Tundra. The
powerpc inside teh fpga has linux running..I have some data in my PLB
master/slave module which has to be transferred to the host pc. So I
was suggested to llok into DMA transfer part. I went through the
powerspan II manual . It doesnt provide the details of data cycle for
the DMA . i.e it only says to write the DMA configuration registers
with the source address , destination address... and then raisethe go
signal. Now my problem is that the source address needs to be the
on-board RAM address. I dont want to use the onboard RAM.I dont want to
use the powerpc either. I wanted to write a module in vhdl to do the
confguration adn the forward the data to the bridge. I dont know
whether this is possible. I

I dont have experience in this field. How can I do a transfer of data
from my master/slave module to the host computer?
Is there a way ?
Thanks,
Nitesh

If you want to write a VHDL module to do the DMA, you need to interface to
the PCI core in your FPGA. The manual for the core should have information
on DMA operation.

 

[cdsmith69@gmail.com]

In article <1136696831.548553.204390
@z14g2000cwz.googlegroups.com>, cdsmith69@gmail.com says...

....the same thing I said several times before.

It looks like my original posting attempts through google groups
finally showed up after 3 days. Sorry about the double or
triple posts. It won't happen again now that I have a real
newsreader setup.

 

[Ray Andraka]

Mike Treseler wrote:

Ray Andraka wrote:

Hard to tell, If I am at the computer it is because I am doing design
work, which means one or more of those apps is open. It doesn't seem
to be tied to any one of those apps though. I've seem MSword do it
too with a long document (50 page book chapter with about 50
drawings). It is as though there is a memory leak, but it isn't
showing up on the task manager.


I expect than one of the windows system
files has been corrupted. I would try
an online update or a setup/repair from
the windows CD.

At work, I use one machine for sim and docs
and a second machine for synth/p+r, both
using the same file server for sources.

-- Mike Treseler

Do the on-line updates repair/replace all of the windows files? I keep
the system updated with the windoze updates, and none of the updates
have fixed it. I've been reluctant to do the windows repair from the CD
because my experience in the past with NT meant doing that and then
going back and redoing all the updates, service packs etc, plus the
occasional reinstall of applications. I suppose doing the repair from
the CD is the next step, I'm jsut dreading it because it probably also
means a day lost getting things back to where they are now.

My main machine is an Athon 64x2 hypersonic cyclone ocx. Moving to this
I more or less abandoned the two machine set up I had previously,
although I still have the second machine here untouched but not powered
up unless I need it. The previous set-up was a dual P3-800 for the
docuementation, design entry, sim, internet access etc and a dual
K7-1800 for par and synthesis. My hearing was getting affected by the
vacuum cleaner like sound emanating from those two machines, and the
excess heat in the room was rather impressive. Part of the reason I
retired the dual P3-800 was to get back onto a single machine to reduce
the noise and heat load, as well as to avoid the network bottleneck
between machines. Simulation as well as the synth and par do run
noticibly faster on the cyclone, provided I can open everything I need
opened. It is also quite a bit cooler, and with the liquid cooling is
virtually silent compared with the vacuum cleaner.

 

[Guido]

ftp://ftp.altera.com/outgoing/release/

Here is the one where you can find the software.

Guido

 

[Antti Lukats]

"Gilles GEORGES" <georges@irisa.fr> schrieb im Newsbeitrag
news:dpu2ud$had$1@amma.irisa.fr...

Antti Lukats wrote:
"Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag
news:dptig7$jk$01$1@news.t-online.com...

"Gilles GEORGES" <georges@irisa.fr> schrieb im Newsbeitrag
news:dpteh3$9hk$1@amma.irisa.fr...

Dear,

I received last week a Xilinx USB Platform Cable.
Using ISE 7.1.04i and EDK 7.1.2 under Fedora core 2 with kernel
2.6.6-1.435.2.3smp, the precompiled driver is not suitable.

[snip]

Firmware version = 1018.
CPLD file version = 0006h.
CPLD version = 1648h.

that is weird on WinXP the file version and CPLD version are the same as
displayed

sorry I meant displayed should be

CPLD file version = 0006h.
CPLD version = 0006h.

antti



Dear Antti,

I just tried the cable with same board on a Win XP computer and it works.
I previously downgrade to cpld firmware V4 (taken in a ISE 6.3 linux
install) => not working under linux but working under windows. Then i
upgrade to version 6 and still working under windows.

Going back to my Linux workstation nothing works.

There is a strange thing with Impact, the "CPLD version" differs with the
"CPLD file version" while the two match on Windows.

Connecting to cable (Usb Port - USB22).
Checking cable driver.
File version of /local/xilinx/bin/lin/xusbdfwu.hex = 1018(dec), 03FA.
File version of /etc/hotplug/usb/xusbdfwu.fw/xusbdfwu.hex = 1018(dec),
03FA.
Max current requested during enumeration is 150 mA.
Cable Type = 3, Revision = 0.
Setting cable speed to 6 MHz.
Cable connection established.
Firmware version = 1018.
CPLD file version = 0006h.
CPLD version = 0021h.

Any idea.

Gilles

tell Xilinx to hire professianals to write and test their software

seriously Linux support just is behind, so all Linux users just have to
accept WAY more problems as WinXP users.

also different departments of Xilinx have their own JTAG drivers and low
level access API so when one departments gets something working then others
do not, then comes new Cable or firmware/PLD update and the game begins all
over, something will brake each time

either impact or XMD server or Chipscope will fail

not really fun

Antti

 

[Morten Leikvoll]

Doh.. I missed on the parity bits. You need to flip INITP00 lines so that
MSB (init3F(35 downto 32) appears first.. same for the other INITP0x's. Too
fast copy and paste..

 

[Andy]

What you're trying to do is an expression with operators (&amp that
requires execution. This cannot be aliased. An alias must be of all,
or a contiguous part, of an existing object, with no execution
required.

You could alias to a slice of an array, but not to a concatenation of
bits in an array.

Otherwise, what Mike said.

Andy

 

[Austin Lesea]

Jude,

ES marking implies that the:
-test program is not final (parts are almost ready for production release)
or
-the verification and characterization is not complete (early silicon,
not all errata are known, or there is still work to do to characterize
the parts)
or
-the part is from a lot that has not finished process qualification
(also early silicon, but all process qual tests may still be incomplete)

Once we have the final test program coverage we require, and the
verification and characterization os signed off, and the process
qualification is complete, then we stop marking parts as "ES."


Stepping relates to the features. Stepping 1 may have more features
than stepping 0 (and may also have fewer errata, or no errata at all).

The stepping program makes it such that a newer stepping is backward
(bitstream) compatible with an older stepping (the old bitstream
provides the same performance). To gain the new features, a new
bitstream may be required.

Austin

 

[Mike Treseler]

Ray Andraka wrote:

Do the on-line updates repair/replace all of the windows files?

No, just some.

I keep the system updated with the windoze updates, and none of the updates
have fixed it.

OK that's not it.

I've been reluctant to do the windows repair from the CD
because my experience in the past with NT meant doing that and then
going back and redoing all the updates, service packs etc, plus the
occasional reinstall of applications. I suppose doing the repair from
the CD is the next step, I'm jsut dreading it because it probably also
means a day lost getting things back to where they are now.

A day if you're lucky.
Sometimes it's more efficient to
go to Fry's and pick up another
box preloaded with the latest XP.

My main machine is an Athon 64x2 hypersonic cyclone ocx.

Is the the XP 64 bit version much of an advantage
for your applications?

Moving to this
I more or less abandoned the two machine set up I had previously,
although I still have the second machine here untouched but not powered
up unless I need it. The previous set-up was a dual P3-800 for the
docuementation, design entry, sim, internet access etc and a dual
K7-1800 for par and synthesis. My hearing was getting affected by the
vacuum cleaner like sound emanating from those two machines, and the
excess heat in the room was rather impressive.

I hear you on the noise.
I am now using a dell optiplex gx520.
It has a fan, but that is inaudible from 2 feet away.

Part of the reason I
retired the dual P3-800 was to get back onto a single machine to reduce
the noise and heat load, as well as to avoid the network bottleneck
between machines.

Hmm. It seems that a 100M ethernet network
ought to keep up a hard drive. What caused
the bottleneck?

Simulation as well as the synth and par do run
noticibly faster on the cyclone, provided I can open everything I need
opened. It is also quite a bit cooler, and with the liquid cooling is
virtually silent compared with the vacuum cleaner.

A single application machine is my goal as well.
Right now, I have one machine running
emacs, modelsim, quartus and open office on Suse Linux
and a separate windows machine for Leo
and Fluke Networks winXP applications.

The key for me is to use an external file
server for 100% of all data files, and to
keep nothing but OS and applications
on my local machine.

Good luck.

-- Mike Treseler

 

[Mike Harrison]

On 9 Jan 2006 10:55:15 -0800, "Andy" <jonesandy@comcast.net> wrote:

What you're trying to do is an expression with operators (&amp that
requires execution.

I realise that & is probably not the right operator..

This cannot be aliased. An alias must be of all,
or a contiguous part, of an existing object, with no execution
required.

All I want do do is alias a group of bits that are not consecutive in the original signal, so I can
assign values to them as a group in a fashion that is logical for my application, instead of
assinging to each bit seperately.

If I can make an alias of bits 3,2 and 1 of a vector signal, why can't I do the same thing with
bits, say, 8, 4 and 2 instead?
All I want to do is the same thing where the bits are not consecutive - There is no execution
required.

Seems a bizarre limitation if this is not possible but then again the more I use VHDL the more I'm
surprised at how primitive and unfriendly it is in some respects...!

 

[Marc Guardiani]

You're welcome. When I read that your outputs were inverted I knew what
the problem was immediately.

I lost about a week's work on this one last year and really tore into
the Xilinx FAEs about not posting the patch directly on the download
page. It is precisely this sort of attitude by Xilinx that has me using
Altera for all new designs (start the Xilinx vs. Altera debate!).

Marc


cdsmith69@gmail.com wrote:

I tried to post this several times yesterday through google
groups and it never showed up, so I got a real newsreader
installed now. If it shows up multiple times it's google's
fault.

In article <1136560656.002159.239020
@g49g2000cwa.googlegroups.com>, news.guardiani@gmail.com says...

The solution is simple, but far from obvious. You need to
download and apply the patch for ISE 7.1 or install the
latest service pack (4). There is a bug that inverts all of
the outputs of CPLDs (with no service pack and also
maybe SP1).

Bingo. That fixed everything. After downloading the 7.1.04
update, which was something like 325 megabytes, nearly as big as
the full download, everything is working fine. My counter
counts right, the outputs aren't inverted, and I can even
directly assign pins to a value and have it work.

Xilinx has refused to post this information to their download
page. I even talked to a factory FAE and he could not get
them to post it. The only way you can find out about it is to
search their site for key words that match the article.

I spent a long time a couple nights ago searching their whole
knowledge base section and reading everything I could find on
the 9500 family CPLDs and never found this information. I only
found it after I went to the download page for the service pack,
and found the link that said something like "read this before
installing" and somewhere in there was a list of what the update
fixed, and in there was a short sentence or two saying that it
fixed an issue with CPLD outputs being inverted. It never did
mention fixing the problem where I couldn't directly assign a
pin to 1 or 0 and have it work. Either way it came out as a
high. Now it works with 7.1.04.

Right now, there isn't much I can say in polite company about
how this makes me feel. This bug has cost me several days time.
If I had been working on a real project at work, instead of
hobby tinkering at home, it would have cost the company a lot of
money in engineering time.

I think it is rather irresponsible of them to not at least have
a notice on the download page for 7.1 saying you NEED the update
to 7.1.04 if you are using CPLDs. And what they really should
have done is taken down the 7.1 update and replaced it with a
7.1.04 full download, and also have the 7.1.04 update available
for those who already have 7.1 installed.

Many thanks to you Marc, and to everyone else who posted their
ideas. Now I can get on with my original project, and maybe
have some fun and learn something with CPLDs and FPGAs.

 

[Mike Treseler]

Mike Harrison wrote:

I realise that & is probably not the right operator..

Andy is correct.
I can't use any operator as an alias.
An alias is just an alternate name for a slice
of an existing variable or signal.
Your example is more than a simple rename.

Seems a bizarre limitation if this is not possible but then again the more I use VHDL the more I'm
surprised at how primitive and unfriendly it is in some respects...!

It's not the only one.
VHDL started as a simulation language.
There are many language features
like alias, block, wait, etc that
seem like they ought to be useful
for synthesis, but just aren't.

-- Mike Treseler

ps:
David Bishop said it best:
"VHDL was written by a bunch of software guys who knew nothing about
designing hardware. We beat on it until you could do hardware with it.
Verilog was written by a bunch of hardware guys who knew nothing about
designing software. We beat on it until you could do software with it.
Neither does the job they were originally intended to do, but they work."

 

[Joseph Samson]

Subhasri krishnan wrote:

Thanks for the reply. But consider the following scenario. After the
power up sequence, I open a row in bank n followed by multiple
read/writes. The last read/write to the current bank has auto precharge
enabled. So when I want to activate a row in bank m for the first time,
should I issue an active command and is that meaningful because there
is no example showing read/write with auto precharge interrupted by
active command to another bank (or has this not been shown because
during row activation we dont care about the DQ's? ).

When the datasheet talks about interrupting, they mean that a read or
write burst is interrupted by another read or write cycle. Once the
precharge happens, you have to wait Trp time before issuing another command.

From page 10:
"The bank(s) will be available for a subsequent
row access a specified time (tRP) after the PRECHARGE
command is issued."

and

"Once a bank has been
precharged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued to
that bank."

enabled. So when I want to activate a row in bank m for the first time,
should I issue an active command
Yes, you have to issue an active command after a bank has been

precharged, but each bank can have a row open simultaneously - you don't
have to precharge Bank n in order to activate a row in Bank m.


---
Joe Samson
Pixel Velocity

 

[Ray Andraka]

Mike,

It is like there is a limit on the number of files that can be open. I
jsut ran into it trying to open Xilinx ISE7. Memory usage was only at
around 790M out of 2GB. It just wouldn't let Xilinx project manager
open. Closing Synplify let me open Xilinx.

 

[Jim Granville]

Marc Guardiani wrote:

You're welcome. When I read that your outputs were inverted I knew what
the problem was immediately.

I lost about a week's work on this one last year and really tore into
the Xilinx FAEs about not posting the patch directly on the download
page. It is precisely this sort of attitude by Xilinx that has me using
Altera for all new designs (start the Xilinx vs. Altera debate!).

Yes, they do seem to have lowered emphasis on CPLD - Xilinx's
are now the oldest families on the market, with both Altera & Lattice
having newer CPLD families.
The OP should stick with the SW that works, but I'd also suggest
future download of the V8.1 into a parallel install, just
to see what they have added - and it is quick to go back...
Good SW version control, archives the tools with the designs, and
this is another example of why this matters...
Since the OP knows ABEL, but is new to both Xilinx tools, and
their CPLDs, I'd also suggest some parallel ABEL code, just to
check 'what's possible', if a similar issue occurs again...

-jg

 

[Nitesh]

The pci bridge used is powerspan II from tundra
http://tundra.com/DST/PowerSpanII.cfm
I dont think so I need a pci core. I am not sure about the pci core
function but I feel it is same as what on-board pci bridge does.
Right now At reset the powerpc running linux on it does the
initialization I guess. I think I have to customize the vhdl interface
at the front end which interfaces the fpga with the bridge and add a
functionality of configuration.What I reaaly need to do after that is
configure the bridge with right images in the registers at powerup.
Then I need to figure out a way to do DMA transfer. I am trying to
create a list of powerup functions( images,addresses) and the timing
diagram for the data and address phases to do the dma.Then will start
writing the code. I hope I am on the right track.
Thanks,
Nitesh