EDK : FSL macros defined by Xilinx are wrong

[Len]

I think you're wrong.

 

[hitsx@hit.edu.cn]

Altera
In the field of both user interface and functionlity.

 

[Jim Granville]

news.guardiani@gmail.com wrote:

The solution is simple, but far from obvious. You need to download and
apply the patch for ISE 7.1 or install the latest service pack (4).
There is a bug that inverts all of the outputs of CPLDs (with no
service pack and also maybe SP1).

Go to www.xilinx.com, select downloads, log in (or create a new
account), then select your ISE version and OS.

Xilinx has refused to post this information to their download page. I
even talked to a factory FAE and he could not get them to post it. The
only way you can find out about it is to search their site for key
words that match the article.

One has to wonder how this schoolboy error got past their supposedly
'rigourous regression testing' - oh, maybe that is only for FPGAs ?

You could also move to ISE 8.1 ?

-jg

 

[Mike Treseler]

John Larkin wrote:

I don't have time to learn an HDL. I read the Xilinx book, draw
schematics (on paper!), and hand them to a minion to enter and
compile.

Ah! The academic solution.
Where have all the minions gone?
Long time passing ...

-- Mike Treseler

 

[Jim Granville]

Eli Hughes wrote:

Hello:

I have absolutely no experience in ASIC design. I do however have
experience in FPGA. I have a CPU design that is currently working in a
Xilinx FPGA. The design fits in a spartan3 XCS200 (144pin Package).

I want to migrate to a fully custom chip in a different package. My
design only has 10 pins that are used for signals so I want to get into
a very small package such as a SOIC20 or a micro lead frame (QFN) 32
package.


Is it possible to take a synthesizable netlist to an ASIC vendor and get
a custom chip in a custom package? What kind of Costs should I expect?
Right now the FPGA solution is too big and to expensive for the runs I
need. The Spartan chips need to get to around $4 (and in a smaller
package) to become cost effective (rather than $20). Also, I want to
get rid of the configuration FLASH to save $$ (Hence the ASIC)

You do not mention your volumes : ASICs (and even some FPGA-ASIC
alternatives, as well ) have substantial NRE (setup) costs, as
well as minimum volumes.
FPGA vendors boast about sub $3 'future-price' devices, and also
have flows that lower prices for stable code and high volume.
- but their high volume, and your high volume, may be different
For cheapest config, look at SPI FLASH devices.

-jg

 

[cdsmith69@gmail.com]

In article <43bdc395$1@clear.net.nz>, no.spam@designtools.co.nz
says...

You do realize Xilinx has ABEL flows for their CPLDs ?
[ Scan for .ABL files, in their examples directories]

You'll find the learning curve much shorter, and ABEL is fine
at the smaller end of the scale.

I did realize that at first, but then I promptly forgot.
Besides, I really wanted to learn VHDL for when I progress on to
bigger and better things.

 

[cdsmith69@gmail.com]

In article <43bf7a85@clear.net.nz>, no.spam@designtools.co.nz
says...

Well, I've been trying to post with google groups, but I see
that even after several tries my recent messages aren't showing
up. Who knows, maybe someday they will make it here from
google's servers. If you see multiple replies from me that are
similar, that is why. Now I've downloaded and installed a
proper newsreader so I shouldn't have to mess with google groups
anymore.

You could also move to ISE 8.1 ?
-jg

I thought about that when I saw that the update from 7.1 to
7.1.04 was something like 325 megabytes, and thought that maybe
the full 8.1 download wouldn't be much more.

But then I figured that I'd probably find a whole new user
interface that I'd have to learn, or there would be other new
bugs in the software, and I would just update to 7.1.04 and get
my CPLD working.

Does 8.1 look and work pretty much the same as 7.1?

 

[cdsmith69@gmail.com]

I tried to post this several times yesterday through google
groups and it never showed up, so I got a real newsreader
installed now. If it shows up multiple times it's google's
fault.

In article <1136560656.002159.239020
@g49g2000cwa.googlegroups.com>, news.guardiani@gmail.com says...

The solution is simple, but far from obvious. You need to
download and apply the patch for ISE 7.1 or install the
latest service pack (4). There is a bug that inverts all of
the outputs of CPLDs (with no service pack and also
maybe SP1).

Bingo. That fixed everything. After downloading the 7.1.04
update, which was something like 325 megabytes, nearly as big as
the full download, everything is working fine. My counter
counts right, the outputs aren't inverted, and I can even
directly assign pins to a value and have it work.

Xilinx has refused to post this information to their download
page. I even talked to a factory FAE and he could not get
them to post it. The only way you can find out about it is to
search their site for key words that match the article.

I spent a long time a couple nights ago searching their whole
knowledge base section and reading everything I could find on
the 9500 family CPLDs and never found this information. I only
found it after I went to the download page for the service pack,
and found the link that said something like "read this before
installing" and somewhere in there was a list of what the update
fixed, and in there was a short sentence or two saying that it
fixed an issue with CPLD outputs being inverted. It never did
mention fixing the problem where I couldn't directly assign a
pin to 1 or 0 and have it work. Either way it came out as a
high. Now it works with 7.1.04.

Right now, there isn't much I can say in polite company about
how this makes me feel. This bug has cost me several days time.
If I had been working on a real project at work, instead of
hobby tinkering at home, it would have cost the company a lot of
money in engineering time.

I think it is rather irresponsible of them to not at least have
a notice on the download page for 7.1 saying you NEED the update
to 7.1.04 if you are using CPLDs. And what they really should
have done is taken down the 7.1 update and replaced it with a
7.1.04 full download, and also have the 7.1.04 update available
for those who already have 7.1 installed.

Many thanks to you Marc, and to everyone else who posted their
ideas. Now I can get on with my original project, and maybe
have some fun and learn something with CPLDs and FPGAs.

 

[cdsmith69@gmail.com]

I tried to post this yesterday through google groups and it
looked like it went, but now it doesn't show so I'm posting
again with a real newsreader...

In article <Xhjvf.193181$V7.130092@news-server.bigpond.net.au>,
spam@tritium.com.au says...

My guess is that you haven't defined which pin on the outside of your
CPLD is connected to which signal on the inside of your CPLD. You've
ended up with random signals to random pins, defined by the fitting tool
to whatever made it's life easiest. The mapping will change every time
you modify and resysnthesise the code.

You need to add a .ucf file to your project with the signal->pin
mappings in it.

I almost did that, but not quite.

The first time I got a project to go through the synthesize and
fit I generated a programming file, and I was about to double
click on Configure Device (iMPACT) and I suddenly thought "How
does it know what pins I want my signals on?" So I looked
at the ISE quick start tutoral I had gone through a few weeks
back when I first downloaded and installed ISE and figured out
how to create UCF.

I still need to figure out how to put timing stuff into the UCF
so I an do proper timing based simulations. I went through the
ISE 7.1 quick start tutorial, but maybe I should spend some time
going through the full ISE tutorial...

 

[Rob]

Does it always happen (not dependent on running applications) or only when
you have certain applications running, like Aldec or Xilinx ISE? I'll
forward your note onto to some XP people that I know and see what I get
back. If I get back anything worth while I'll post it.

Not that I'm an XP expert, but this kind of smells like a memory (mother
board RAM) issue. Open up the Task Manager and take a look at available
system memory when you start to experience this problem, just for grins.



"Ray Andraka" <ray@andraka.com> wrote in message
news:Qhkwf.41617$Mi5.28702@dukeread07...

I've been plagues lately with my machine seeming to have a limit on the
number of documents or programs that can be opened. If I exceed that
quota, I either get the MFC "failed to create an empty document" (in Aldec
when I try to open another source file), or the application just plain not
opening with no warnings (Xilinx, for example). The limit seems to
decrease as I work, to the point where I can only have one application
open, then I have to reboot the machine.

I checked my disk array for space...there is about 160 GB of 490 GB total
occupied, so disk space shouldn't be the issue. I looked at the temp
folder, and that doesn't seem to be full either.

This is windoze XP pro.

Anybody seen this and have a cure?

 

[Ray Andraka]

Rob wrote:

Does it always happen (not dependent on running applications) or only when
you have certain applications running, like Aldec or Xilinx ISE? I'll
forward your note onto to some XP people that I know and see what I get
back. If I get back anything worth while I'll post it.

Not that I'm an XP expert, but this kind of smells like a memory (mother
board RAM) issue. Open up the Task Manager and take a look at available
system memory when you start to experience this problem, just for grins.

Rob, thanks!

Hard to tell, If I am at the computer it is because I am doing design
work, which means one or more of those apps is open. It doesn't seem to
be tied to any one of those apps though. I've seem MSword do it too
with a long document (50 page book chapter with about 50 drawings). It
is as though there is a memory leak, but it isn't showing up on the task
manager.

I haven't seen the RAM usage go over about 1.5GB (2GB RAM in the
system), and I have the paging file set to 3072MB min, 8192MB max. I've
never seen that file increase above the 3GB minimum.

 

My guess is that you haven't defined which pin on the
outside of your CPLD is connected to which signal on
the inside of your CPLD.

I almost did that, but not quite.

The first time I got a project to go through the synthesize and fit I
generated a programming file, and I was about to double click on
Configure Device (iMPACT) and I suddenly thought "How does it know what
pins I want my signals on?" So I looked at the ISE quick start
tutoral I had gone through a few weeks back when I first downloaded and
installed ISE and figured out how to create UCF.

 

My guess is that you haven't defined which pin on the
outside of your CPLD is connected to which signal on
the inside of your CPLD.

I almost did that, but not quite.

The first time I got a project to go through the synthesize and fit I
generated a programming file, and I was about to double click on
Configure Device (iMPACT) and I suddenly thought "How does it know what
pins I want my signals on?" So I looked at the ISE quick start
tutoral I had gone through a few weeks back when I first downloaded and
installed ISE and figured out how to create UCF.

 

[m]

On Mon, 09 Jan 2006 04:20:31 GMT, "Rob" <robnstef@frontiernet.net>
wrote:

Does it always happen (not dependent on running applications) or only when
you have certain applications running, like Aldec or Xilinx ISE? I'll
forward your note onto to some XP people that I know and see what I get
back. If I get back anything worth while I'll post it.

Not that I'm an XP expert, but this kind of smells like a memory (mother
board RAM) issue. Open up the Task Manager and take a look at available
system memory when you start to experience this problem, just for grins.

Actually I don't think this is a hardware issue (especially because a
reset cures it). I think some app is leaking system resources
(memory/windows/gdi handles etc) which is normally not supposed to
happen with XP. One thing which is not clear with Ray's post is
whether this continues to happen even if he closes all open apps. One
thing to try is to open task manager (ctrl-alt-del) and see if there
are any zombie processes which belong to dead applications. These may
be keeping windows/other resources in memory. Close all apps which are
not used, all processes which are not needed anymore and see if you
can recover without a reboot. Also going to
windowsupdate.microsoft.com to get the latest patches might help.

 

[backhus]

Emel schrieb:

Hi,

I designed a 7th order FIR filter using MATLAB fdatool and obtained
the VHDL code using the HDL Coder. I think that in the following part
of the code there is a problem (Delay pipe line is an 8 element
array, whose elements are 16 bit vectors. filter_in is a 16 bit
vector):

IF reset = '1' THEN
delay_pipeline(0 TO 7) <= (OTHERS => (OTHERS => '0'));
ELSIF clk'event AND clk = '1' THEN
IF clk_enable = '1' THEN
delay_pipeline(0) <= signed(filter_in);
delay_pipeline(1 TO 7) <= delay_pipeline(0 TO 6);
END IF;
END IF;

This part simply shifts previous inputs and should be saving the new
input (filter_in) into delay_pipeline(0) (which it does). However,
after delay_pipeline(0) <= signed(filter_in);, it says
delay_pipeline(1 TO 7) <= delay_pipeline(0 TO 6);.

As far as I know, the statements in a process are sequential.

So, if you change
delay_pipeline(0) right at the beginning, isn't the old value of
delay_pipeline(0) totally gone? Because, afterwards delay_pipeline(0)
(its new value) is assigned to delay_pipeline(1).

Hi Emel,
for instant relief follow Mikes advice and get yourself a simulator, you
may need it anyway sometime.

But to help you understand you should learn the difference between
variables and signals in VHDL. Signals (assigned with <= ) are updated
only at the end of each process. (look for Reader-Driver Model)
Variables are instantly updated.
What you said about sequential statements is right, but only affects
signal assignments if you assign values to the same signal like this:

Signal_1 <= '0';
if condition=true then
Signal_1 <= '1';
end if;

Here the first assignment serves as a default. The if-statement
overwrites signal_1 whenever the condition becomes true.

have a nice synthesis
Eilert

 

[Mike Treseler]

Mike Harrison wrote:

I can't figure out how to use alias to create vectors of arbitary signals...

It can be done, but I don't do it
because alias identifiers are not visible
in simulation. If the expression is
used more than once, declare and
assign a variable or signal.
....
is
variable lcdbufburst_v : std_logic_vector(2 downto 0);
begin
lcdbufburst_v := lcdbufadr(1) & lcdbufadr(0) & lcdbufadr(8);
...

-- Mike Treseler

 

[Marco]

Antti, thanks, sorry for the -2.5V, my fault! I searched on the
Spartan3 data sheet and on table 10, pag.10 of DS099-3 there seem to be
only 2.5V allowed, no 3.3V.
Marco

 

[John Adair]

Nitesh

As I thing Brian said you need to look at the chip specification. Usually
you will find a register/s location at a particular offset/s from the BAR
base address for these kind of DMA transfers but I don't have a lot recent
PLX experience to expand on that.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development
Board.
http://www.enterpoint.co.uk

"Nitesh" <nitesh.guinde@gmail.com> wrote in message
news:1136781556.613473.256380@o13g2000cwo.googlegroups.com...

I am working on drivers n the host side. I wasnt clear about few
things. I can configure the bridge from the fpga side over the
processor bus. In the manual its not stated as to how to do the data
transfer without using the on-board RAM. It only specifies how to
configure the bridge for the DMA transfer (with initiation fromthe fpga
side ) i.e to specify the start address on the on-board ram ,
destination address and the size. How do I go about tranferring the
data without using the on-board external RAM.
Is it possible?
Thanks,
Nitesh

 

[Roger]

Requires money = Buy

I don't want the webpack version as if I do decide to go for the tools, the
projects will be for the larger devices not supported by Webpack. I want to
be able to target the larger devices with my code now and run some
simulations.

I hope this is precise enough.

Rog.

"Antti Lukats" <antti@openchip.org> wrote in message
news:dptru4$otp$02$1@news.t-online.com...

"Roger" <enquiries@rwconcepts.co.uk> schrieb im Newsbeitrag
news:%guwf.64944$Cj5.57950@newsfe6-win.ntli.net...
An Evaluation version would cost me approx. USD20 in shipping. I was
wondering when the Evaluation version would be there to obtain.

Rog.

well, then be precise with wording

eval version does not have a 'buy' price,
shipping costs do apply, but it doesnt make the eval as 'purchaseable
product'

order webpack 8.1 links are there, and I assume you should be able to
obtain the webpack from online download very soon, it should actually
provide evaluation of almost all the featueres of the full ISE so try that
first in case the 8.1 eval CD order is not available yet

--
Antti Lukats
http://www.xilant.com

 

[Gilles GEORGES]

Antti Lukats wrote:

"Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag
news:dptig7$jk$01$1@news.t-online.com...

"Gilles GEORGES" <georges@irisa.fr> schrieb im Newsbeitrag
news:dpteh3$9hk$1@amma.irisa.fr...

Dear,

I received last week a Xilinx USB Platform Cable.
Using ISE 7.1.04i and EDK 7.1.2 under Fedora core 2 with kernel
2.6.6-1.435.2.3smp, the precompiled driver is not suitable.

[snip]

Firmware version = 1018.
CPLD file version = 0006h.
CPLD version = 1648h.

that is weird on WinXP the file version and CPLD version are the same as
displayed

sorry I meant displayed should be

CPLD file version = 0006h.
CPLD version = 0006h.

antti



Dear Antti,

I just tried the cable with same board on a Win XP computer and it
works. I previously downgrade to cpld firmware V4 (taken in a ISE 6.3
linux install) => not working under linux but working under windows.
Then i upgrade to version 6 and still working under windows.

Going back to my Linux workstation nothing works.

There is a strange thing with Impact, the "CPLD version" differs with
the "CPLD file version" while the two match on Windows.

Connecting to cable (Usb Port - USB22).
Checking cable driver.
File version of /local/xilinx/bin/lin/xusbdfwu.hex = 1018(dec), 03FA.
File version of /etc/hotplug/usb/xusbdfwu.fw/xusbdfwu.hex = 1018(dec), 03FA.
Max current requested during enumeration is 150 mA.
Cable Type = 3, Revision = 0.
Setting cable speed to 6 MHz.
Cable connection established.
Firmware version = 1018.
CPLD file version = 0006h.
CPLD version = 0021h.

Any idea.

Gilles