EDK : FSL macros defined by Xilinx are wrong

Hallo gerald,

This is not recommended.You may use ISE webpack freely as long as you
want.You may download it from
http://www.xilinx.com/ise/logic_design_prod/webpack.htm

Cheers,
Monica
 
Parkov wrote:

I'm looking at doing some basic CPLD designs via Schematic Entry. Who
has easier to learn/use schematic entry software, Xilinx or Altera?
Click to expand...
Altera Quartus.

-- Mike Treseler
 
Parkov,

I would invest my time in learning a HDL: VHDL or Verilog.

Schematic entry for logic design is (almost) completely dead. It has
become rare to find anyone doing anything in schematic form, except for
the highest level where the pins are connected.

All of the levels of logic are described in hardware design language
(HDL) modules.

To pick a vendor based on their 'schematic tool' is probably the least
interesting criteria.

Picking the vendor based on:

-available technology
-speed
-power
-features
-cost
-size
-package
-ease of use of software tools
-available synthesis tools
-available simulators
-FAE support
-web support
-part availability

all makes sense.

Austin
 
Austin Lesea wrote:

I would invest my time in learning a HDL: VHDL or Verilog.
Click to expand...
Good advice, but allow several months.

Schematic entry for logic design is (almost) completely dead. It has
become rare to find anyone doing anything in schematic form, except for
the highest level where the pins are connected.
Click to expand...
The one place it isn't dead is for
circuit-board oriented, first-time
cpld users copying some glue logic
off of an application note.

-- Mike Treseler
 
The one place it isn't dead is for
circuit-board oriented, first-time
cpld users copying some glue logic
off of an application note.
Click to expand...
Thats about where I'm at. No worries, I'm checking out the two HDL
variants, just wanted to get a couple things rolling fast in the
meantime. I'm coming from a 74xxx chip to chip background so I already
have some designs on paper. Thanks for the heads up everyone on the
Quartus recomendation.
 
Mike Treseler <mike_treseler@comcast.net> wrote:
Austin Lesea wrote:

I would invest my time in learning a HDL: VHDL or Verilog.

Good advice, but allow several months.
Click to expand...
But schematic entry oftem leads to non-registered designs, where you should
allow several month of debugging too...
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
 
Hi Jim.

As far as I can forsee, all that I would need are either Altera
EPM3032A/3064A's or Xilinx's XC9536/XC9576 both in 44pin packages.

If I went into a Boolean Equation Language, is ABEL or AHDL easier to
learn/use? I can't seem to find any head to head comparisons. Is
Xilinx going to continue support for ABEL for their CPLD's and is
Altera going to continue support for AHDL for theirs? I know that
these are not practical languages for complex FPGA design, but that
doesn't need to be the issue. Tks.
 
Parkov wrote:

Hi Jim.

As far as I can forsee, all that I would need are either Altera
EPM3032A/3064A's or Xilinx's XC9536/XC9576 both in 44pin packages.
Click to expand...
Atmel's ATF1502 / 1504 would also be in that category.
( as would Lattice MACH4000 series )
Why not also the Coolrunner ?

If I went into a Boolean Equation Language, is ABEL or AHDL easier to
learn/use? I can't seem to find any head to head comparisons. Is
Xilinx going to continue support for ABEL for their CPLD's and is
Altera going to continue support for AHDL for theirs?
Click to expand...
Good questions, someone in Xilinx / Altera / Lattice could answer that ?

I do know from a 'tough' Xilinx.ABEL user, that Xilinx improved their
ABEL flows, for CPLDs in recent releases - In their ABEL flow they now
use (IIRC) VHDL as the 'back end' and ABEL as the front end.

This allows them to hook-into timing simulation tools, but does
loose ABEL's test vector generation ? (useful only on smaller packages)

One they have that, of course, then 'continued support' is inherent,
as the ABEL is only a front end.

That can't have been trivial to do, so I was impressed - but it does
indicate how much CPLD code is out there, in ABEL/Boolean EQN.

In a similar vein, of using HDL's as 'back ends languages', see Jan
Decaluwe's posting today of MyHDL : Python -> Verilog.

-jg
 
Jim Granville wrote:
If I went into a Boolean Equation Language, is ABEL or AHDL easier to
learn/use? I can't seem to find any head to head comparisons. Is
Xilinx going to continue support for ABEL for their CPLD's and is
Altera going to continue support for AHDL for theirs?


Good questions, someone in Xilinx / Altera / Lattice could answer that ?
Click to expand...
Further to this, I went to the Lattice web site
http://www.latticesemi.com/products/designsoftware/isplever/ispleverstarter.cfm

It says
"ispLEVER-Starter Primary Module (212 MB)
This module is required to run the ispLEVER Starter software, and should
be installed first. It includes the ispLEVER Project Navigator, and all
the tools and device libraries you need to implement a design in
Lattice's newest and most popular CPLD products. Note: This module
supports ABEL, EDIF and Schematic design projects only. For Verilog or
VHDL design project support, you must download one of the Synthesis
modules listed below."
....

Device Support

FPGA:
LatticeECP: ECP6
LatticeEC: All
LatticeXP: XP3, XP6

CPLD:
MachXO: All
ispMACH 4000
ispXPLD 5000MX

So, since MachXO is clearly in the "newest and most popular CPLD
products" category, this web page is saying ABEL support
for MachXO is there.

Call me cynical, but I'd believe that more if a Lattice FAE was able
to verify that ?

-jg
 
It's an interesting question though. I can't remember what exactly happens
when I installed my ISE. Does the SW get a validation from the Web or
something or would a fresh installation simply work again on another
machine? If so it's a bit weak of Xilinx since they charge so much for ISE
Foundation.

Rog.

"Monica" <monica_dsz@yahoo.com> wrote in message
news:1136397969.354645.215170@g44g2000cwa.googlegroups.com...
Hallo gerald,

This is not recommended.You may use ISE webpack freely as long as you
want.You may download it from
http://www.xilinx.com/ise/logic_design_prod/webpack.htm

Cheers,
Monica
Click to expand...
 
cdsmith69@gmail.com wrote:

So I need some help getting started with programmable logic and VHDL.

In the past all I have done in the programmable logic area are 16V8 and
22V10 PALs.

I actually feel kind of stupid about the simple questions I am about to
ask, since it isn't like I don't know a lot about electonics. I have a
BSEE and in the past I've designed DSP boards and motor controllers
that control hundreds of amps and make electric forklifts able to lift
thousands of pounds. Pretty fun stuff actually.

But I am stumped by a few simple things with VHDL, Xilinx ISE 7.1, and
the Xilinx XC9536XL experimenter board I am using.
Click to expand...
What did you use to design the 16V8/22V10's ?
Why not use ABEL, for the 9536 ?

-jg
 
What did you use to design the 16V8/22V10's ?
Why not use ABEL, for the 9536 ?
-jg
Click to expand...
Most commonly was ICT pals with their WinPlace software, but I did use
some AMD pals and their ABEL software, way back in about 1995.

Neither of these programs will work for the 9536.
 
In the current release (ispLEVER v5.1) the MachXO device family does
require a Verilog HDL or VHDL synthesis front-end like Precision RTL or
Synplify. You can use the schematic editor, however, there's currently
no library for gate-level design so it's best used as a block-diagram
editor. In the design flow the schematic editor produces a structural
model that's read by logic synthesis. I use it today with the latest
FPGA families (including XO):to organize RTL modules or those modules
generated from IPexpress the module/IP core manager.

Meanwhile another option for someone who's trying to migrate a
74xx-class design is a 3rd party EDA schematic front-end like Aldec,
Altium (Protel), or Orcad which can also generate EDIF 2 0 0 or
structural HDL you can import into FPGA tools. Altium in particular is
focused on making this "board-level" design style easy.

Troy Scott
Lattice Semiconductor TME
 
On Wed, 4 Jan 2006 22:08:26 +0000 (UTC), Uwe Bonnes
<bon@hertz.ikp.physik.tu-darmstadt.de> wrote:

Mike Treseler <mike_treseler@comcast.net> wrote:
Austin Lesea wrote:

I would invest my time in learning a HDL: VHDL or Verilog.

Good advice, but allow several months.

But schematic entry oftem leads to non-registered designs, where you should
allow several month of debugging too...
Click to expand...
Why? Logic is logic. We do lots of complex designs, state machines and
all, in schematic form, and they come up in days or hours.

John
 
Hi,

The encoding is handled by the PHY. Are you implementing the PHY on an
Fpga?

Alan
 
Why don't you use a Gigabit PHY (for example Marvell 88E1111) ?
Then you only have to care about the interface FPGA <--> PHY.

Rgds
André
 
My understanding is that you can only load once each line that's it ...
 
yes I am trying to look at if I can implement an ethernet multiplexer
in FPGA

if you have any info please forward it to me.

thanks & regards
Kedar
 
On Fri, 6 Jan 2006 08:52:13 +0000 (UTC), Uwe Bonnes
<bon@hertz.ikp.physik.tu-darmstadt.de> wrote:

John Larkin <jjlarkin@highnotlandthistechnologypart.com> wrote:
On Wed, 4 Jan 2006 22:08:26 +0000 (UTC), Uwe Bonnes
bon@hertz.ikp.physik.tu-darmstadt.de> wrote:

Mike Treseler <mike_treseler@comcast.net> wrote:
Austin Lesea wrote:

I would invest my time in learning a HDL: VHDL or Verilog.

Good advice, but allow several months.

But schematic entry oftem leads to non-registered designs, where you should
allow several month of debugging too...

Why? Logic is logic. We do lots of complex designs, state machines and
all, in schematic form, and they come up in days or hours.

If you do registered designs and don't relay on some function having some
definite delay, things will be fine. However many TTL designs are created
different...
Click to expand...
Sure, one can do nasty async design in schematics, or in VHDL for that
matter. But S/360 and Cray and the HP35 and moon rockets were designed
before HDLs, and they worked fine. Some people were good at logic
design a long time before FPGAs were invented.

I don't have time to learn an HDL. I read the Xilinx book, draw
schematics (on paper!), and hand them to a minion to enter and
compile. Works great.

John
 
John Larkin wrote:

Sure, one can do nasty async design in schematics, or in VHDL for that
matter. But S/360 and Cray and the HP35 and moon rockets were designed
before HDLs, and they worked fine. Some people were good at logic
design a long time before FPGAs were invented.

And some people are still quite lousy with logic design despite having
Click to expand...
FPGAs and the best HDLs. HDLs do not make a good logic designer, they
are simply a tool.
 
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