EDK : FSL macros defined by Xilinx are wrong

[Brian Drummond]

On 5 Dec 2005 14:21:02 -0800, juendme@yahoo.com wrote:

Second, since obviously not everyone here knows enough about binary
arithmetics to understand my questions, let me illustrate on an example
of adding/subtracting 2 3-bit signed numbers:

Using 2's complement representation, we can represent the following
numbers with 3 bits:
[...]

To store the valid result, we only need 4 bits.

However, if one of the numbers is unsigned, 4 bits are not enough. We
can illustrate that using the following example:

Clearly if you add two sign bits together, you can store the result in
.... one sign bit.

And the surprise of this is ... ?

- Brian

 

glen herrmannsfeldt wrote:

porterboy76@yahoo.com wrote:

I am looking for the homepage of Xilinx Research Labs, but Google is
not helping me. Does anybody know if they even have a homepage. I'd
like to know what type of research they do at Xilinx, whether it is all
at the solid state and IC level, or whether they undertake higher level
algorithmic research as well.

Post to comp.arch.fpga and ask there.

-- glen

 

[Austin Lesea]

Xilinx Research Labs -

has an internal webpage (visible only to Xilinx employees on our network).

All of the information therein is marked confidential.

If you have interest in applying for employment (summer intern, or
regular position) with Xilinx, please forward your resume to our website
HR links.

Or, you may send it to me, and I will forward it to the appropriate person.

Please do not send anything if a position is not already open (ie
posted) on the website.

If you are associated with a school, university, or other research lab
and wish to join us in research, obtain hardware or software; please
contact:

http://www.xilinx.com/univ/

(xup@xilinx.com)

Thank you for considering Xilinx,

Austin

porterboy76@yahoo.com wrote:

glen herrmannsfeldt wrote:

porterboy76@yahoo.com wrote:


I am looking for the homepage of Xilinx Research Labs, but Google is
not helping me. Does anybody know if they even have a homepage. I'd
like to know what type of research they do at Xilinx, whether it is all
at the solid state and IC level, or whether they undertake higher level
algorithmic research as well.

Post to comp.arch.fpga and ask there.

-- glen

 

[Steven Derrien]

Austin Lesea wrote˛ :

If you are associated with a school, university, or other research lab
and wish to join us in research

Hi,

I had a glance to the XUP webpage, but it mostly focus on teaching
resources.

Let's say "I have a friend of mine" who is an academic considering
going for a sabbatical, and who would be *very* interested to join
Xilinx Labs during that time, should I also go through this channel ?

Thanks in advance,

Steven

, obtain hardware or software; please
contact:

http://www.xilinx.com/univ/

(xup@xilinx.com)

Thank you for considering Xilinx,

Austin

 

[Ray Andraka]

Simon Peacock wrote:

You may want to check the stockings by the fireplace.

Simon

"Antti Lukats" <antti@openchip.org> wrote in message
news:dn20o1$t57$1@online.de...

ISE 8.1 release was planned for mid nov, now its mid december soon, I

wonder...

I got 8.1 this morning by electronic delivery. I haven't tried
installing it yet. I'll wait till I have the current projects out of
the way before subjecting myself to being a guinea pig again.

 

[Austin Lesea]

Steven,

Please have them email me directly, and I will put them in touch with
the right person.

We definitely enjoy having talented faculty spend time here (or in our
new 'EU research centre' in Dublin).

Austin

Steven Derrien wrote:

Austin Lesea wrote˛ :


If you are associated with a school, university, or other research lab
and wish to join us in research


Hi,

I had a glance to the XUP webpage, but it mostly focus on teaching
resources.

Let's say "I have a friend of mine" who is an academic considering
going for a sabbatical, and who would be *very* interested to join
Xilinx Labs during that time, should I also go through this channel ?

Thanks in advance,

Steven

, obtain hardware or software; please contact:

http://www.xilinx.com/univ/

(xup@xilinx.com)

Thank you for considering Xilinx,

Austin

 

Hi, I was just wondering some technicalities about a board.

Ive got the XUP virtex-II pro from digilent and I believe it was
designed by the XRL.
Well I was wondering what kind of CAD (schematic capture + pcb layout)
software does the team used. And also, out of curiosity, what PCB
manufacturer do they use and the number of layers involved. A friend of
mine thinks it's around 12. Which I doubt. So to make things clear, I
am asking the experts here.

Thanks for the tip, but im impressed by the job and I wanna know what
it takes to do that.

JA

Steven Derrien wrote:

porterboy76@yahoo.com a écrit :
glen herrmannsfeldt wrote:

porterboy76@yahoo.com wrote:


I am looking for the homepage of Xilinx Research Labs, but Google is
not helping me. Does anybody know if they even have a homepage.

Hi,

They used to have one (well, Satnam Singh had his page until he left
Xilinx).

I'd like to know what type of research they do at Xilinx, whether it is all
at the solid state and IC level, or whether they undertake higher level
algorithmic research as well.

From what I know (i.e. academic perspective) Xilinx folks mostly focus
on higher level problems (system level design, hardware compilation,
runtime reconfiguration, etc.).

If you want to have more details have a look to some FPGA related
academic conference proceedings such as FPL or FCCM, you will
probably find some papers by people from Xilinx.

Besides, I am sure that Peter Alfke and Austin Lesea will be glad to
answer your questions.



Post to comp.arch.fpga and ask there.

-- glen

 

[GaLaKtIkUs™]

Which distrib do you use ?
In Fedora Core 4 it works fine.
I had a problem trying the first time to install it from an NFS share.
But uncompressing the files to a LOCAL location solved the problem.

 

[Andy Peters]

Antti Lukats wrote:

ISE 8.1 release was planned for mid nov, now its mid december soon, I wonder
if it is known how much more the ISE 8.1 release is delaying? Xilinx is
advertising ISE webcast on Dec 14, I wonder if that will only cover soon to
be obsoleted 7.1 or be focused on 8.1?

Actually I am more waiting for the EDK 8.1 in the hope DDR2 support is
added, but as EDK 8.1 release was projected 4 weeks after ISE 8.1 release I
guess the EDK 8.1 actuall release date is slipping also most likely into
2006?

I suppose the better question is, "when will the first service pack be
available?"

-a

 

[Symon]

I suppose the better question is, "when will the first service pack be
available?"

Andy,

It's a brave (or possibly desperate) man who dives in before SP3! ;-)
Cheers, Syms.

 

[Symon]

I suppose the better question is, "when will the first service pack be
available?"

Andy,

It's a brave (or possibly desperate) man who dives in before SP3! ;-)
Cheers, Syms.

 

[Stephen]

Porterboy76, Glen, and Others,
I work in Xilinx Research for our CTO and would very much like to hear
of any external research or sabbatical proposals you may have. You can
send them directly to me and I'll follow up with you outside of this
news group.
Incidently, I read this newsgroup infrequently.
Regards,
Stephen
Ps we don't have an external web page, yet, but we are evaluating
options, so please send us suggestions if there's something specific
you'd like to see.

porterboy76@yahoo.com wrote:

glen herrmannsfeldt wrote:
porterboy76@yahoo.com wrote:

I am looking for the homepage of Xilinx Research Labs, but Google is
not helping me. Does anybody know if they even have a homepage. I'd
like to know what type of research they do at Xilinx, whether it is all
at the solid state and IC level, or whether they undertake higher level
algorithmic research as well.

Post to comp.arch.fpga and ask there.

-- glen

 

[Jim Granville]

Andy Peters wrote:

Antti Lukats wrote:

ISE 8.1 release was planned for mid nov, now its mid december soon, I wonder
if it is known how much more the ISE 8.1 release is delaying? Xilinx is
advertising ISE webcast on Dec 14, I wonder if that will only cover soon to
be obsoleted 7.1 or be focused on 8.1?

Actually I am more waiting for the EDK 8.1 in the hope DDR2 support is
added, but as EDK 8.1 release was projected 4 weeks after ISE 8.1 release I
guess the EDK 8.1 actuall release date is slipping also most likely into
2006?


I suppose the better question is, "when will the first service pack be
available?"

and an even better one.... "When will it be safe to unleash on legacy
designs ? "

-jg

 

[reidek@gmail.com]

Austin,

If it's not obvious, I'm new to this, so bear with me.

One of the things that I need to be able to do is create a calibration
table. The PPC would read a few values from the FPGA, and create a 8K
or so table, which seems to be within the limits of the ultracontroller
II. What I'm not sure of is whether the FPGA has access to the caches,
or whether I can write to some other block RAM with the PPC that the
FPGA would have access to.

Sorry if this isn't quite making sense. I'm a software guy and haven't
worked with this stuff in a few years. Eventually, another team member
will be writing the VHDL/firmware and I'll be writing the software that
runs on the PPC. I've been tasked with figuring out how to program the
PPC and interface it with the firmware. No one at the company has done
this type of thing before, so I'm breaking "new ground".

Eric

 

[Jim Granville]

Kryten wrote:

svasus@gmail.com> wrote in message
news:1133949644.536667.201480@z14g2000cwz.googlegroups.com...

So I was hoping to find a chip which would sandwich between the FPGA
and I2C interface.
Searched on the net but could not find any.


That should tell you something then.

Like nobody does it that way, for good reasons.

There are some controller chips but you have to write code to use them.
And if you can do that, you might just as well write the code to bit-bash
the I2C interface. Come on, it isn't that hard to do.

That depends - if you want to bit-bash, on a FPGA that infers a
SoftCPU, and that is resource intensive.
First, you need to have this CPU, then you need the time/code resource
to service i2c.

Also, i2c slave is non trivial, and the external chip does it already
( or, the OP might need 5V compliant i2c, not so easy on FPGAs ! )

Thus a parallel controller could be INIT and serviced with a simple
statemachine, but I would favour a small uC as a SPI-i2c buffered
bridge, as that can be smarter, and has less pin-cost
( but that does have another development cycle of its own)

-jg

 

[Eric Smith]

vasudev srinivasan wrote:

I am needed to talk with a microcontroller through an I2C interface
from my FPGA. I dont want to write a code for it as well not use an
opensource core. This is partly due to space constraints and testing.
Speed and cost are not constraints.
So I was hoping to find a chip which would sandwich between the FPGA
and I2C interface.

Antti Lukats wrote:

there is no such thing.

Certainly there is! Look for the Philips PCF8584 or PCA9564.

 

[Ray Andraka]

I2C is not particularly resource intensive, especially if only a subset
of the full spec is used. It can be incorporated in the FPGA fabric
without a huge development effort, and with modern FPGAs is going to
take but a small corner of the FPGA. For the slave side, which it
sounds like you are, the decode and data steering is probably bigger
than the shift register and state machine.

 

[ylc199]

ylc199 wrote:
Hi

I have a Stratix EP1S80 DSP development board. However, i am not able
to
get the ADC or the DAC devices on the board to work. What i am trying
to
do is simply send an analog waveform (eg 1 khz sine wave) into the adc
and
then try to recover the waveform with the DAC. Can anyone please
kindly
advice on this or even better if anyone have a design example that can
email me? Thanks

I remember a colleague having had his problems too.
The local Altera distributor was of a great help
on the phone.

Rene
--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

It has been a week and the local altera distributor hasn't reply. Still
with a some luck i finally got it to work; problem solved. Thanks

 

[Antti Lukats]

"Eric Smith" <eric@brouhaha.com> schrieb im Newsbeitrag
news:qhfyp45x0x.fsf@ruckus.brouhaha.com...

vasudev srinivasan wrote:
I am needed to talk with a microcontroller through an I2C interface
from my FPGA. I dont want to write a code for it as well not use an
opensource core. This is partly due to space constraints and testing.
Speed and cost are not constraints.
So I was hoping to find a chip which would sandwich between the FPGA
and I2C interface.

Antti Lukats wrote:
there is no such thing.

Certainly there is! Look for the Philips PCF8584 or PCA9564.

no there isnt - the overhead for interfacing external i2c controller is
larger than the sw needed to implement the i2c in softwre only so from that
point of view there is no easy solution that makes the fpga sides simpler.

implementing i2c in fpga in hw or sw is simpler than interfacing PCFxxx pr
PCAxxx

so there is no easy sandwitch-chip

Antti
PS look at other posters they say the same thing I did.. and YES I do know
the existance of the silicon you mentioned.

 

[Thomas Stanka]

code in TESTBENCHES.
If there are many other ways of testing and validation which i'am
unaware of PLEASE let me know.

Code review, testbenches, static timing analyses and formal
verification are the major verification tasks. Don't know which of them
makes sense for your designs and team.

One last doubt, in verification, do we even work on STATIC TIME
ANALYSIS and SYNTHESIS. or this is done by the designer itself..

How could we know if you don't? STA is usually perfomed after layout,
has your designer feedback from layout? Do you have to verify after
layout or are you only responsible for functional verification until
synthesis?

bye Thomas