EDK : FSL macros defined by Xilinx are wrong

[Raymund Hofmann]

"Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag
news:dki76s$cb1$1@online.de...

Why Spartan-3e is the best
==================
Antti Lukats
4.Nov 2005

[lot's of indispensable 3e advantages snipped]

6) There are possible some other nice new features
I have not discovered yet

Yes, you forgot to mention the extra fun you may have with the DCM / DFS

90MHz && <220MHz.

Raymund Hofmann

 

[Gabor]

Krzysztof Przednowek wrote:

g.wall napisal(a):
im trying to reverse engineer a windows driver
for a PCI fpga development board so i can use it on a linux machine
(write my own driver)
all i need are the command and control signals
in order to configure, do dma, reset, etc...
i need to capture these things as they are being sent from
the windows kernel to the PCI bus, then to the pci bridge on the board.

anyone have any ideas?

If You have PCI board with FPGA, RAM and some inferface to second PC, it
would be easier to do it in hardware.

Best Regards
Krzysztof Przednowek

Easiest is to get hold of a VMETRO or CATALYST PCI bus analyzer. You
can
probably rent one.

 

[John Adair]

Have a look at this Xilinx publication
http://www.xilinx.com/publications/products/cpld/logic_handbook.pdf . There
are also handbooks for Spartan-3 etc that go into the architecture but you
may have to pay for those (about $10).

John Adair
Enterpoint Ltd. - Home of Raggedstone1. The Cheap Spartan-3 Development
Board.
http://www.enterpoint.co.uk

"Okashii" <nordicelf@msn.com> wrote in message
news:438e3387$1@news.starhub.net.sg...

Hi there, pardon me but I'm a newbie at fpga and stuff. I was using Xilinx
ISE and vhdl to build some components and no matter what the size of
component I keep getting "number of bonded iob" exceeded. Then after some
observation I finally realized that its the size of bits of the ports of
the top level component . May I know where I can find layman information
on fpga online that explains what are "slices, slice flip-flops, LUT, IOB"
and all these?
Thanks in advance!

 

[Eli Hughes]

http://www.fpga4fun.com/


Okashii wrote:

Hi there, pardon me but I'm a newbie at fpga and stuff. I was using Xilinx
ISE and vhdl to build some components and no matter what the size of
component I keep getting "number of bonded iob" exceeded. Then after some
observation I finally realized that its the size of bits of the ports of the
top level component . May I know where I can find layman information on
fpga online that explains what are "slices, slice flip-flops, LUT, IOB" and
all these?
Thanks in advance!

 

[damir]

Nice solution!

"Arlet" <usenet+5@ladybug.xs4all.nl> wrote in message
news:1133294098.430743.59950@g14g2000cwa.googlegroups.com...

damir wrote:
I need to implement slow FIFO (16-bit wide, max. 10 MHz) using external
single-port SRAM connected to the FPGA (Spartan II/III).

Does anyone have similar FIFO controller (sync/async) implemented using
VHDL?

Thanks,

Damir

I would put two small FIFOs on the FPGA, and then have a simple,
synchronous state machine to control the external RAM. The state
machine would look at how full/empty the FIFOs are, and based on their
priority determine whether it will do a either a read or write access
to the external RAM.

If you need an asych FIFO, then use one of the on-chip FIFOs to cross
the clock domains, and keep the rest on the same clock.

 

[JarJarJP12]

Nanditha -

You rock! Thanks, that solved that issue and has allowed me to
simulate the sample test of the Aurora core. Now I'm trying to
incorporate a Coregen created Aurora core into an existing project, but
it doesn't seem to like me doing this. I have an existing project in
ISE and I add the <aurora_core>.xco. Whenever I try to view the HDL
Functional Model it regenerates the core but does not display the HDL.
Whenever I double click on Manage Core, it invokes Coregen but then
says that my device is not the virtex-4 and thus does not have the
Aurora Core. The specific error is:

ERROR:sim:160 - Could not find requested IP (Aurora,2.3) for currently
selected part.

I go to project options and it displays that my device is not virtex-4
but Automotive Coolrunner2. I change it to the correct device, but
this does nothing. Any idea why this is?

Also, I've noticed in the sample_test of the Aurora core that it uses
the GT11_custom instantiation. This leads me to believe that if I use
a GT11_custom core via Architect Wizard and have the attributes match
those of the Aurora Core it would work in the same fashion. Is this
true?

Thanks again for all your help!

JP

 

[Dave Pollum]

juendme@yahoo.com wrote:

I'm trying to build a simple ALU with an adder/subtracter unit and I
need both carry and overflow outputs to set the appropriate flags.
However, CoreGen (6.3) doesn't let me have both carry and overflow
outputs. I really don't understand why.

Xilinx designers should think twice before limiting their users in such
a stupid way. Just because you don't see why someone would want both
outputs, doesn't mean that somebody won't find an application that may
require them. If you think that doesn't make sense, fine; that's what
we have warnings for. Warn me that the value of overflow is meaningless
for unsigned numbers, but don't prevent me from using it.

For instance, in this case, I don't know whether the user will
add/subtract signed or unsigned numbers!!! It's up to them to decide,
and then it's up to them to look into the appropriate flag. Except that
I can't provide that flag using this core. Now I have to do it
manually, which will most likely be less efficient. And then I'll
compare it with Altera's LPM, which will of course be more efficient.

Frustrated,

Fred

P.S.

For those that don't believe that this is the case, you can see it for
yourself in the following document:
http://www.xilinx.com/ipcenter/catalog/logicore/docs/addsub.pdf (Table
2)

I use ISE-WebPack, so I guess I don't have CoreGen. I'm still just out
of the VHDL newbie stage, but if I understand the document's table #2,
it doesn't look like CoreGen will build an adder/subtractor that
handles _both_ signed and unsigned data. At least I didn't see a "pin"
that tells the logic to treat the data as signed or unsigned. If all
that's true, it looks like you'll have to roll your own.
-Dave Pollum

 

[Russ Panneton]

Dave Roberts wrote:

Dear all,

I place a timing constraint on a pair of registers (from, to) either side of
some logic. After I run the ISE 6.3 toolchain, I look at the actual delays
for the constraint in Timing Analyzer.

The constraint seems to have been applied from the source register which I
specified as my destination, to a register or pad elsewhere in the design.
The constraint is applied to logic other than specified.

Any suggestions?

Cheers,

Dave.

Can you check the PCF to see if the FROM TO still references the correct
register pair?

Russ

 

[Eric Smith]

I asked about the possibility of LUT output glitches, and
Peter Alfke replied:

Good question, often asked:
No glitch, and that behavior is guaranteed by the decoding structure.
[...]
I have answered this particular question many times over the past 15
years.

Sorry to bring it up for the umpteenth time, then, but thanks for the
answer.

Should I have been able to figure this out from the data sheet or other
documentation? The description of the Function Generator on page 12
of DS099-2 v1.4 (Spartan 3 functional description) didn't make it clear
to me that I could count on a LUT being glitchless.

Are the FxMUX multiplexers similarly designed for glitchless transitions?

(For those that aren't aware of it, some simple 2:1 mux designs are
suceptible to glitches when switching between inputs that are the same
state. For instance, if you use two AND gates, an inverter, and an OR,
you can have a glitch to 0 when switching between two inputs that are 1.
If a CMOS mux is implemented with two transmission gates, this shouldn't
occur unless output loading affects the output state while both TGs are
open.)

Eric

 

[Eric Smith]

I asked about the possibility of glitches on LUT outputs. Peter gave
a definitive response, and Symon wrote:

You got a good answer from Peter. However, my smarty pants response is to
never put yourself in a position where you care what the answer is! You'd
never clock a FF from the output of a LUT. Would you? ;-)

I fully agree; my designs are fully synchronous.

The reason the whole question came up is that a friend is trying to
cram old TTL logic designs into an FPGA without redesigning them to
be synchronous, so he has latches, S-R flops, and other horrible stuff.
I was wondering whether an S-R flop implemented as two cross-coupled
gates using a LUT for each gate could even be guaranteed to function
correctly; if LUTs can have output glitches they would not.

I'm still trying to convince my friend that his approach is likely to
cause him much grief.

Eric

 

[Austin Lesea]

Eric,

Some comments on glitches:

Because the LUT is really more than one stage of multiplexing, the last
stage has the fastest response, with the least glitching (or none at
all, depending on how such mux'ing is actually accomplished, ie pass
gate mux, or logic mux).

The FMUX is similar, in that the last stage will always result in the
least possibility of changes occuring leading to intermediate states.

Last stage is a relative term, as last is what you make it by how you
use it. If you never change an input on the real last stage, the 'last
stage' becomes the previous one with an input that selects.

Earlier product families treated all LUT input delays equal, as the
routing couldn't really take advantage of using the more detailed
information. I believe now in FPGA Editor for V4 you see the different
delays on each input.

With more advancements in software, one can use the individual delays to
advantage and get better performance, and also less glitch power (power
aware routing).

Getting all the delays to all stages of mux in the LUT from the previous
stages of logic is a nightmare only suitable for a computer to crunch
on. How valid it will be over all process/voltage/temperature is
another practical matter. Claiming "glitch free" for all corners is
something I don't feel comfortable with (as I don't control the inputs
nor their possible timing), but claiming minimal glitching is OK (or no
glitches while transitioning when input delays are fixed and known).
Especially when in a synchronous system, the only penalty of glitches is
slightly more power as lines get charged/discharged/charged....

Now how much less power, and how much better performance is something
that is often claimed (and disputed) so I won't go into that except to
say there is some possibility here for improvements.

Those that have hand routed designs to squeeze the most performance (or
least glitching power loss) seem to feel that this is worth it.
Theoretically it also seems to be valid.

Austin


Eric Smith wrote:

I asked about the possibility of LUT output glitches, and
Peter Alfke replied:

Good question, often asked:
No glitch, and that behavior is guaranteed by the decoding structure.

[...]

I have answered this particular question many times over the past 15
years.


Sorry to bring it up for the umpteenth time, then, but thanks for the
answer.

Should I have been able to figure this out from the data sheet or other
documentation? The description of the Function Generator on page 12
of DS099-2 v1.4 (Spartan 3 functional description) didn't make it clear
to me that I could count on a LUT being glitchless.

Are the FxMUX multiplexers similarly designed for glitchless transitions?

(For those that aren't aware of it, some simple 2:1 mux designs are
suceptible to glitches when switching between inputs that are the same
state. For instance, if you use two AND gates, an inverter, and an OR,
you can have a glitch to 0 when switching between two inputs that are 1.
If a CMOS mux is implemented with two transmission gates, this shouldn't
occur unless output loading affects the output state while both TGs are
open.)

Eric

 

[Peter Alfke]

Your friend's TTL designs must be really old. As early as 1969 (when I
was at Fairchild Applications) we touted synchronous design with 4-bit
synchronous counter/registers (the 9310 and 9316, copied by T.I. and
called the 74160 and 74161) and other register-oriented logic.
Enlightened circles frowned upon making latches out of gates, as early
as 1968.

BTW, you can build a latch out of one single LUT, by feeding its output
back to its input. Then you have 3 control inputs, and you can make
them be anything you wish, D, S, R, Enable and even clock...
Things for a lazy afternoon, not for serious business...
Peter Alfke

 

[Brad Smallridge]

Hi Okashi,

I found the tutorial at XESS.COM very useful when I was just starting out.
That was a year or so ago and things change. Seems like you are having
trouble
with pin IO counts, however, so you should go to the Xilinx site and look
for there
comparative data. Or just ask the group, we'll size it.

Brad Smallridge
aivision.com

"Okashii" <nordicelf@msn.com> wrote in message
news:438e3387$1@news.starhub.net.sg...

Hi there, pardon me but I'm a newbie at fpga and stuff. I was using Xilinx
ISE and vhdl to build some components and no matter what the size of
component I keep getting "number of bonded iob" exceeded. Then after some
observation I finally realized that its the size of bits of the ports of
the top level component . May I know where I can find layman information
on fpga online that explains what are "slices, slice flip-flops, LUT, IOB"
and all these?
Thanks in advance!

 

[maps]

@ et oui cal moe

 

[Peter Alfke]

Just to get back to the original question (which was kind of academic):
my answer still stands. The muxing inside the LUT is done by pass
transistors, and the internal capacitance holds the value during
non-overlapped switching. So: no glitches.
Austin describes glitching in a more general sense, and then mentions
on the delay differences of different LUT address inputs. Good info,
but does not contradict my statement.
Peter Alfke

 

Hi All,

I haven't seen much replies on My Questions ...?
are they too foolish or every body is too busy in there works

can anybody please tell me or guide me to some sites documents or books
on the implementation of Ethernet Multiplexers

Kedar

 

[Simon Peacock]

There's no real point when you can buy a switch IC for $20. Its less than
the cost of the FPGA and includes the PHY.

We actually use a Marvell ... which will even allow clocks to be sourced
from the FPGA instead of the other way around. Its so simple and gives 4
ports + CPU + FPGA... no need to even worry. That way you don't have to
worry about filtering, forwarding, VLANs, priorities etc.

P.S. Almost all Ethernet switching IC's are under NDA as the companies are
paranoid about someone stealing their design.

Simon


<kedarpapte@gmail.com> wrote in message
news:1133417075.151227.174060@g44g2000cwa.googlegroups.com...

Hi All,

Can anyone please tell me about some good links or documents paprs etc.
on Implementing Ethernet Multiplexers using FPGAs

THanks & Regards
Kedar

 

[Simon Peacock]

You will probably find that the 'Carry' uses the dedicated Carry logic.. it
therefore can support only one function.
Two support more.. one has to be done in LUT's that makes it harder.

You could build your own by hand coding LUT's... its a bit of a pain but tit
can be more optimal than writing A <= A + B; in VHDL.

Simon



<juendme@yahoo.com> wrote in message
news:1133474129.086453.274910@g14g2000cwa.googlegroups.com...

Such pins do exist (see Table 1.; signals A_SIGNED and B_SIGNED),
although I have no idea what exactly those signal do (thanks to
incomplete documentation). Because if you look into any digital design
textbook, you'll see that the adder/subtracter circuit is exactly the
same for both signed and unsigned numbers. The only difference is that
carry is not an indication of the error in the result for signed
numbers, but you need overflow.

And going back to table 2, what are the 2 extra bits in the result
(P=Q+2) in rows 2 and 3? Carry and ....? Could it be overflow? But then
why isn't P=Q+2 an option when both inputs are signed?
Xilinx, thanks for incomplete and confusing documentation!

In contrast, Altera's lpm_add_sub readily provides both carry and
overflow outputs. It also provides a parameter to specify whether the
numbers are signed or unsigned, and explains what effect that paramter
has on the operation of the circuit (it only affects the behavior of
the overflow output, nothing else).

 

[David Tweed]

dp wrote:

If the purpose is to have the FIFO (and not to build it, say,
for learning or economic purposes), you can use one of
the 72XX (IDT used to make them) FIFO chips. They have
the R/W pointer circuitry inside etc., really convenient
to use - and you will need no memory address lines out
of the FPGA, nor will the data necessarily go through it
(that is, you can just handle the full/empty flags and
the R/W strobes - and there also is a half full flag).

Yes, but they are of limited size and rather expensive.

I once needed to delay a T1/E1 signal (all three states,
so 1.544 or 2.048 million bit-pairs per second) by up to
tens of milliseconds, continuously adjustable. I ended up
with an external cheap generic CMOS SRAM (128K x 8) and
an Actel ACT2 FPGA to control it. Most of the FPGA runs
synchronously with the output clock at 4x the data rate
(6.176 or 8.192 MHz). For the input data, there's a 4 x 2
shift register that runs at the input clock rate and a
block of logic that passes memory write requests to the
output clock domain.

With 16 clocks per read/write pair, there was plenty of
time to work with and resolve conflicts between reads and
writes. I even did all of the address arithmetic using a
2-bit wide serial data path to save logic.

-- Dave Tweed

 

[Raymund Hofmann]

I guess it's because of their Problems with the DCM / DFS in stepping 0

Raymund Hofmann

"Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag
news:dmpfou$5am$03$1@news.t-online.com...

Hiho

Spartan3E status:

1) Avnet has sold 400 (maybe a few hundred more) of their 69USD
XC3S100E based starterkit, now they have 18 in stock if that is sold
out then leadtime for next order is: 26 weeks !

2) All Spartan3e devices have been removed from Avnet online inventory
search ?

3) Cesys GmbH can ship from stock 500E based boards
http://www.cesys.com/index.php?language=en&doc=advanced&docparams=USB3FPGA&menuparams=53

4) Xilinx Spartan3e kits are coming... at Christmas?

5) Spartan3 100e 'sample' pack pictures are online at nuhorizon!
I assumed that this product/info remains confidential until officially
launched by Xilinx, well here is at least the pictures

http://www.nuhorizons.com/products/xilinx/spartan3e/samplepack.html

6) nuhorizon part search on XC3s return page unavailable

Antti