EDK : FSL macros defined by Xilinx are wrong

[Brendan Cullen]

The first training I got in PM was ETP's 10-step approach :
http://www.etpint.com/tensteps.htm. For software-specific projects I've
found Steve McConnell's ideas helpful : http://www.construx.com/. Another
consideration is PMP certification wiht PMI : www.pmi.org. Overall I'd
agree with other posters that tools are far less important than process and
attitude. PM has many angles, cost, scheduling, quality, etc... Don't
neglect any of them. One apprach is to consider you (the PM) being pulled
in 4 different directions - scope, quality, time & cost. You (and your
stakeholders and team members) need to appreciate that those 4 all are
factors. E.g., if you increase the scope and the other three constraints
remain the same your project will fail.

Brendan


<gretzteam@hotmail.com> wrote in message
news:1133279619.861418.105430@o13g2000cwo.googlegroups.com...

Hi,
I just got chosen as 'project manager' for our next project. It seems
like most people feel 'sorry' for me around here... We are designing a
moderately large mostly digital asic and the team consists of about 6
people. I've never managed anything before and most of the people in
the team are more senior designer than me. Right now, things are
decided from hallway conversations, and nothing is really written down
in terms of schedule and who-does-what...

I wonder what tools if any that people use to manage a project. Is
something like MS-Project any good? I understand that the schedule we
would put in place will never hold, but I figure it's better to have
something than nothing. Also, what do people use to track down bugs and
issues. The chip is divided in 6-7 blocks, each will be assigned to
one-two person. Where should I gather the information coming out of the
weekly meeting - schedule slip, bugs to be fixed etc...email?
ms-project? hallway?

Thanks a lot,

Dave

 

Absolutely, Fergus O'Connell / ETP teach a huge amount of common sense.

Alan

 

[Austin Lesea]

Eric,

Yes, he will have problems.

Glitches on LUTs will be the least of his problems.

Austin

Eric Smith wrote:

I asked about the possibility of glitches on LUT outputs. Peter gave
a definitive response, and Symon wrote:

You got a good answer from Peter. However, my smarty pants response is to
never put yourself in a position where you care what the answer is! You'd
never clock a FF from the output of a LUT. Would you? ;-)


I fully agree; my designs are fully synchronous.

The reason the whole question came up is that a friend is trying to
cram old TTL logic designs into an FPGA without redesigning them to
be synchronous, so he has latches, S-R flops, and other horrible stuff.
I was wondering whether an S-R flop implemented as two cross-coupled
gates using a LUT for each gate could even be guaranteed to function
correctly; if LUTs can have output glitches they would not.

I'm still trying to convince my friend that his approach is likely to
cause him much grief.

Eric

 

[John Adair]

For most Xilinx families datasheets there is a page near the end of section
that has an I/O count versus package table.

There is also information in Xcell which you can download here
http://www.xilinx.com/publications/xcellonline/index.htm . Look at the last
few pages for shortform part data.

John Adair
Enterpoint Ltd. - Home of Raggedstone1. The Low Cost Spartan3 Development
Board.
http://www.enterpoint.co.uk

"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message
news:11ov5j451ce316f@corp.supernews.com...

Hi Okashi,

I found the tutorial at XESS.COM very useful when I was just starting out.
That was a year or so ago and things change. Seems like you are having
trouble
with pin IO counts, however, so you should go to the Xilinx site and look
for there
comparative data. Or just ask the group, we'll size it.

Brad Smallridge
aivision.com

"Okashii" <nordicelf@msn.com> wrote in message
news:438e3387$1@news.starhub.net.sg...
Hi there, pardon me but I'm a newbie at fpga and stuff. I was using
Xilinx ISE and vhdl to build some components and no matter what the size
of component I keep getting "number of bonded iob" exceeded. Then after
some observation I finally realized that its the size of bits of the
ports of the top level component . May I know where I can find layman
information on fpga online that explains what are "slices, slice
flip-flops, LUT, IOB" and all these?
Thanks in advance!

 

[Dave Roberts]

Yes - FROM, TO is correct. The constraints are still being applied
incorrectly FROM my specified TO group, going to some arbitrary destination.
Not sure what's up.

Thanks,

Dave.

"Russ Panneton" <pannetron@hotmail.com> wrote in message
news:dmnusn$2ck1@xco-news.xilinx.com...

Dave Roberts wrote:
Dear all,

I place a timing constraint on a pair of registers (from, to) either side
of some logic. After I run the ISE 6.3 toolchain, I look at the actual
delays for the constraint in Timing Analyzer.

The constraint seems to have been applied from the source register which
I specified as my destination, to a register or pad elsewhere in the
design. The constraint is applied to logic other than specified.

Any suggestions?

Cheers,

Dave.

Can you check the PCF to see if the FROM TO still references the correct
register pair?

Russ

 

[aptecelectronics]

I have a 16V (PALCE16V8H-15PC/4) that has lost it's program, and need
a new copy made. Can you do it for me? Cost? The part is an HP
08751-80130, and I have a good one that could be copied from, and I
have a new blank to be copied to. Stu Aplin 310-640-7262

Oil4warwrote:
16V* is most pupular low cost chip. from 1984, Abel 1.1 and

many DOS

stuff. If you want, I can burn a CD for you. I block
E-mail in
this AOL.

hope your E-mail addr. is real one.

 

[Antti Lukats]

"Pankaj" <pankajgode@gmail.com> schrieb im Newsbeitrag
news:1133609780.108306.290080@z14g2000cwz.googlegroups.com...

Using RiscWatch with Xilinx FPGA's for powerpc.
I have Xilinx 7.1 package with xilinx fpga boards , as well ML310
with virtex 2p devices ,on which powerpc and microblaze architectures
are supported.
I wanted to run an application on this powerpc architecutre and debug
it.

As i am using powerpc so i think risc watch debugger would be better.
But my question is does xilinx provide support for riscwatch.
I mean, i have a base system created using EDK 7.1. And thus i have a
bitstream corresponding to this base system with powerpc as processor.
Now i want to run application and collect some statistics. For this i
want to use risc watch debugger.
I don't know whether gdb available with EDK is of use for powerpc
platform, because i want register level information.

reg level access is avilable from edk supplied debugger
no need to use riscwatch

antti

 

[Symon]

"Antti Lukats" <antti@openchip.org> wrote in message
news:dmsdq1$lcp$1@online.de...

Hi Symon,

yes it works in V4 too, but the correct LOC syntax is

NET iopad LOC="UNB_X2Y53";

and with 7.1 tools for V2/P the UCF should be

NET iopad LOC="NOPAD45";

not UNBxxx

Hi Antti,

It seems there are two types of unbonded IOBs. One set called NOPADxx,
another set called UNBxxx. Both seem to work in this type of application. My
guess is that the UNBxxx type have a pad on the silicon for a bond wire
which can be used in a package with a lot of balls (if you see what I
mean!), whereas the NOPADxx ones are not used in any package so don't have
this pad.
Guesswork though!
Cheers, Syms.

 

[joseph]

one possible problem is that if the interface type is "memory", oclk need be connected.

 

[David Brown]

Antti Lukats wrote:

juendme@yahoo.com> schrieb im Newsbeitrag
news:1133767201.391460.43970@f14g2000cwb.googlegroups.com...
OK. Can someone quote the sentence where I was wrong? I would like to
learn.


I DID READ all your posting. And replayed based on that.

if you want to learn, then what I suggested is what you should do, this way
I hoped you would learn and understand.

ok, if you dont wanna learn yourself then you well this was already given in
an another post to you, the addsub uses carry chain and there just is not
'other' pin available. So you get the result and one additional signal -
thats it. If anything else is required it can not be implemented by the
addsub carry-chain built macro.

and as of efficiency of the coregen - it is defenetly possible to make as
efficient or better (hard)macros by hand, so if you know what you want just
implemenet it in efficient way and forget the coregen.


Antti

The Quartus tools spot many common hand-coded constructs, and implement
them with cores automatically, so that writing your addsub by hand or
using the ready-made cores will give the same implementation. Won't
Xilinx tools do that too?

 

[Antti Lukats]

"David Brown" <david@westcontrol.removethisbit.com> schrieb im Newsbeitrag
news:43942668$1@news.wineasy.se...

Antti Lukats wrote:
juendme@yahoo.com> schrieb im Newsbeitrag
news:1133767201.391460.43970@f14g2000cwb.googlegroups.com...
OK. Can someone quote the sentence where I was wrong? I would like to
learn.


I DID READ all your posting. And replayed based on that.

if you want to learn, then what I suggested is what you should do, this
way I hoped you would learn and understand.

ok, if you dont wanna learn yourself then you well this was already given
in an another post to you, the addsub uses carry chain and there just is
not 'other' pin available. So you get the result and one additional
signal - thats it. If anything else is required it can not be implemented
by the addsub carry-chain built macro.

and as of efficiency of the coregen - it is defenetly possible to make as
efficient or better (hard)macros by hand, so if you know what you want
just implemenet it in efficient way and forget the coregen.


Antti


The Quartus tools spot many common hand-coded constructs, and implement
them with cores automatically, so that writing your addsub by hand or
using the ready-made cores will give the same implementation. Won't
Xilinx tools do that too?

Sure the Xilinx flow does the same, but...

if you write some construct that does add and sub and provides __separate__
outputs for carry and borrow, then how should that be written in order to be
recognized for core extraction and what should the coregen actually
implement?

For 'normal' addsub there are no problems. The OP wants carry and borrow at
the same time from the same core primitive !

Antti

 

[Antti Lukats]

"Lina" <lnzhao@emails.bjut.edu.cn> schrieb im Newsbeitrag
news:ee92962.-1@webx.sUN8CHnE...

Hi all,

Who has ever used the tool of EDK 7.1 "tools->programme flash memory" to
fulfill the aim: put my file into the flash and then when the power of the
fpga board is on, the file on the flash begin to run.

Who has some documents expecially some examples, please help me!

Thank you very much. Lina

Hi Lina,

first of all Flash has no legs and can not run. The Flash is a non volatile
memory that has normally no files on it. It is possible to use Flash as
file-system, in that case some areas of the flash may be considered as
'files', in most cased Flash is used simpley as nonvolatile memory (no
files, just some binary contents).

the EDK ->program flash memory function can copy some prepared image (with
any contents) to the flash memory - that is only possible if your hardware
is built in proper recognized way.

after you program the flash with EDK your SoC system can access the flash as
some area in the memory map.

if you have properly modified the linker scripts and made your software
application capable to start from flash then your program would then start
from the flash memory.

so download the GNU linker manual and start reading

Antti
PS first time I had to get microblaze to boot from flash it took me 2 weeks.
this included custom flash programmer software and time to fix the bug in
the EMC IP core that preveneted CFI commands to be executed on byte wide
flash memories.

 

[David Brown]

Antti Lukats wrote:

"David Brown" <david@westcontrol.removethisbit.com> schrieb im Newsbeitrag
news:43942668$1@news.wineasy.se...
Antti Lukats wrote:
juendme@yahoo.com> schrieb im Newsbeitrag
news:1133767201.391460.43970@f14g2000cwb.googlegroups.com...
OK. Can someone quote the sentence where I was wrong? I would like to
learn.

I DID READ all your posting. And replayed based on that.

if you want to learn, then what I suggested is what you should do, this
way I hoped you would learn and understand.

ok, if you dont wanna learn yourself then you well this was already given
in an another post to you, the addsub uses carry chain and there just is
not 'other' pin available. So you get the result and one additional
signal - thats it. If anything else is required it can not be implemented
by the addsub carry-chain built macro.

and as of efficiency of the coregen - it is defenetly possible to make as
efficient or better (hard)macros by hand, so if you know what you want
just implemenet it in efficient way and forget the coregen.


Antti

The Quartus tools spot many common hand-coded constructs, and implement
them with cores automatically, so that writing your addsub by hand or
using the ready-made cores will give the same implementation. Won't
Xilinx tools do that too?


Sure the Xilinx flow does the same, but...

if you write some construct that does add and sub and provides __separate__
outputs for carry and borrow, then how should that be written in order to be
recognized for core extraction and what should the coregen actually
implement?

For 'normal' addsub there are no problems. The OP wants carry and borrow at
the same time from the same core primitive !

Antti

My point is that the OP should write the code the way he wants it to
run. If the Xilinx tools can implement it using some faster or smaller
mechanism than an obvious LUT implementation, then great. If not, then
it's likely to be because there is no such better implementation on the
particular architecture. But you let the tool do the work, rather than
trying to figure out how to force the coregen into making the right
construction. That's why we use these tools, rather than drawing out
Karnough maps and hand-optimising everything.

 

[Lina]

Hi Antti,

thank you for you answer.

Since you have successfully fulfilled the function and have the experience to do the experiment, you surely know the detail about how to programme flash memory. Would you please kindly provide me some materials and explain it in detail to me. Would you please give me some general example projects to me?

I met some problems when using tools->program flash memory. My flash are two chips of "AT49BV162A" which are controlled by emc and there are two sram(each of them is 512K bytes) together with them. During my experiment there is always an infromation

"DeviceIoControl LPT_WRITE_CMD_BUFFER Failed", then the project is always running without stop.

I also want you to explain to me the different meanings of "flash memory properties" and Scratch Pad Memory Properties". what are they two repectively used for?

Thank you very much.

Best regards.

Lina

 

[Peter Alfke]

Fred, this is a public newsgroup. Answers are posted voluntarily and
for free. Only a few of us are employed by companies that have a stake
in this, and benefit more or less directly from the timely resolution
of apparent problems (I fall into this latter category).
That's why it is so important to maintain a friendly and cooperative
spirit, and avoid insults and slamming.
If you feel that Xilinx documentation is not perfect, I would be the
first to agree. But similar critique can also be voiced about lots of
other documentation. FPGAs are being used by a wide variety of
designers with widely varying background and expertise. It is tough
enough to avoid mistakes, even tougher to be complete, and hopeless to
please everybody.
Let's be friendly and cooperative, and avoid insults...
Peter

 

Hello Tomoya-san,
We have an errata sheet published on
www.altera.com/literature/lit-stx2.jsp which shows the differences
between the ES and production devices. There's nothing there that is
directly connected to DDR memory interfaces, but I suggest that you
take a look and see if anything in your design is related to these
errata.

Of course your bigger question is "How can I make a DDR interface
work?" We have various literature, IP, and development kits on DDR
memory (also DDR2), so there's some resources there to help you in the
debug process. We have many customers using these memories so in
general the Altera device can implement the interface.
http://www.altera.com/technology/memory/sdram/mem-ddr_sdram.html
http://www.altera.com/technology/memory/dram/ddr2/mem-ddr2.html

Often when two seemingly similar parts behave differently, there may be
a subtle timing problem, and a part being a little faster or slower
than the other can cause a problem. Particularly with DDR, where
there's the added complication of the round trip where the FPGA drives
the clock of the DDR memory, so the data coming back to the FPGA must
be resynchronized. The literature I cited above has some information on
how to implement this.

Another source of timing problems is board power supply - we've seen
some cases where the IR drop of a connector sourcing power to the board
causes the FPGA's VCC to be below spec, which slows it down. Another
good thing to check.

If you think the PLL is a cause here, you could check the jitter on the
output of the ES part and the production device. But that's usually
pretty robust.

Another good tool (in case you don't know about it) is SignalTap, which
lets you probe the interior design of the FPGA and view the results on
your PC.

I hope that these suggestions help. They are pretty general but will
give you a good starting point.

Sincerely,
Greg Steinke
Altera Corporation

 

[John Williams]

Hi Philip,

Philip Freidin wrote:

and they all have better hair than me, so I know this is not a

What does a good haircut cost in Sunnyvale?

Xilinx files patents because they don't want someone else to make
FPGAs that use the technology that they have invented. This is
independent of the LUT contents, which is why you don't see
patents from Xilinx that refer to specific contents.

They also seem to file patents on novel applications of their FPGAs. My
guess is this is to prevent anyone limiting what Xilinx customers can do
with Xilinx FPGAs - a kind of defensive patenting on behalf of their
customers.

John

 

[Tomoya]

Greg-san, thak you for good comment.

From the interface point of view, DDR interfaces (there are two
DDR-200/400 interfaces on the evaluation board) are worked well

(DDR-200/400 runs on the both board, old and new). The DDR module and
its interface runs under DCM. Then, such clock jittar (that Greg-san
suggested) will be cancelled (is not seen), I guess (maybe). The
only difference behavior that we had faced is, data communication.
Our board has total 750 general purpose IOs (these are 2.5 Volt
single-ended interface). These interface does not run under DCM.
These are driven by the system clock (is generated by the FPGA internal
PLL). The old one runs at 250 MHz (or more) speed. But, the new one
runs at 150 MHz. So, 40% down. Therefore, I have such question (the
original question).

Anyway, we'll check the clock characteristics. Especially, clock
jittar.

Thank you for good advice. And I'm waiting for any other comments
about this issue.
Best regards,
---
Tomoya Kaku <URL: http://www.accverinos.jp>
Yokohma R&D Center, Verification System Development Division,
SK-Electronics CO., LTD

 

[Simon Peacock]

You may want to check the stockings by the fireplace.

Simon

"Antti Lukats" <antti@openchip.org> wrote in message
news:dn20o1$t57$1@online.de...

ISE 8.1 release was planned for mid nov, now its mid december soon, I
wonder
if it is known how much more the ISE 8.1 release is delaying? Xilinx is
advertising ISE webcast on Dec 14, I wonder if that will only cover soon
to
be obsoleted 7.1 or be focused on 8.1?

Actually I am more waiting for the EDK 8.1 in the hope DDR2 support is
added, but as EDK 8.1 release was projected 4 weeks after ISE 8.1 release
I
guess the EDK 8.1 actuall release date is slipping also most likely
into
2006?

Antti

 

[Aurelian Lazarut]

you need to compile the simmprim vhdl library first.
in your $XILINX directory under /vhdl/src/simprims
(replace $XILINX with your actual xilinx installation dir)

Aurash

bachimanchi@gmail.com wrote:

Hi all,
to be more clear about my problem with timing simulation
after i implement it using xilinx it is creating one TIME_SIM.VHD and
TIME_SIM.SDF file under the folder "timing"
it has an identifier "X_INV_PP" in both files when i compile
TIME_SIM.VHD it is giving an error
"Unknown identifier "X_INV_PP""
Cannot find component declaration
did anyone come across similar kind of problem.please help me out

thanks,


Regards
Ramakrishna