EDK : FSL macros defined by Xilinx are wrong

jamesp wrote:
Hi,

I am a mature student will be doing some complex VHDL and Verilog design
work for my course. As well as having to create and test the
functionality of the design (in both languages) I want to document how
the design is put together and it's complex hierarchy.

Is there anything out there that will allow me to represent my design in
some sort of hierarchical functional blocks to use as a documentation
tool? As I want to use both languages for the design something that
ideally can accommodate VHDL and Verilog.

I am happy using my normal editing system for the code design so I don't
want a 'block-to-code' type of system.

Thanks for your help.

James.
Hi James,
Click to expand...

We have a tool which we believe will address your questions. There is a
15 day fully functional evaluation download available on the web site so
please feel free to try it out.

www.expressivesystems.com


--

Cheers
Brian
___________________________________
Expressive Systems.
www.expressivesystems.com
 
Hi

I have read that, it says we should not use asynchronous reset

The program what i have written is also taken from there and they say it will be mapped to BRAMs

I am observing in my p&r report that it is getting mapped to BRAM but the slice count is not getting reduced.

regds bijoy
 
"Simon Peacock" <simon$actrix.co.nz> schrieb im Newsbeitrag
news:4393e2d9$1@news2.actrix.gen.nz...
I am still waiting for the Xilinx Spartan 3E demo board.. price is right
and
it has Ethernet

Simon
Click to expand...
good luck with your waiting!

I have the cesys board with 500E chip so my wait is now over :)
Antti
 
It is normal, DONE pin is not modified during the partial
reconfiguration.

In ISE 7.1 partial reconfiguration on Virtex4 is not well supported.
It works only with very small designs making some manual work on the
FPGA Editor.

Regards

Javier Castillo

On 8 Dec 2005 07:19:46 -0800, "Denaice" <dgalerin@gmail.com> wrote:

Hi,

I'm trying to dynamically reconfigure a Virtex-4 FPGA, by following the
example of XAPP 290. I'm following the module-based partial reconfig
flow, but since the tools don't support generation of partial
bitstreams, I use difference-based bitstreams to reconfigure the FPGA.
The generation of full and partial bitstreams works perfectly, and I
have no problem when downloading the initial bitstream to the chip.
However, when I try to download a partial bitstream, I have the
following warning message :

Warning:iMPACT:2218 - Error shows in the status register, release_done
bit is NOT 1.

The FPGA pauses (it seems that the outputs are 3-stated) until I click
ok "ok". When I read the status register after that, the done pin has
the correct value.

Does anyone have an idea about the cause of this warning ?

Thanks,

Denis

PS : I'm using a VIRTEX-4 LX25 on an Avnet board, and I'm using a
parallel cable IV in Boundary scan mode. I'm working with ISE 7.1 SP3.
Here are my bitgen -g options :

-g ActivateGCLK:Yes
-g ReadBack
-g DebugBitstream:No
-g CRC:Enable
-g ConfigRate:4
-g M0Pin:pullUp
-g M1Pin:pullUp
-g M2Pin:pullUp
-g ProgPin:pullUp
-g DonePin:pullUp
-g DriveDone:No
-g PowerdownPin:pullUp
-g TckPin:pullUp
-g TdiPin:pullUp
-g TdoPin:pullNone
-g TmsPin:pullUp
-g UnusedPin:pullUp
-g UserID:0xFFFFFFFF
-g DCMShutDown:Disable
-g DisableBandgap:No
-g StartUpClk:JtagClk
-g DONE_cycle:4
-g GTS_cycle:Keep
-g GWE_cycle:Keep
-g LCK_cycle:NoWait
-g Match_cycle:NoWait
-g Security:None
-g Persist:No
-g ActiveReconfig:Yes
-g DonePipe:No
-g Encrypt:No
Click to expand...
 
"Ray Andraka" <ray@andraka.com> schrieb im Newsbeitrag
news:wmklf.16519$Mi5.14447@dukeread07...
Simon Peacock wrote:
You may want to check the stockings by the fireplace.

Simon

"Antti Lukats" <antti@openchip.org> wrote in message
news:dn20o1$t57$1@online.de...

ISE 8.1 release was planned for mid nov, now its mid december soon, I

wonder...


I got 8.1 this morning by electronic delivery. I haven't tried installing
it yet. I'll wait till I have the current projects out of the way before
subjecting myself to being a guinea pig again.
Click to expand...
I am not asking you to be a guinea pig but could you checkout (in the 8.1
manual?)
if jtag indirect programming of serial flash devices for Spartan 3e is
supported?

Altera and Lattice both support this kind of programming I wonder if Xilinx
is
getting up to the competitors or not.

Or maybe some one from Xilinx could answer my question? please?

Antti
 
Thanks for your help.

I have one more question : Is there a mean to reconfigure the virtex-4
(with partial bitstreams) without pausing it, or do we have to use full
bitstreams ?

Thanks in advance,

Denis
 
"Denaice" <dgalerin@gmail.com> schrieb im Newsbeitrag
news:1134138476.071974.187070@g49g2000cwa.googlegroups.com...
Thanks for your help.

I have one more question : Is there a mean to reconfigure the virtex-4
(with partial bitstreams) without pausing it, or do we have to use full
bitstreams ?

Thanks in advance,

Denis
Click to expand...
it should be possible, but may be very tricky
antti
 
You can use Metor Graphics's FPGA Advantage. When I was a student I
used it to design complex VHDL designs.
You have graphical entry of HDL code. The HDL code can also be
converted to a graphical representation. See www.mentor.com for more
infos on theyr products.

A+
Mehdi
 
The local FAE dropped off a copy of 8.1 yesterday.

It exists.

Tried it out for a while. No major issues noted. Some issues I was
having with Spartan3e are fixed.


--
Phil Hays to reply solve: phil.hays at not(coldmail) dot com
If not cold then hot
 
I'm not sure what you are asking. When you reconfigure the FPGA with
a partial bitstream the FPGA is not paused, the not reconfigured part
is working during the partial reconfiguration. That is the reason
because you can reconfigure one part of the FPGA using the ICAP port.
For this type of questions I recommend you to use the partial
reconfiguration mailing list.

Regards

Javier

On 9 Dec 2005 06:27:56 -0800, "Denaice" <dgalerin@gmail.com> wrote:

Thanks for your help.

I have one more question : Is there a mean to reconfigure the virtex-4
(with partial bitstreams) without pausing it, or do we have to use full
bitstreams ?

Thanks in advance,

Denis
Click to expand...
 
Well, for the moment, I'm not reconfiguring through ICAP with a PPC or
Microblaze. I'm only trying to reconfigure in JTAG by the remote PC,
but it seems - obviously - that the FPGA pauses when reconfiguring
(because in my design, the leds which, should continue to blink, are
shut down).

I don't know....
 
I must develop a system with lots of I/O, about 180-190. My chief don't
want use BGA (fg320), but pq208...
so I thought to connect 2 fpga pq208.

I think it'is bad... but there are other chances?

Otherwise does exist a BGA adapter for fg320 package to change it into a
pq320?

Why not use a FPGA module like the Zefant Modules? (www.zefant.de)?
Click to expand...
I have one of those Zefant S3-1000 boards + Baseboard , it's an
excellent combination.

There is even 47 pcs. 5v tolerant CPLD pins in addition to the FPGA
pins.



Carsten
 
Yes, impact send a command to stop the FPGA. One thing you can do it
to use the SelectMap interface or send the bitstream to the jtag
without using Impact. It is not very difficult to make a program in C
to program the FPGA using the JTAG.

Javier

On 9 Dec 2005 08:28:47 -0800, "Denaice" <dgalerin@gmail.com> wrote:

Well, for the moment, I'm not reconfiguring through ICAP with a PPC or
Microblaze. I'm only trying to reconfigure in JTAG by the remote PC,
but it seems - obviously - that the FPGA pauses when reconfiguring
(because in my design, the leds which, should continue to blink, are
shut down).

I don't know....
Click to expand...
 
"Carsten" <xnews1@luna.kyed.com> wrote in message
news:lehjp19rgq012omivffaerbdr58ofjfblp@4ax.com...
I must develop a system with lots of I/O, about 180-190. My chief don't
want use BGA (fg320), but pq208...
so I thought to connect 2 fpga pq208.

I think it'is bad... but there are other chances?

Otherwise does exist a BGA adapter for fg320 package to change it into a
pq320?

Why not use a FPGA module like the Zefant Modules? (www.zefant.de)?

I have one of those Zefant S3-1000 boards + Baseboard , it's an
excellent combination.

There is even 47 pcs. 5v tolerant CPLD pins in addition to the FPGA
pins.



Carsten
Click to expand...
It seems good. I'll look for it.

Many Thanks
Marco
 
Marco wrote:
"Antti Lukats" <antti@openchip.org> wrote in message
news:dn6b3a$h6c$01$1@news.t-online.com...
"Marco" <marcotoschi@nospam.it> schrieb im Newsbeitrag
news:dn643r$hbo$1@nnrp.ngi.it...
Hallo,
does anyone has connected 2 FPGA?
Which kind of connection have used?

Many Thanks
Marco

FPGAs are often connected to each other by different means.

your question can have no reasonable answers as you are the only person
who know WHY you want to connect the FPGA, and the answer to that question
is needed in order to decide HOW. It all depends why and what you are
going to achive.

Antti


I must develop a system with lots of I/O, about 180-190. My chief don't want
use BGA (fg320), but pq208...
so I thought to connect 2 fpga pq208.

I think it'is bad... but there are other chances?

Otherwise does exist a BGA adapter for fg320 package to change it into a
pq320?

Many Thanks
Marco
Click to expand...
What reasons do you have for not using BGAs? Any contract manufacturer
(who will do the reflow soldering) will quote you **cheaper** on BGAs
than quad packs, because they are easier to place. If you intend to
sell a lot of them, the manufacturing price becomes important.

As noted, if you need debug access to the pins, bring them out to a
header that simply would not be fitted in production.

As to prototyping with BGAs, there are people around who successfully
put down BGAs with heat guns.

Of course, you could use a plugin module, but then you expose yourself
to the single greatest failure mechanism in all electronic equipment;
mechanical connections.

Cheers

PeteS
 
First off, I think it's better to instantiate BRAM than inferring it.
When you go to the restaurant
and you want veal, you should say it, don't describe the veal to the
waiter :)
The other issue is that your FFs are read from and written to in the
same clock. I vaguely
remember reading and writing to the same BRAM address is a bad idea.

bijoy wrote:
Hi

I have read that, it says we should not use asynchronous reset

The program what i have written is also taken from there and they say it will be mapped to BRAMs

I am observing in my p&r report that it is getting mapped to BRAM but the slice count is not getting reduced.

regds bijoy
Click to expand...
 
"fahadislam2002" <fahadislam2002@hotmail-dot-com.no-spam.invalid> schrieb im
Newsbeitrag news:kdqdnV-4CqYi4AbeRVn_vA@giganews.com...
Hi
We are trying to interface a 16MB MMC(of Infineon) to Spartan-2
FPGA ...
We have designed reader for card(in VHDL) abopting MMC protocol(not
SPI) and this card is supports 2.7 to 3.0 standard ...
Before designing its writer i want to test reader ...
and before that i want your suggestions ... :)

So please share your experience and guide me ...

Thanks
Click to expand...
so whats your problem ??
why are "trying" and not "DOING" ??

I have published an project at opencores that can configure an FPGA from MMC
in MMC mode this IPcore is hardware tested (uses 21 PLD macrocells!)

at
http://gforge.openchip.org

there is snapshot from mmc host controller ip core from LARK project -
notice that ipcore is 100% non-tested

and www.xilant.com
has MMC/SD cardside ipcore that could be used for testing (not announced
yet)

for initial testing you can just make an Microblaze SoC in the S-2 and use
bitbang to read the MMC so it would be easy to debug and see the response, I
think I published once that software but dont recall where and if it is
still on the web, in any case it isnt complex

so go ahead and test you mmc interface, until you do that, you would not
know if it works or not

Antti
 
Hi I don't know how to implement a shift register using BRAMs. That is why i tried to use the map property to enable the mapping option.

If any one has an idea, could you please share it with me.

regards bijoy
 
A single line with the default, right before the case statement
in DCM_comb, should do it:

DCM_NextState <= DCM_CurrentState;

Jan

Hi Jan,
Click to expand...
You are right. I also thought about that, but somehow I expected it to
create latches as well. Strange, since I'm using the
defaults-before-case style a lot. Fooled by too much routine possibly :)

But still, ISE created a latch free result before that change.
Maybe one could complain about a missing warning.
And even after the proposed correction ISE created a smaller and faster
result than Precision RTL. (Synopsys dc also created something latchfree
but again the FSM extraction failed, so further optimisation wasn't
possible)

How comes that the simpler(?) tool does the better job?

Enlightened, but still wondering :)

Eilert
 
Any recommendations for documentation describing MMC, SD, and their differences. I have Googled, and got swamped with loads of
links to places selling such cards. The few techy links were fairly useless, along the lines of "you can buy the full spec
from...."

http://www.sdcard.org/sd_memorycard/index.html
Click to expand...
http://www.sandisk.com/pdf/oem/AppNoteMMC_SDv1.0.pdf

BTW: will your MMC or SD card interface be open-source?
I am interested in the SD card interface, ?but don't find
the time to implement it.

Martin
 
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