EDK : FSL macros defined by Xilinx are wrong

[Petter Gustad]

svasus@gmail.com writes:

So I was hoping to find a chip which would sandwich between the FPGA
and I2C interface.

A second microcontroller Connect the PIC 16FL87X to your FPGA and
program the PIC to send data received on the RB port out on the I2C
port or vice versa...

Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

 

[Hans]

Hi Antti,

I am happy to see you managed to get it up and running although using the
serial port might have been easier than using chipscope. I will add an 8254
and 8259 (required for a minimum system) as soon as my workload reduces a
bit (probably around Christmas) If only I had some more "spare" time......


Regards,
Hans.
www.ht-lab.com

"Antti Lukats" <antti@openchip.org> wrote in message
news:dn6tpb$7oh$02$1@news.t-online.com...

seeing is beliving

the modelsim precompiled version was offered by HT-LAB for free for some
time, but that did not trigger my curiosity level - but now as also EDIF
version are available its really simple and easy to test drive the CPU86
ipcore in FPGA! it took about 1 hour to get the core todo something in an
Virtex4, the utilization in FX12 was 51% of the slices.

http://xilant.com/content/view/19/2/

there is ChipScope Pro snapshot of the first succesfull test.

and the CPU86 is from HT-LAB
http://www.ht-lab.com/

Antti

Hans are you here?

 

[Antti Lukats]

"Hans" <hans64@ht-lab.com> schrieb im Newsbeitrag
newstSlf.6121$E14.3906@newsfe7-win.ntli.net...

Hi Antti,

I am happy to see you managed to get it up and running although using the
serial port might have been easier than using chipscope. I will add an
8254 and 8259 (required for a minimum system) as soon as my workload
reduces a bit (probably around Christmas) If only I had some more "spare"
time......

Regards,
Hans.
www.ht-lab.com

Hi Hans,

spare time for Christmas - thats I suppose the ultimate wish of all of us

using serial port would not have been easier as I should have added a DCM to
supply proper clock, and I did have any RAM in the system only the bootstrap
ROM. I just wanted to make a REALquick inFPGA test.

yes having a 8259+8254 would be cool or even better a minimal "PC" setup
when I wrote my 8086 ipcore I also started the 8254 etc ipcores but they are
not completed

another idea what I would really like to see is some sort of 'virtual' mode
where the cpu could fall back into shadow supervisor mode and emulate
unimplemented hardware or instruction, with an FPGA IP core it would be
really easy to implement (sure not by editing the EDIF..)

Antti
PS Hans I have some realworld customer queries about x86 ipcore as well so
please contact me in private as well

 

[damir]

Currently I'm looking only in 800x480 resolution with (if possible) 18-bit
color (16 bit is also ok) and flat-panel digital RGB interface.

Damir



"Don McKenzie" <look@mysig.com> wrote in message
news:43973685$0$17708$afc38c87@news.optusnet.com.au...

damir wrote:

I'm looking for simple VGA (XGA up to 800x600) controller for displaying
simple images on the LCD pannel - any suggestion for available ASIC (LCD
controller) or FPGA (VHDL core) design will do. Thanks,

Damir

http://www.dontronics.com/micro-vga.html
is one solution

Don...


--
Don McKenzie
E-Mail Contact Page: http://www.dontronics.com/e-mail.html

Micro,TTL,USB to 1.5" color LCD http://www.dontronics.com/micro-lcd.html
USB,RS232 or TTL to VGA Monitor http://www.dontronics.com/micro-vga.html
World's smallest USB 2 TTL Conv http://www.dontronics.com/micro-usb.html

 

[nospam.eric@gmail.com]

Hi

At a minimum we need to know how much bandwidth and latency you
accept/require for the communication between your FPGAs and how much of
your FPGAs you intend to dedicate to inter-FPGAs communication. The
caracteristics of the FPGA themselves are also welcome.

Waiting for your answer,

Eric DELAGE, Senior ASIC/FPGA Architect
EMail: nospam DOT eric AT gmail DOT com
Homepage: http://eric-delage.no-ip.info

 

[Michael]

Thank you so much! I think it is a very good board for me. But I am not sure
the following three things:
1. Will the image signal be got in the memory of the FPGA board? RGB or
other format?Need I design some FPGA module for them?
2. For this board, is the price including the daughter board?
3. For using this FPGA design, any extra software needed for downloading or
writing?
Thanks again

"Antti Lukats" <antti@openchip.org> wrote in message
news:dn6sth$uue$01$1@news.t-online.com...

"Gabor" <gabor@alacron.com> schrieb im Newsbeitrag
news:1133966508.937738.86720@g43g2000cwa.googlegroups.com...
hongying meng wrote:
Hi,

I will do some research on video/image processing on FPGA. I will design
VHDL codes for some video/image processing algorithms. I needs a FPGA
development board with a big FPGA chip on it. I also hope it can be
connected with a digital camera or image sensor with real-time image
access
into the board. It's better if the image in RGB format and input to the
board frame by frame.

Does any one know where there exist this kind of FPGA development board
or
not? If not, any suggestion should be really appreciated.

Thanks
Michael

Check out Xilinx:

Virtex-4 Video Starter Kit (HW-V4SX35-VIDEO-SK-US)

This seems to have an RGB image sensor built in.

http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-V4SX35-VIDEO-SK-US&sGlobalNavPick=&sSecondaryNavPick=


thats a nice bundle, yes.

the FPGA board is actually a ML402 what costs far less as standalone board

the micron camera that should be bundled is RGB camera, but its interface
does not deliver RGB as parallel, there is some multiplexing required
anyway.

funnily the camera chip is not on the video daughter board (or nor clearly
visible) also there seems to be no suitable connector for the camera and
there is no other info so I wonder where the image sensor is hidden?

Antti

 

[Marco]

<nospam.eric@gmail.com> wrote in message
news:1134033868.487979.128590@g49g2000cwa.googlegroups.com...

Hi

At a minimum we need to know how much bandwidth and latency you
accept/require for the communication between your FPGAs and how much of
your FPGAs you intend to dedicate to inter-FPGAs communication. The
caracteristics of the FPGA themselves are also welcome.

Waiting for your answer,

Eric DELAGE, Senior ASIC/FPGA Architect
EMail: nospam DOT eric AT gmail DOT com
Homepage: http://eric-delage.no-ip.info

Many Thanks in advance!

Fortunately I make sure my chief changes his mind toward the use of 2 FPGA.
Now we're searching for an adapter for BGA package.
I have found this from Interconnect Systems: HiLoTM BGA Socketing Supports
XilinxŽ Virtex 4 BGA Packages

Does anyone has already used it? Could proive feedback?

Many and many thanks
MArco

 

[Abbs]

Thomas Stanka wrote:

code in TESTBENCHES.
If there are many other ways of testing and validation which i'am
unaware of PLEASE let me know.

Code review, testbenches, static timing analyses and formal
verification are the major verification tasks. Don't know which of them
makes sense for your designs and team.

One last doubt, in verification, do we even work on STATIC TIME
ANALYSIS and SYNTHESIS. or this is done by the designer itself..

How could we know if you don't? STA is usually perfomed after layout,
has your designer feedback from layout? Do you have to verify after
layout or are you only responsible for functional verification until
synthesis?

bye Thomas

hi
i was told to study corner case testing, different testing scenarios
and BFM models. i have to test the design before the layout. before
after synthesis not to sure... i wana get good knowledge regarding
verification. can you help me with links that gives a brief idea
related to testing...
thanks
Bye

 

[Jan Panteltje]

On a sunny day (Wed, 7 Dec 2005 13:47:03 -0000) it happened "hongying meng"
<hm512@york.ac.uk> wrote in <dn6p4m$m8m$1@pump1.york.ac.uk>:

Hi,

I will do some research on video/image processing on FPGA. I will design
VHDL codes for some video/image processing algorithms. I needs a FPGA
development board with a big FPGA chip on it. I also hope it can be
connected with a digital camera or image sensor with real-time image access
into the board. It's better if the image in RGB format and input to the
board frame by frame.

Does any one know where there exist this kind of FPGA development board or
not? If not, any suggestion should be really appreciated.

Thanks
Michael
You could consider buying a webcam with ethernet rj45 interface.

These have a build in web server (I use D-Link DCS-900) (<150$).
Then find a FPGA board with ethernet interface.
This camera sends jpeg picture stream.
So.. then you have to process the jpeg (opencores?) and make TCP/IP HDL.
Or use a custom ASIC... mmm
Simpler is to use a RGB sensor on some IO pins....
Actually many of these sensors (CMOS) will sens some multiplexed form of YUV.

All depends on what your idea of 'image processing' is.
Anyways I think the ethernet cams are more fun then the USB (because of drivers).
I have this cam also working in Linux, seesm very popular for home security
(lot of downloads): http://panteltje.com/panteltje/mcamip/
No I am not associated with D-Link.

 

[Aurelian Lazarut]

See below
rybol wrote:

Hi,

in my design I would like to have the possibility to switch beetween
two
clock signals: 'clk' (this is my main clock) and 'ext_clk' (the second,

external clock) and the output clock is 'clk_out'. It all depends on
one
signal - let's call it 'temp'. 'Clk_out' is then used in the
sensitivity
list of some process ("process(clk_out) ..."). But when I code it in
VHDL
like this:

clk_out <= clk when temp = '0' else ext_clk;

in ISE I get the message that clk_out signal
"is generated by combinatorial logic and XST is not able to identify
which
are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify te clock signal(s)
generated by combinatorial logic.
Some clock signals were not autmatically buffered by XST with BUFG/BUFR

resources. Please use the buffer_type constraint in order to insert
these
buffers to the clock signals to help prevent skew problems."

So how should I solve this problem correctly?

Thanks in advance,
Tomek

intantiate a BUFGMUX (from ISE tepmlates)

Library UNISIM;
use UNISIM.vcomponents.all;

-- BUFGMUX_VIRTEX4: Global Clock Buffer 2-to-1 MUX
-- Virtex-4
-- Xilinx HDL Language Template version 8.1i

BUFGMUX_VIRTEX4_inst : BUFGMUX_VIRTEX4
generic map (
INIT_OUT => 0, -- Inital value of 0 or 1 after configuration
PRESELECT_I0 => FALSE, -- TRUE/FALSE set the I0 input after
configuration
PRESELECT_I1 => FALSE) -- TRUE/FALSE set the I1 input after
configuration
port map (
O => O, -- Clock MUX output
I0 => I0, -- Clock0 input
I1 => I1, -- Clock1 input
S => S -- Clock select input
);

-- End of BUFGMUX_VIRTEX4_inst instantiation

Regards,
Aurash

 

[Len]

http://www.xilinx.com/xcell/xl37/xcell37_54.pdf

 

[Len]

http://www.xilinx.com/xcell/xl37/xcell37_54.pdf

 

[Eric Smith]

"Antti Lukats" <antti@openchip.org> writes:

implementing i2c in fpga in hw or sw is simpler than interfacing PCFxxx pr
PCAxxx

It takes fewer pins to do I2C directly than to interface the Philips parts,
unless you already have a parallel bus you're using for other stuff.

But it's not particularly "simpler" to do I2C hardware yourself, at least
if you care about actually meeting the full I2C specifications. I've
seen a lot of bad I2C implementations that won't work under various
real-world conditions. For instance, I2C masters that don't handle
clock-stretching, or that don't handle arbitration. And I2C slaves that
don't meet the I2C timing specs.

The software bit-banging implementations are usually (but not always)
the worst as far as violating the specs.

I'm not saying that it's tremendously difficult to do it right, but it
is definitely more difficult than just bolting on a chip with an 8-bit
parallel interface that does all the "heavy lifting" for you. I've done
it both ways. I wouldn't design in the Philips chip is a cost-sensitive
high-volume product, but for a less cost-sensitive design, or if time-to-
market is a major concern, it's a reasonable approach.

Eric

 

[Dal]

fpgakid@gmail.com wrote:

Hi All,

I have a embedded desig where I communicate with two boards via Fast
ethernet. The design is very simple, the packets are generated from a
fpga and sent to the ethernet phy on MII. In the new design I'd like to
replace the ethernet phy with a VSDL2 chipset, so I need only one
twisted pair and for supporting more than 100 m.
Has anybody did something similar? IMO it should be very straight
forwarded to replace the phy with a VDSL2 chipset, but please let me
know if I'm wrong.

Regards,

Kim

It is not clear what you are really trying to achieve, and whether VDSL2
is the right solution. There may be better options for connecting two
boards in a more standard way, though I don't know what would meet your
needs best.

Do you need to maintain the high data rate over a much greater distance,
and is it really important to achieve the high rate over only one pair?
If you can live with the 100m restriction or less, and use standard
cabling, it sounds simpler to stick with what you have.

I have done something similar but it was before VDSL2, and I had access
to proprietary hardware.

You will probably be restricted by whatever interface the chipset
provides, even if you can get hold of the chipsets. And it is likely to
be a lot of effort to design something which will always be non-standard.

 

[Jim Granville]

Eric Smith wrote:

"Antti Lukats" <antti@openchip.org> writes:

implementing i2c in fpga in hw or sw is simpler than interfacing PCFxxx pr
PCAxxx


It takes fewer pins to do I2C directly than to interface the Philips parts,
unless you already have a parallel bus you're using for other stuff.

But it's not particularly "simpler" to do I2C hardware yourself, at least
if you care about actually meeting the full I2C specifications. I've
seen a lot of bad I2C implementations that won't work under various
real-world conditions. For instance, I2C masters that don't handle
clock-stretching, or that don't handle arbitration. And I2C slaves that
don't meet the I2C timing specs.

The software bit-banging implementations are usually (but not always)
the worst as far as violating the specs.

I'm not saying that it's tremendously difficult to do it right, but it
is definitely more difficult than just bolting on a chip with an 8-bit
parallel interface that does all the "heavy lifting" for you. I've done
it both ways. I wouldn't design in the Philips chip is a cost-sensitive
high-volume product, but for a less cost-sensitive design, or if time-to-
market is a major concern, it's a reasonable approach.

another alternative ( but perhaps a bit new...) is this family from
Philips :

http://www.standardics.philips.com/products/bridges/spi.slave.i2c.master.gpio/

This is TSSOP16, SPI-i2c master, 3Md on SPI and 400KHz on i2c.
[ It may even be a pgmd LPC916 ? ]

The overview does not say if the i2c side is 5V compliant.

-jg

 

[Uwe Bonnes]

Marco <marcotoschi@nospam.it> wrote:

"Antti Lukats" <antti@openchip.org> wrote in message
news:dn6b3a$h6c$01$1@news.t-online.com...
"Marco" <marcotoschi@nospam.it> schrieb im Newsbeitrag
news:dn643r$hbo$1@nnrp.ngi.it...
Hallo,
does anyone has connected 2 FPGA?
Which kind of connection have used?

Many Thanks
Marco

FPGAs are often connected to each other by different means.

your question can have no reasonable answers as you are the only
person
who know WHY you want to connect the FPGA, and the answer to that
question
is needed in order to decide HOW. It all depends why and what you are
going to achive.

Antti


I must develop a system with lots of I/O, about 180-190. My chief don't
want use BGA (fg320), but pq208...
so I thought to connect 2 fpga pq208.

I think it'is bad... but there are other chances?

Otherwise does exist a BGA adapter for fg320 package to change it into a
pq320?

Why not use a FPGA module like the Zefant Modules? (www.zefant.de)?

--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

 

[Chloe]

Thanks for your reply.

I would actually like to simulate the verilog model AFTER synthesis but
BEFORE translate. Is there any way to do that?

Thanks in advance.

 

[Antti Lukats]

"bijoy" <pbijoy@rediffmail.com> schrieb im Newsbeitrag
news:ee92e82.-1@webx.sUN8CHnE...

Hi

FPGA : Spartan-3, Xilinx ISE :tools ------------------------------------
have wrote a VHDL code to implement shift registers

as shown below
type reg_array is array(7 downto 0) of std_logic_vector(7 downto 0);
signal reg : reg_array;
process(clk) begin if(clk'event and clk = '1')then if(en = '1')then reg <=
reg(14 dwonto 0) & din; end if; end if; end process
want to map this logic to BLOCK RAM instead of slices.
have done this by enablling the option in MAP properties of ISE.
But what i observed is it uses BLOCK RAM but occupies slices also.
Can anyone help me in this regard
whether i am doing anything wrong ?
regards bijoy

the logic is that ISE can auto map to BRAM is ver limited and specific, read
the datasheet and manuals it is explained there what type of logic can be
auto mapped to BRAM

antti

 

[Ben Twijnstra]

Hi Antti Lukats,

most PCIe PHY datasheets are still under NDA, but Marco Groeneveld has
already made freely available the schematic of the SENDERO board that
includes the PX1011A chip with its connection - downloadable from

http://www.fpga.nl/

Actually, I just got word that the Sendero board passed the PCI Plugfest in
the US with flying colours this week, with an 85% score, and that the
motherboards on which it didn't work well had problems with most other x1
cards too.

Ready-made Sendero boards can be ordered from Sascoholz and other Arrow
subsidiaries.

Best regards,


Ben

 

[Antti Lukats]

"Ben Twijnstra" <btwijnstra@gmail.com> schrieb im Newsbeitrag
news:cfaf2$43992f17$d52e23a9$6108@news.chello.nl...

Hi Antti Lukats,

most PCIe PHY datasheets are still under NDA, but Marco Groeneveld has
already made freely available the schematic of the SENDERO board that
includes the PX1011A chip with its connection - downloadable from

http://www.fpga.nl/


Actually, I just got word that the Sendero board passed the PCI Plugfest
in
the US with flying colours this week, with an 85% score, and that the
motherboards on which it didn't work well had problems with most other x1
cards too.

Ready-made Sendero boards can be ordered from Sascoholz and other Arrow
subsidiaries.

Best regards,


Ben

Hi Ben,

thats another Altera FPGA Based PCIe board passing plugfest then!
I was reading the Sendero stuff and they only say "PCIe physical interface"
tested
so I assumed it was actually not tested in full. Real cool nice board !

it really seems that Xilinx is behind with PCIe, Stratix-GX passed plugfest
looong time ago.
And the promised Spartan3E+PhilipsPHY solution well havent seen much
pictures of
such boards yet. (except the northwest board that can use different phys).
There was some notice on Xilinx web that they have it working also (with
PX1011) but
where are the boards for Spartan3+PX1011 evaluation? I had the impression
Avnet
was targetting to have them ready by July (this YEAR!) - but nothing there.
Ah ok
it was possible delayed as the board was supposed to be S3e based. And I
guess
the Philips PHY delayed also it still says only samples available and DS
under NDA.

So for those who want lowcost PCIe today its Cyclone-II + PX1011A Go!
(or Lattice, they also just advertized low cost PCIe stuff)

Antti