EDK : FSL macros defined by Xilinx are wrong

[CMOS]

thank you. i noticed that. im wondering about the purpose of the JTSEL
( pin 6 you mentioned ) pin in USB2 module. No indication in the
documentation. there might be a way to make it float from the
microcontroller.
CMOS

 

[CMOS]

please let me know the maximum speed that can be acheived using the
supplied software dll and microcontroller firmware. I just need to
transfer the whole memory at once thru the USB port.

thank you.
CMOS

 

[hetfield]

It seems like you want to "count" the 1s in a 150-bit wide word, coming
in every 100 ns = 10 MHz.

Here is how I would do it:
Use 6 or 7 dual-ported BlockRAMs as LUTs.
Each BlockRAM is used as a ROM, organized 4k x 4,i.e. with 12 address
bits and 4 output bits.
The ROM stores the value of the number of ones on the address inputs.
One ROM takes care of 12 inputs, but since it is dual-ported, each
BlockRAM takes care of 24 inputs, generating two independent 4-bit
outputs.
Six BlockRAMs thus cover 144 inputs, and generate 12 independent 4-bit
binary numbers in less than 4 ns. The remaining 96 ns can be used in
simpler adder structures, or in a 12-step sequential accumulator
running at, say, 200 MHz.
Peter Alfke, Xilinx Applications

That's great guide for me.
Thanks a lot!

 

[sulimma]

acetylcholinerd@gmail.com schrieb:

Our application is we have one main board and 3 daughter boards, up to
1m away, and we are constrained to essentially using seven wires to
connect each daughter board to the main board. For this sort of
distance, we wanted to go LVDS in both directions, but to keep
everything synchronous, that would require that the B->D lvds pair also
contain the clock; clock recovery was going to let us still keep
everything synchronous. We knew we'd need a PLL

We've decided to go with a single-ended clock/data pair on one set of
wires and a (clock-multiplied) LVDS pair for the receiver (from
daughterboard -> mainboard),

Hmm. Seven wires. That is
- GND
- LVDS pair data D->M
- LVDS pair data M->D
- LVDS pair clk M->D

That's enough for a synchronous system. Somehow I do not see your
problem.
You can use one clock for data transfer in both directions.

Kolja Sulimma

 

[Vaughn Betz]

Hi Andre,

There are two separate attributes; one for input registers and one for
output registers.

Use "fast_input_register = on" to put a register that is capturing an input
to the FPGA from an I/O cell into the I/O cell.
Use "fast_output_register = on" to put a register that is storing a value
that drives an I/O cell (either the data port or the OE port) into the I/O
cell.

You can set these attributes either on registers or on I/O cells. So if you
have a bidirectional I/O, and want both the input path and output path
registers for the signals into and out of the I/O cell to be implemented in
the I/O cell, set the altera_attribute on the I/O to be:
"-name fast_input_register = on; -name fast_output_register = on"

Alternatively, you can just set timing constraints on your I/O paths in
Quartus, and it will move registers into the I/O cells if that will improve
your timing. In that case, you don't need to make any fast register
assignments. You should really make I/O timing assignments no matter what,
since (1) you want to know if you violate a constraint on your design, and
(2) there are other I/O timing optimization decisions Quartus makes besides
just where to put the registers connected to an I/O, and those optimizations
need timing constraints to guide them.

Regards,

Vaughn
Altera
[v b e t z (at) altera.com]

<ALuPin@web.de> wrote in message
news:1127388093.247646.196300@g14g2000cwa.googlegroups.com...
Hi Subroto,

I think the use of attributes in VHDL modules can be helpful for the
purpose of
clearness and readability.

Regarding tristate buffers I have the following additional question:

Let's assume the following description of a bidirectional bus with
tristate buffer:

ENTITY xy IS
PORT ( ...
DataInOut : INOUT std_logic_vector(15 downto 0);
...
END xy;

ARCHITECTURE gt OF xy IS
BEGIN
DataInOut <= ls_datareg WHEN ls_drive='1' ELSE (OTHERS => 'Z');
-- with ls_datareg and ls_drive being registers.

END gt;

What does the Altera fitter do if I use the
useioff attribute for the bidirectional DataInOut ?
Does the fitter implement fast input registers as well as fast output
registers ?

Best regards
André

 

[johnp]

Anuja -

Xilinx has a sample program called 'playxsvf' that you can customize
to your environment.

You use the normal Xilinx tools to create your bitfile, then convert it
to a .xsvf file. This is the file that playxsvf downloads.

You can get the source code from the Xilinx web site, I believe it
came with one of their app notes. You then need to modify the source
code to work in your environment.

I've modified the original code from Xilinx to work in several
different
environments including one with some dedicated hardware to do the
bit shifting.

So look around for playxsvf!

John Providenza

 

[johnp]

Anuja -

I found the XIlinx App note that describes playxsvf - look for XAPP058


John Providenza

 

[Symon]

Simon,
Firstly, congratulations on having parents who can spell. Secondly, you may
be interested in this link:-
http://www.fpga-faq.org/FAQ_Pages/0017_Tell_me_about_metastables.htm
Lots of good stuff, complete with a link to this:-
http://www.fpga-faq.org/archives/59375.html#59399
a simple and reliable circuit posted by Rick Collins to transfer a flag from
one domain to another.
Cheers, Symon.

p.s. Isn't Google ads great? At the bottom of the above linked page, I saw
an advertising link for beach footwear! Guess which type....

"Simon Heinzle" <sheinzle@student.ethz.ch> wrote in message
news:4333e8e2$1@news1.ethz.ch...

To exchange flags (1 bit signals) between two unrelated clocks, a single
synchronizer flip flop to clock that signal is used normally. However,
under
violations of setup/hold times of the flip flop, metastability can occur.

On a Virtex2 Pro, does metastability occur often? Does adding a second (or
even third) flip flop after the synchronizer flip flop help or is that
overcautious?

Best Regards,
Simon Heinzle

 

[Adrian Knoth]

S.T. <st@iss.tu-darmstadt.de> wrote:

Debian Sarge with 2.4.6. and WinDriver v6.03 (orig xilinx) or v7.01 gives:

Kernel 2.4.6? This is pretty old, albeit the real problem I suggest
you first update your kernel.

// *** BATCH CMD : setCable -port ttyS1 -baud -1

ttyS1 is a serial (probably rs232) port. I don't own a usb cable,
but even if it emulates a serial port I guess it won't be called ttyS1
(ttyS1 is usually the second serial port, in DOS-speak COM2).

It should also be noted that it is always a good idea to use
up-to-date cable drivers, at least my parallel cable needs
the new windriver (>7.0.0) if I don't want to patch it for
using it with kernels newer than 2.6.11.

--
mail: adi@thur.de http://adi.thur.de PGP: v2-key via keyserver

Wenn die Kuh am Himmel schwirrt, hat sich die Natur geirrt

 

[Mohammed Elbadri]

Does anyone know of another forum or website where I can get an answer to my question?

Thanks. Peace, Moh

 

[Sylvain Munaut]

Nitesh wrote:

Hello Moh,
I have only one master So there is no problem of arbitration I guess.

The problem is that the M_request remains constant at '0'. with no
change even when I try to request a master write operation in my
user_logic.vhd

I enable my IP2bus_wrreq high place a valid address and data on the
IP2bus_addr,IP2bus_data,
IP2Bus_Retry <='0';
IP2Bus_Error <='0';
IP2Bus_ToutSup <='0';
IP2Bus_RdAck <='0';
IP2Bus_WrAck <='0';

My only doubt is what address should we assign to IP2IP_addr.
I think thta is the one which gives the problem.

IP2IP_addr must be the address inside your ip address range where you
want the data to be 'written' (or read).
So if you ask for a master read from 0x10000000 (IP2Bus_addr) to
0x20000000 (IP2IP_addr) (with 0x2000000 being in the address range
assigned to your IP), your slave interface will see signals as if
someone was trying to write to 0x2000000 from the exterior.

Not sure i'm very clear ...


Sylvain

 

[bkuschak@gmail.com]

Thanks. Your comment forced me to closely examine my XCF file. It
turned out to be pilot error - I was missing a semicolon at the end of
line. Doh!

Now it's working.

-Brian

 

[Anuja]

can u get these drivers online or do u have to create one?

 

[Nitesh]

I got that part.I have a user space of 256 bytes with 4 bytes per
block.So the ip2ip_addr address which I am assigning is also correct
but still I cannot get any change on M_request signal.
I have gone through the opb manual and also the opb ipif signals manual
but I still cannot figure out the solution.

 

[Marc Randolph]

francisontheweb@yahoo.com wrote:

Hi,

Recently I noticed that Xilinx FPGA has RocketPHY 10Gbps
serial interfaces using 64B66B encoding. However, it seems
to have no FEC built in the hardware. Is this a problem?
At 10Gbps, the channel won't be clean.
There has to be some FEC one way or the other.

Howdy Francis,

Why won't it be clean, and why do you feel there must be FEC? While
OC-192 has the option for FEC, it isn't required. Same for 10 Gbps
Ethernet.

Can we really let go FEC at 10Gbps (e.g. relying on DFE) ?

Yes - many applications do so. I assume DFE stands for decision
feedback equalizer? If so, I think it's a safe bet that many (most?
or possibly all?) 10 Gbps receivers have some sort of equalization.

Or perhaps user needs to build their own FEC in the FPGA to
use it along? Anyone had experience on this?

I'm certain it could be done, if your application needed the extra
coding gain.

In addition, any other FPGA vendor having 10Gbps serial port
FPGA chips?

No, not yet. Several others provide bonding of four 3.125 Gbps
channels to get you the effective rate in excess of 10 Gbps.

Have fun,

Marc

 

[Philip Freidin]

On 23 Sep 2005 06:51:59 -0700, "Anuja" <thakkar.anuja@gmail.com> wrote:

i dont want to use Impact.. the project requires me to write APIs in C
code such that i can download the bit file w/out using any special
software

Well, even the code you write is "special"

You may find the following helpful:

http://www.fpga-faq.org/FAQ_Pages/0038_Config_FPGA_from_a_processor.htm

Basically, you need some type of interface from your software to
the FPGA hardware for configuration, JTAG is an example, and
the Xilinx Serial Slave mode is another. The serial slave mode
is the simplest. you need a clocl line, a data line, a program line,
and a way to read back done and init. With software you shift the
data out 1 bit at a time to the data pin, and you make the clock
signal go high and low with software too. This is how the old
Xilinx parallel download cable works (for both serial slave and
JTAG modes).

You should be totally confused by now. Let me try and help:

The parallel download cable is called parallel because it
uses the parallel port of the PC. BUT it is used to send
data serially (one bit at a time) by directly controlling
turning various bits of the parallel data on and off. One
of these bit is used as the serial slave clock, and another
is used for serial slave data.

Have a look here at what Xilinx has inside their cable:

http://toolbox.xilinx.com/docsan/data/alliance/jtg/fig26.htm

Once you understand this, everything else is easy

Philip



Philip Freidin
Fliptronics

 

[Adam Megacz]

Some one already told me "Jbits is dead" but didn't explain why !

Because http://www.megacz.com/research/bitstream.secrecy.xt

- a

--
PGP/GPG: 5C9F F366 C9CF 2145 E770 B1B8 EFB1 462D A146 C380

 

[S.T.]

Hi Adrian

Debian Sarge with 2.4.6. and WinDriver v6.03 (orig xilinx) or v7.01
gives:

Kernel 2.4.6? This is pretty old, albeit the real problem I suggest
you first update your kernel.
Mh, tried different versions from 2.4.6, 2.4.26 and 2.6.13 all with the same

error :-(

// *** BATCH CMD : setCable -port ttyS1 -baud -1

ttyS1 is a serial (probably rs232) port. I don't own a usb cable,
but even if it emulates a serial port I guess it won't be called ttyS1
(ttyS1 is usually the second serial port, in DOS-speak COM2).
No i *think* that this is just a message because they ported it from the

serial cable? I haven't seen any use of the usb serial driver from impact,
windriver etc.

It should also be noted that it is always a good idea to use
up-to-date cable drivers, at least my parallel cable needs
the new windriver (>7.0.0) if I don't want to patch it for
using it with kernels newer than 2.6.11.
Yes, the parallel cable works here without problems. But we want do buy more

of these xup boards but if we have to buy new cables for each of these
boards it gets to expensive.

Thanks
ST

 

[Anuja]

Can the downloading of the bit file be done w/out using an embedded
processor or EPROM/PROM as we are just trying to program the device
autonomously. This is not going into production so i dont have to worry
about loosing the configuration data in case of power loss.
Anuja

 

[Newman]

Some of it depends what size/type device you are using, and how much
money you would like to spend.
The DO-ML403-EDK-ISE seems to be a good deal if the target is a FX12
part
http://www.xilinx.com/xlnx/xebiz/productview.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=-1210985&iLanguageID=1&category=/Xilinx+Products/Hardware+and+Cables/Development+Boards/Virtex-4+Boards

If FPGA's and ASIC's are not in your immediate future, I would pass on
Synopsys.

Xilinx Synthesizer works pretty well, and is bundled with the
implementation tools. The above package comes with a baseX version
that limits the size of the device. The full version costs more.

Synplicity is regarded very well, and has the advantage of being able
to target different vendors as with Synnopsys and Mentor.

Don't really have any data on Mentor.

BTW. I own Synplicity stock.

-Newman

Waage wrote:

Hi,

I are looking to purchase some FPGA software in the very
near term for a project utilizing Xilinix's Virtex-4 device.

I are relatively new to FPGA design and would appreciate any comments
from those who have experience with Virtex-4 regarding FPGA synthesis
software
options.

I have looked at Mentor, Synplicity, Synopsis, and Xilinx solutions.
Are there any recommendations for or Against any of the above?
Am I missing a good resonably priceds third party option?

Thanks, Chris