EDK : FSL macros defined by Xilinx are wrong

[Newman]

Some of it depends what size/type device you are using, and how much
money you would like to spend.
The DO-ML403-EDK-ISE seems to be a good deal if the target is a FX12
part
http://www.xilinx.com/xlnx/xebiz/productview.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=-1210985&iLanguageID=1&category=/Xilinx+Products/Hardware+and+Cables/Development+Boards/Virtex-4+Boards

If FPGA's and ASIC's are not in your immediate future, I would pass on
Synopsys.

Xilinx Synthesizer works pretty well, and is bundled with the
implementation tools. The above package comes with a baseX version
that limits the size of the device. The full version costs more.

Synplicity is regarded very well, and has the advantage of being able
to target different vendors as with Synnopsys and Mentor.

Don't really have any data on Mentor.

BTW. I own Synplicity stock.

-Newman

Waage wrote:

Hi,

I are looking to purchase some FPGA software in the very
near term for a project utilizing Xilinix's Virtex-4 device.

I are relatively new to FPGA design and would appreciate any comments
from those who have experience with Virtex-4 regarding FPGA synthesis
software
options.

I have looked at Mentor, Synplicity, Synopsis, and Xilinx solutions.
Are there any recommendations for or Against any of the above?
Am I missing a good resonably priceds third party option?

Thanks, Chris

 

[Nitesh]

I tried the ILA tutorial example exactly the way given in the document.
I tried the vio. No luck either.
"waiting for core to be armed,slow or stopped clock "
I tried the same stuff on a windows machine.Still no luck. I get the
same result.

 

[rhnlogic@yahoo.com]

Peter Alfke wrote:

Your wear-out analogy does not apply.

I did not use only a wear-out analogy, although I did mention
some possibly wear related factors. On the flip side, many
circuit components also have infant mortality failure rates.

Metastability failure is
completely statistical and probabilistic. Even when the MTBF
is a million years, the failure can occur in the next second.

The same is true of a meteor strike on the circuit under
question (given that many are in chaotic orbits), as well
as radiation upset events, thermal noise, even someone tripping
over the power cord, etc.

That's why I claim that the problem can never be solved. We can
only reduce the probability down to an acceptable level.

Then the same must also be true of completely synchronous logic,
because various other design issues also have probability factors
which must also be reduced to acceptable levels to meet design
goals. Good engineering usually involves balancing several risk
factors so that all meet acceptable limits, and without wasting
extra effort on those that are well away from being the limiting
factor.

And I'm not saying that metastability is not a problem at all
(having had to debug a few poorly designed asynchronous input
to synchronous logic circuits in my junior engineer days). But
there are a number of papers on the subject which essentially
reduce some forms to solved problems for many given reliability
levels when using properly designed and characterized flip-flops
(as I assume your employer has done) with sufficient delay time
and/or delay cycles for resolution with a probability which
meets or exceeds that required for the given product reliability.


IMHO. YMMV.
--
Ron
rhn A.T nicholson d.O.t C-o-M

 

[mice]

Problem solved. Sorry for taking up space (and bumping)...
Left clicking on icon is export and selecting "Program Device" works
fine.

Cheers!
((mice

 

[seb_tech_fr]

Why don't you used Chipscope Inserter instead of instantiating ILA and
ICON in your design?
According to my personnal experience, when Chipscope says "Waiting for
Core to be armed, slow or stopped clock", it generally means that your
system clock is not working.

---------------------------------------------
-- TechwaY
-- TechwaY
Partners
-------------------------------------------

 

[Kris Vorwerk]

I need an ARM environment, hopefully a complete ARM9 and bus, on an
FPGA to prototype multiple copies of a custom, loosely coupled, media
signal processor. The MSP is about 50K (real) gates with 16KB of
dual-port memory on each. I'd like to try to hang two of them (total
100K gates and 32KB dual-port) off an AHB or AHB2 to test the
interprocessor communication with an RTOS plus driver/manager software.

The old Altera Excalibur looks like the ideal solution, especially if I
can find an old EPXA10 DDR Dev Board.

While not identical to what you specified, this still might be of interest
to you ...

http://www.actel.com/products/ip/ARM7.html

Kris

 

[Nitesh]

I tried both ways , instantiating as well as the inserter but still no
luck.
Nitesh

 

[Phil Hays]

"Waage" <chris@ednainc.com> wrote:

I have looked at Mentor, Synplicity, Synopsis, and Xilinx solutions.

I've had good experience with Synplicity. Smaller and faster results,
easier to use, good technical support.

Xilinx does ok. Price is right. Good choice as long as speed and
density are not critical, or if speed and density are so critical as
to force the designer to map all logic by hand.


--
Phil Hays to reply solve: phil_hays at not(coldmail) dot com
If not cold then hot

 

[Eric DELAGE]

If you can afford the price of Synplicity, I would definitively
recommend you Synplify Pro for the quality of its results.

The only drawback that I think of is stability. It performs very well
but it might (not so rarely) happen that it crashes w/o any result.
Fortunately, the support is very reactive to provide us w/ new releases
fixing the issues.

Has someone a significant experience w/ Amplify (or the new
SynplifyPremierDP) from Synplicity? What do you think about it?

Eric

 

[Ashok]

One more problem with ISE XST. In Synthesis Constraint file (.xcf) you
can not use wildcards.

 

[Frank van Eijkelenburg]

Sean Durkin wrote:

Frank van Eijkelenburg wrote:

Does anyone have experience with running the plb bus at 125 MHz and
using the ipif interface?

The last EDK I worked with was 3.2, and I was using a Virtex 2 Pro, but
"back then" it said in the documentation (the PDF you get when you open
the documentation in the graphical editor) that the maximum frequency
for the PLB is 100MHz, so I never even tried going faster.

Don't know where the restriction comes from, though, i.e. if it has
something to do with the FPGA fabric not being fast enough (in that case
a V4 should be better) or the CoreConnect-IP...

cu,
Sean

Documentation for PLB bus indicates a frequency between 141 MHz and 194
MHz (for a virtex 2 pro -7). Documentation for the IPIF interface
indicates a frequency between 101 MHz (using all services) and 189 MHz
(for a virtex 2 pro -6). This is documentation that belongs to edk 7.1.
Since the used ipif interfaces in my design won't use special services
(only burst support is used), I expect it shouldn't be any problem?!

Frank

 

[Ed McGettigan]

Nitesh wrote:

I tried the ILA tutorial example exactly the way given in the document.
I tried the vio. No luck either.
"waiting for core to be armed,slow or stopped clock "
I tried the same stuff on a windows machine.Still no luck. I get the
same result.

Have you double checked that you have an active clock in the FPGA?

If you connect the clock in the system to an asynchronous VIO input
does it toggle?

Ed

 

[melbadri]

Are you using "T!" (Trigger Now and Display Buffer Data Samples) button
or ">" (Apply Settings and Arm Trigger) button. As well on what are
you triggering (what signals)? If it is the clock then I would
recommand to change that because the clock is too fast to be caught by
Chipscope. I'm using the Multimedia board with 27 MHz as my clock. My
trigger is not my clock it's some data signal. However I have my clock
as one of my output data and all I see is a constant '0' on the clock
signal output hence Chipscope can't catch it.

Hope I'm clear and hope this helps.

Peace,
Moh

 

[John_H]

Synplify Pro now has a "message window" that sorts all the notes, warnings
and such in groupings. There is a filter included to ignore those messages
we all "know" aren't of any help. It's better than trying to look through
the log but it's still not the best interface. Cartainly an improvement,
however.

"Simon Peacock" <simon$actrix.co.nz> wrote in message
news:433a65a9@news2.actrix.gen.nz...

The one main complaint I have with symplify is the number of warnings and
messages it generates... I like to check them off and say "that's ok" ...
"that's unnecessary" etc .. but I haven't found a way to turn the
unnecessary ones off.

Typically this happens on some of my standard modules which might have
unused pins or internal blocks which are going to be optimized out, but
will
leave a signal or two (which will also be optimized away).

Altera fixed this with the 'if_used' attribute in AHDL... but that's gone
by
the wayside since AHDL isn't supported any more.
The other annoying one is where ROMS are generated and it optimizes
columns
out as they aren't unique ... something's you just don't care about

Simon

 

[Hans]

Hi Alan,

I believe there is a generic Nios clone called Manik (see
http://www.niktech.com), just contact them to see if they can synthesis it
to a ProASIC. Other cores with good support (gcc/Linux) are the excellent
Leon2/3 core and the OR1200 from Opencores. If you really want 16 bits you
can look at my 8088 core
(http://www.ht-lab.com/hardware/APABoard/APABoard.html). It requires as a
minimum an APA450 and runs at about 16MHz. You can also wait until Actel
releases the ProASIC + ARM core

Hans
www.ht-lab.com


<amyler@eircom.net> wrote in message
news:1127915110.847546.293070@g14g2000cwa.googlegroups.com...

Can anyone recommend a 16-bit microprocessor core to use in an Actel
ProAsic+ device.

I'm familiar with Altera Nios and would like to find something similar
in complexity, performance, and ease of use (compiler, monitor etc).

Any suggestions?

Alan Myler

 

[Rene Tschaggelar]

henrique.portela@gmail.com wrote:

Hi All,

I am developing a board using Virtex FPGA. Right now i am using Protel,
but i am not being able to use the "Equilize net lenghts" nor the
auto-route.
I wonder if there is any software better than protel to develop pcb
boards. Does any one know which software xilinx use??

Both features can be considered experimental.
There are other packages, not to be considered
bargain packages such as protel that are able
to do this. Are you sure you want to learn it
price ?

Rene

 

[Falk Brunner]

"Rene Tschaggelar" <none@none.net> schrieb im Newsbeitrag
news:433d7fe4$0$1150$5402220f@news.sunrise.ch...

I am developing a board using Virtex FPGA. Right now i am using Protel,
but i am not being able to use the "Equilize net lenghts" nor the
auto-route.
I wonder if there is any software better than protel to develop pcb
boards. Does any one know which software xilinx use??

Both features can be considered experimental.
There are other packages, not to be considered
bargain packages such as protel that are able
to do this. Are you sure you want to learn it
price ?

And beside, the automatic "Equalize net lenght" in other REALLY expensive
EDA packages (lets say from vendor "M") isnt that usefull at all. Best
results with minimum trouble is to use a half-automatic tool (such a thing
that displays the actual netlength in real time while you move the traces).
Been there, done that.

Regards
Falk

 

[Falk Brunner]

<henrique.portela@gmail.com> schrieb im Newsbeitrag
news:1128106917.840181.240320@g47g2000cwa.googlegroups.com...

Can you give me examples of software with that feature?

As I said, vendor "M" (aka Mentor Graphics) has this feature. But the
packages are REALLY expensive.
I dont know about other (mortal price) software with this feature.

Regards
Falk

 

Which tools form vendor M ?? Does Pads have that feature?

 

[Gabor]

troy.scott@latticesemi.com wrote:

Gabor,

I've been able to the GUI environments for ISE, ispLEVER, and Quartus
with no modifications under Win2000. However, if you run your program
executables from the command line, you will need to manage the
enviroment variables for ISE and ispLEVER since the tools use similar
executable names (NGDBuild, MAP, PAR, etc.).

I've also found conflicts between the Actel and Lattice-Editions of
Synplify which are provided with the free "starter" tools.

Best Regards,
Troy Scott
Lattice Semiconductor TME

Thanks fo the info. I have already installed ispLEVER on my machine.
The conflict with Quartus was not with ISE, but the older Foundation
(Aldec-based) tools. With Quartus installed I lost the ability to
compile Abel modules (yeah we have some really old code here). So
now I have two versions of Xilinx and ispLEVER on the same machine
and haven't found any conflicts yet (at least with Xilinx tools, I
haven't played with the ispLEVER very much yet).

Regards,
Gabor Szakacs