EDK : FSL macros defined by Xilinx are wrong

[John_H]

"geoffrey wall" <wallge@eng.fsu.edu> wrote in message
news:dg4n2j$dqk$1@news.fsu.edu...

how can you reduce the number if IOBs a design uses
during synthesis?

thanks

Specify fewer input/output ports in the top level of the hdl file or
schematics.

 

[Duane Clark]

Ram wrote:

Hi,


Does ISE 7.1i use the same install code for Windows as it does for Linux? A
Xilinx rep told me they are the same.

Yes, they are the same.

 

[Mark McDougall]

Jon Schneider wrote:

Is Kingston SDRAM really that bad ?

I agree with the other posters in this thread, and would tend to suspect
my own design before suspecting the SDRAM...

... but ...

A few weeks ago we bought three new PCs for the office. All with 2GB
SDRAM, and all but one of the 1GB modules was some brand which I have
never heard of, and can't recall (the last was a Corsair). I started
having problems with my PC rebooting for no reason. Starting running a
comprehensive memory test and it showed hundreds of bit errors
overnight. The other guys here ran the same tests and, although not all
quite as bad, all had bit errors in an overnight test.

We went back and exchanged the RAM (including the Corsair, which did
*NOT* fail) for another brand, and re-ran the tests. *Zero* errors on
all 6 modules.

Now that *could* be put down to crappy mobo design (they're identical
machines) or bad SDRAM, but it is food for thought...

Regards,
Mark

 

[Jim Wu]

FWIW, I had to use different registration code for windows and linux.

Jim

"Ram" <r_fpga_dev@yahoo.com> wrote in message
news:AflVe.5881$Gh.4642@tornado.socal.rr.com...

Hi,

I've read through the archives for notes and hints on installing ISE 7.1i
for Linux.

I got curl, portmap, motif, etc all installed. The installer now comes
up.

However, when I enter in the Registration ID, it keeps telling me that
it's
invalid.

Does ISE 7.1i use the same install code for Windows as it does for Linux?
A
Xilinx rep told me they are the same.

Any help would be appreciated. This is very frustrating!

Ram.

 

[JJ]

Adrian wrote:

Hi,
I seem to be getting a higher P&R speed (I put a constraint on the only
clk I have in the design) than that I got from synthesis. Sometimes by up to
10 MHz. Is that possible? I am using ISE 6.3 and targeting a Virtex 2
1000 -4.

Thank you
Adrian

I have seen that too on occasion, usually the very next change to the
code fixes it right away

JJ

 

[S.T.]

Hi Kris

Kris Heyrman wrote:

I have been working off and on trying to use the Xilinx XUP board on
Linux Fedora Core 3 with EDK 7.1 and ISE 7.1. I have been fairly
succesful with the software, but downloading the bitstream over the USB
cable has got me baffled. It has worked a few times, but most of the
time there seem to be errors in transmission and this makes the board
trying to do this:
So you are more successfull than i. I asked Xilinx about it 2 month ago and

the answer was that in a later revision the usb adapter of the XUP will
work. But it seems as if ise71sp4 still doesn't do the trick for me. But in
my case i am not able to upload some code since the three chips are marked
as unkown. Digging around i found that this seems to be a special version
of the ez-usb device which needs a firmware loaded via fxload (take a look
at the /etc/hotplug/usb/xusbdfwu xusbdfwu.fw files). My suspection is that
this XUP doesn't work with the standard firmware distributed with ise71
(bin/lin/xusbdfwu.hex). Probably there is a way to extract this hex from a
windows driver version. But at a first glance i found no hexfile in the
windows ise.

Date: Apr 26 2005. Xilinx patches for ISE and EDK have been applied.
ise xinfo tells you the exact version. Could you give me your version

number? I would be interested which firmware is loaded into your board.
does
diff /etc/hotplug/xusbdfwu.fw/xusbdfwu.hex $XILINX/xusbdfwu.hex
give some output?

Is there a good way to determine what is causing this unreliability?
Are there any tests I can perform? I would be very grateful for any
suggestions.
The easiest way is to use an good old paralell cable V and connect with this

cable. But i would also be really interested in a real usb solution :-(

Hope this helps
S.T.

Hey Xilinx are you listening?

 

[B. Joshua Rosen]

On Tue, 13 Sep 2005 00:00:43 -0700, Paul Gentieu wrote:

Here's a benchmark for PAR (high effort level) running on two different CPUs. The design utilized about 40% of an XC2V4000-5 and had some difficult-to-meet timing constraints. PAR's peak memory usage was ~500 MB.

Intel Pentium D 830 (3.0 GHz), 2 GB RAM: Total CPU time to PAR completion: 2 hours 32 mins

AMD Athlon 64 4000+ (2.4 GHz), 2 GB RAM: Total CPU time to PAR completion: 1 hour 2 mins

I was blown away by the result. I was expecting a modest speed increase with the AMD- maybe 1.3x, if you go by the model number- but certainly not 2.5x. Based on this benchmark, the AMD CPU should actually be called a 7500+.

The Pentium is a dual core and the AMD is a single, but the Xilinx software utilizes only one core so this is a fair comparison of raw processor speed.

The Pentium probably gets killed by its deep pipelines. I'd guess that PAR, like most real-world apps, consists mainly of spaghetti code rather than regular loops processing masses of similar data. So the Pentium spends a lot of its time flushing pipelines because of mispredicted branches and such. It probably suffers from its higher memory access latency as well.

It sure would be nice if Xilinx could made their software multithreaded... then an Athlon X2 4800+ would really scream. As it is, I'd guess that an Athlon FX-57 (2.8 GHz) will give the fastest PAR performance currently possible.

-Paul

That's consistent with what I've seen. Note the 4000+ has a 1M cache which
is critical for the performance of EDA codes. For NCVerilog I've found
that when recordvars is off there is a 2 to 1 difference between an A64
with a 1M cache vs one with a 1/2M cache. I now have a 4400+ in addition
to the 3400+ and the 3800+ shown on this page,

http://www.polybus.com/linux_hardware/index.htm

I haven't updated my benchmark page with the the 4400+ results but they
are consistent with the other results. The 4400+ is about 10% faster then
the 3400+ on single threaded jobs like NC or Xilinx place and results
which is exactly what you would given that each core in the 4400+ runs at
the same clock speed and has the same cache size (1M) as the 3400+ but it
has dual memory channels vs a single channel on the 3400+.

 

[Giox]

The post route verilog (it starts as follow the following)

// Xilinx Verilog netlist produced by netgen application (version G.30)
// Command : -sim -ofmt verilog -sdf_anno true -w -s 8
FIOS_with_FSM_out
// Input file : FIOS_with_FSM_out.ncd
// Output file : FIOS_with_FSM_out.v
// Design name : FIOS_with_FSM
// # of Modules : 1
// Xilinx : /mentor/software/xilinx
// Device : v300efg456-8 (PRODUCTION 1.69 2003-12-13)

// This verilog netlist is a simulation model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used

// with supported simulation tools.

`timescale 1 ns/1 ps

module FIOS_with_FSM (
CLK, READY, RESET, S_parameter
);

 

[Giox]

The post place and route module is:

module FIOS_with_FSM ( CLK, READY, RESET, S_parameter);

and the testbench is as follows:

`resetall
`timescale 1ns/10ps

module test_FIOS_with_FSM ;
// Inputs
reg CLK;
reg RESET;
reg [7:0]S_parameter;

// Outputs
wire READY;

// Instantiate the Unit Under Test (UUT)
FIOS_with_FSM uut (
.CLK(CLK),
.RESET(RESET),
.READY(READY),
.S_parameter(S_parameter)
);

////////////////////////////////////////////////////////////////////////////////
initial
CLK = 1'b0; //set clk to 0
always
#25 CLK = ~CLK; //toggle clk every 5 time units
////////////////////////////////////////////////////////////////////////////////


initial begin
// Initialize Inputs
RESET = 1;
S_parameter = 8'b00001100;
#100;

RESET = 0;
S_parameter = 8'b00001100;
#100;
end
endmodule

It seems to me that it is correct but if you note something wrong let
me know

 

[Ram]

Hi Josh,

B. Joshua Rosen wrote:

The Xilinx installer is very distribution sensitive although the tools
aren't. I keep Whitebox Linux 3 (RHEL3) on one of my older machines and do
by Xilinx installs there, once the install is done I rsync the Xilinx
directory to by other machines.

Yes, seems like it!

Which directories do you end up having to rsync? Just one installation
directory?

I might go this route if I have to.

Thanks,
Ram.

 

[Mark McDougall]

jai.dhar@gmail.com wrote:

Regarding the PC RAM issue, is anything being overclocked? That seems
really odd that they would mostly all fail... on all the PC's for
that matter. I would try the RAM in another PC and see what happens.

No, these are office PCs so everything is factory settings on Gigabyte
mobos. The RAM is long gone - returned to the shop for replacement. And
going from 100+ errors overnight (6 modules on 3 mobos) to zero errors
with the new RAM is pretty damning evidence IMHO.

Regards,
Mark

 

Thanks a lot Valdislav and Sean.
You people made my day.

Regards
Williams

 

[Jim Granville]

they call me frenchy wrote:

I am thinking of using a lowcost CPLD as a brain to do various logic
functions in addition to driving 3 separate PWM generators. The PWM
generators will receive their intputs from a state diagram that is
cycled through via a pushbutton. Sounds simple. Does anyone object
to using a very low cost CPLD for this?

Obviously there are many more details involved, like the battery
powered, low power requirement (Coolrunner II, maybe)...but I just
wanted to have a general discussion at this point.

The choice will depend on how many macrocells you actually need,
and the cost relative to alternatives. eg there are many small
uC that can handle 3 PWMs, but a CPLD might give speed or resolution or
protection advantages.
Lowest power 5V parts are Atmel ATF150xASL, and lowest power
1.8V parts are Xilinx Coolrunner and Lattice Mach4000Z series.
-jg

 

[Simon Peacock]

The truth is (e) none of the above...
if you order 500,000 you can have the first shipment in 4-6 weeks
if you order one then its 12-16 weeks

I would ask your dist how much and how soon.. because he will do his best to
get them to you on time or will loose the business.

Simon


"Finn S. Nielsen" <removfinnstadel@tiscali.dk> wrote in message
news:43272fa7$0$67259$157c6196@dreader2.cybercity.dk...

Does anyone know what the current delivery situation is for
XC3S1000-5FT256C.
On Xilinx's website they say 3-4 weeks, but from Memec they say more than
8
weeks.
Does anyone know the truth here.. Austin ?

Finn

 

[B. Joshua Rosen]

It sure would be nice if Xilinx could made their software multithreaded... then an Athlon X2 4800+ would really scream. As it is, I'd guess that an Athlon FX-57 (2.8 GHz) will give the fastest PAR performance currently possible.

-Paul

PAR is multithreaded, use the -m switch.

 

[Symon]

"Mike Treseler" <mike_treseler@comcast.net> wrote in message
news:3ore1nF7di2fU1@individual.net...

JTW wrote:
Attached is my first cut at an address decoder. While it works I am not
sure it's the best method. Also I am not sure why there are four 4:1 muxes

in the design.

Any help or ideas?

Yes. Get a better text editor.
Need to eliminate the tabs and
add a few line feeds.

I agree. If you're gonna code like that, you might as well use Verilog.

Cheers, Syms.

 

[David Brown]

they call me frenchy wrote:

On Wed, 14 Sep 2005 11:54:14 +1200, Jim Granville
no.spam@designtools.co.nz> wrote:


they call me frenchy wrote:

I am thinking of using a lowcost CPLD as a brain to do various logic
functions in addition to driving 3 separate PWM generators. The PWM
generators will receive their intputs from a state diagram that is
cycled through via a pushbutton. Sounds simple. Does anyone object
to using a very low cost CPLD for this?

Obviously there are many more details involved, like the battery
powered, low power requirement (Coolrunner II, maybe)...but I just
wanted to have a general discussion at this point.

The choice will depend on how many macrocells you actually need,
and the cost relative to alternatives. eg there are many small
uC that can handle 3 PWMs, but a CPLD might give speed or resolution or
protection advantages.
Lowest power 5V parts are Atmel ATF150xASL, and lowest power
1.8V parts are Xilinx Coolrunner and Lattice Mach4000Z series.
-jg



Mr. Granville,

Thank you very much for your response. Since this is my 1st
programmable logic project since college, I really dont know how many
macrocells I will need yet. I am in the process of learning VHDL
right now and coding the most efficient triple 8-bit PWM
imeplementation that I can. It is going well, but it will still be
1-2 days before I can compile it and see how many macrocells are
required. (I am using Xilinx's free ISE 7.1 software).

When you say there are many small uC that can handle 3 PWMs, can you
give me a couple of specific examples so that I can compare their
cost/functionality? I admit to you that although I graduated with an
EE degree, I have been a musician and running a recording studio for
the last several years. I am just now getting back into the EE loop,
but I love it and am moving forward quickly. Unfortunately, the fool
in me has no idea what you are referring to when you say uC. It
probably means microcontroller, but I have never used one and I dont
know if they are re-programmable like CPLDs are. The reason that I
was looking into the Xilinx Coolrunner II is because I need ultralow
power consumption and I found the price on their smallest one
(32macrocells) to be $0.85 at quantities of >100k. I hope I can fit
it into the smallest one!

thx again,
frenchy

Unless you have complex timing requirements, a small micro would be the
best for making 3 PWMs. Get a small msp430 processor - they are cheap,
easy to work with, and have good free tools (the gcc port is excellent,
and there are free versions of ImageCraft and IAR tools for limited
program sizes).

 

[Alex Gibson]

"Mancini Stephane" <nospam@nospam.nospam> wrote in message
newsan.2005.09.15.12.26.07.96556@nospam.nospam...

Hi all,
Does anyone has implemented a SATA link on Xilinx V2Pro to connect to a
hard disk drive ?
Indeed, we have the Xilinx XUP V2Pro Dev board from Digilent and it has a
SATA connector. So I'm wondering if one can control a hard disk drive from
this SATA connector.
Furthermore, I would like to mount the disk on linux running on the PPC.
I've already compiled and installed an own driver on linux and I'm
wondering if it would be possible to mount a SATA hard disk drive.

Do you have any information about such development ?

Thanks a lot for your help

Stéphane

I believe all you need is to power the drive and to have a kernel compiled
with sata support.

I want to do this with the xupv2pro board but haven't had the time.

Could also use uclinux as well.
http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/
http://www.itee.uq.edu.au/~wu/downloads/uClinux_ready_Microblaze_design.pdf

Alex

 

[they call me frenchy]

On 15 Sep 2005 10:35:32 +0200, David Brown
<david@westcontrol.removethisbit.com> wrote:

Unless you have complex timing requirements, a small micro would be the
best for making 3 PWMs. Get a small msp430 processor - they are cheap,
easy to work with, and have good free tools (the gcc port is excellent,
and there are free versions of ImageCraft and IAR tools for limited
program sizes).

David,
Thank you very much for your response. I am new to programmable logic
and I really appreciate the suggestion. Just to make sure that I
paint the entire picture, here are my full requirements...

1) 3independent PWM generators running at the same frequency. I am
starting with 8-bit, but I could justify going down to 7bit and
maaaaaaybe 6 or even 5 bit if it will save me much grief.

2) The FSM will probably have 8 states (cylcled through with a simple
pushbutton, no reset). State 1 will tell PWM1 to run at 90% and PWM2
and 3 to be off. The rest of the states will turn the PWMs off and on
in a variety of ways. The most complex of the states will tell all 3
PWMs to cylce from 10% to 90% out of phase from each other at about
0.5Hz. I do not have complex timing requirements.

3) I would like to detect the battery voltage and when it is running
semi low, I would like to scale down the values of ALL PWM signals to
extend battery life. For example, full battery = all PWMs @ 100%,
battery 1/2 dead = all PWMs @ 50%, battery pretty much dead = sleep
mode until the batteries start to receive a recharge, which could be
several hours away.

I got a Coolrunner II development kit just to get going with a
256macrocell chip onboard. I will plan on testing my functionality on
that even if I fill the whole damn thing and then perhaps migrate to
your recommended MSP430 after some research to prove why that would
indeed be better than a CPLD.

My application is geared towards a very high quantity consumer part,
so I would like to see the chip cost under US$1 at quantity. I know
that I have an uphill climb in front of me and my boots are on.

If I indeed switch over to a MSP430, will my VHDL code that I am
writing now be able to come with me?

admitted newbie with big goals,
frenchy

 

Atmel has an example that fits 4 8-bit PWM controllers in a 32
macrocell CPLD. It is written in CUPL.

You need to download their tools at:

http://www.atmel.com/dyn/products/tools_card.asp?tool_id=2759

The file is PWM8X4.PLD

kevin