EDK : FSL macros defined by Xilinx are wrong

[perica]

It would be a case if delta cycle in simulator is set to the same
value as clk period.

 

[icegray]

Hi,
Orcad has these features? You think which is better Orcad or PADS? (why)

 

[Karthikeyan Subramaniyam]

Simon
he's asking about how to use multi-dimentional arrays in port
declaration. not for signal/variable declaration.

Rgds,
Karthik


Simon Peacock wrote:

first you create a type.. then assign it...
type v_typ is array (2 downto 0) of std_logic_vector(11 downto
0);
signal v: v_typ

now you can access it as
v(i)(j) <= -- something

Simon



"eeh" <eehobbyist@yahoo.com.hk> wrote in message
news:1128136736.906033.205550@z14g2000cwz.googlegroups.com...

Hi,


I am just beginner of VHDL. I want to define a 2 dimensional input
variable in entity. I think the syntax is something like this:

v : in std_logic_vector(2 downto 0)(11 downto 0);

Please advice. Thanks!

--
Karthikeyan Subramaniyam,
Verification Engineer,
TooMuch Semiconductor Solutions Pvt. Ltd.
www.toomuchsemi.com
A Bangalore based startup specialising on services in EDA & Verification.

 

[wanch]

Could you suggest some devices which are suitable to run at a clock
rate more than 311MHz?

 

[Brad Smallridge]

The ML401 is a great board, and great value, but the
rgb output just sucks.

I am interested in this problem. What do you mean the
RGB sucks? There is a real RGB chip on the board right?
Is there something wrong with that chip?

I read on the Xilinx web site that some of the analog gnds
are mixed up with the digital gnds. Is it possible to lift these
pins and ground them to the right places and improve the
RGB output?

Brad Smallridge
aivision.com

 

[Pete Fraser]

"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message
news:11jtqvs3d0mbbc3@corp.supernews.com...

The ML401 is a great board, and great value, but the
rgb output just sucks.

I am interested in this problem. What do you mean the
RGB sucks?

The video out has asynchronous resonant spikes running
through it. The spikes are about 100 mV p-p, and have a
resonant frequency of about 250 MHz, with about 6 half-cycles
present.


There is also about 15 mV p-p of pixel clock and harmonics.

There is a real RGB chip on the board right?
Is there something wrong with that chip?

I don't think so. It's a fine chip that I've used in many designs.

I read on the Xilinx web site that some of the analog gnds
are mixed up with the digital gnds. Is it possible to lift these
pins and ground them to the right places and improve the
RGB output?

I have not tried that. It's often tricky to get a decent,
low-impedance alternative ground.

Brad Smallridge
aivision.com

Pete

 

[Thomas Entner]

The video out has asynchronous resonant spikes running
through it. The spikes are about 100 mV p-p, and have a
resonant frequency of about 250 MHz, with about 6 half-cycles
present.

There is also about 15 mV p-p of pixel clock and harmonics.

Hard to believe when Xilinx tells us that they are signal integrity
leader...

(Sorry, just could not resist ;-)

Thomas

 

[Ray Andraka]

Kolja Sulimma wrote:

vssumesh wrote:


Ok .. but is it easy to simulate? And if we code it in a hierarchial
tree will it take more area than required. Please give little more
details in this.


Also try to think about whether you really need a random accessible mux
in your case. For example if you allways need the inputs in the same
order you can load all of them into a shift register and shift them out.

Kolja Sulimma


you can get better pipelined performance by decoding the selects before

the first level then combining the first level outputs in an OR tree.
You can also use the carry chains, or if using virtexII the horizontal
or chains with this method to help reduce the size of the logic. This
is for a random selection sequence. As Kolja said,, a shift register
might be a better choice if you can constrain the selection order. If
it is to read back registers that you've written into a design, you can
use a block ram as a shadow for the registers and read back the block
RAM. Finally, if you can afford the latency, you can get better place
and route results by going with a linear structure.



--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Newman]

Francis
I used to run this little script (below) after running ProjNav.
There are other options to data2bram that help verify the correct data
is going to the right bram.
This worked with ISE6_2.

-Newman

#######################################################################
# This script runs data2bram to populate BRAMs with program
information.
# This is automatically generated by LibGen.
#
#######################################################################
echo Initializing BRAMs with program information ...
echo Inserting executable image

data2bram -bm implementation/system_bd -bt projnav/system -bd
ppc405_i/code/executable.elf tag bram1 -o b projnav/download.bit

 

[Kevin Brace]

Hello Broaddown2 customers,

Those users considering purchasing Broaddown2 Development Board for
personal projects might also want to consider purchasing BDS XPCI PCI IP
core to accelerate the development.
BDS XPCI PCI IP core is a Xilinx (TM) LogiCORE (TM) PCI compatible
(replacement) PCI IP core developed by Brace Design Solutions.
BDS XPCI32 PCI IP core is available for as little as $100 for
non-commercial, non-profit, personal use, and the same 64-bit version
BDS XPCI64 PCI IP core (Includes BDS XPCI32 PCI IP core) goes for $200.
Since the pricing starts at only $100, it is ideal for HDL learners,
FPGA beginners, FPGA hobbyists, computer hardware enthusiasts, or
student graduation projects.
BDS XPCI PCI IP core comes with a PCI testbench for Verilog HDL which
allows the user to simulate the design extensively on an HDL simulator
like ModelSim before firing up the FPGA.
VHDL support is currently poor, but VHDL porting of reference designs
and PCI testbench should be available in a month.
BDS XPCI PCI IP core officially supports the following PCI boards.

- Insight Electronics Spartan-II 150 PCI (Already discontinued)

- Insight Electronics Spartan-II 200 PCI Development Kit
http://www.memec.com/uploaded/SpartanII200PCI.pdf


BDS XPCI PCI IP core "unofficially" supports the following PCI boards.

- Avnet Xilinx Spartan-3 Evaluation Kit
http://www.em.avnet.com/evk/home/0,1719,RID%253D0%2526CID%253D7816%2526CCD%253DUSA%2526SID%253D4742%2526DID%253DDF2%2526SRT%253D1%2526LID%253D18806%2526PVW%253D%2526BID%253DDF2%2526CTP%253DEVK,00.html
http://www.em.avnet.com/ctf_shared/evk/df2df2usa/Xilinx%20Spartan-3%20Evaluation%20Kit%20-%20Brief%20022504F.pdf

- Enterpoint Broaddown2 Development Board
http://www.enterpoint.co.uk/moelbryn/broaddown2.html


So with BDS XPCI PCI IP core, almost anyone can make their own PCI
device for about $400 to $500. ($300 to $400 for the board + $100 for
BDS XPCI32 PCI IP core)
For commercial users who want to modify a Xilinx LogiCORE PCI or want to
convert a design that uses Xilinx LogiCORE PCI to an ASIC (FPGA to ASIC
conversion), BDS XPCI PCI IP core is also available in Verilog HDL RTL.
For more information, visit Brace Design Solutions website at
http://www.bracedesignsolutions.com.


Kevin Brace


John Adair wrote:

For all the hardened FPGA addicts and please excuse the sales push.

If anyone is interested in our lower spec Broaddown2's BD2-400, BD2-1000
then we are having a stock clearance next week. Details will follow on our
website shortly but pricing will be GBPŁ160 (BD2-400) and GBPŁ190 (BD2-1000)
only while stock lasts.

Our MINI-CAN boards now have an uprated spec for those intersted in these
boards. Details to follow on the website but essentially you get a XC3S1000
now in the FPGA hole.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development
Board.
http://www.enterpoint.co.uk

--
Brace Design Solutions
Xilinx (TM) LogiCORE (TM) PCI compatible BDS XPCI PCI IP core available
for as little as $100 for non-commercial, non-profit, personal use.
http://www.bracedesignsolutions.com

Xilinx and LogiCORE are registered trademarks of Xilinx, Inc.

 

[Andy Peters]

sk.sulabh@gmail.com wrote:

I am using ISE tool for implementing my design.But i am facing a
problem.In this tool it is written that some modules are supported to
infer rather than inatantiate. My prof says to make design wholly
structural . and using the modules available, just like we do in
shematic. But since for some design elements , instatiating is not
supported, i cant do it.I have to write a module code to infer that
module.but according to prof this should not be the way.

I'm not sure what your professor is getting at.

Is he implying that you should always instantiate everything, even
primitives such as AND gates? If so, then there's little point in
using an HDL.

I suppose, though, that in a logic design course, it's vital that you
learn the basics, so rather than coding a counter as count <= count + 1
mod LENGTH, perhaps your professor is requiring that you learn what
goes into creating a counter. That's a separate issue, though.
Hopefully your professor is making this clear.

It's certainly possible to write structural HDL code that infers
various logic elements, from the simple (like AND gates) to the complex
(like counters and memory elements). I do it all the time!

Second thing while making these design elements (like counter) with
flip flop and gates (for which instantiation is supported), its min
clock period is large compared to the one which is inferred.Suggest me
what can do here.

Here's where inference helps you. The synthesis tool recognizes
certain structures and knows about the specifics of the chip
architecture and how to map those structures to the chip efficiently.
I'll bet that in your case, your flops-and-gates implementation of a
counter doesn't take advantage of an FPGA's special carry chain. And
hopefully you're not coding a ripple counter!

-a

 

[Antti Lukats]

"Simon Peacock" <simon$actrix.co.nz> schrieb im Newsbeitrag
news:433f22f3$1@news2.actrix.gen.nz...

who the F*** designed your web site.... I know putting frames around
product
briefs lets you keep your logo.. but that's almost 2/3's of the screen
gone...

Simon

translated: fire your web designer

Thanks Simon!

no translation required, I agree with you 2000 %,
but I have no influence to solve the issue.

Antti
PS its not my website. Its from the company I work for at the moment.
(my contract ends 31.12.2005)

 

[vssumesh]

Hello Simon,
Yes i am trying to implement the 64 nos of 8bit wide (240:1) mux.
And there is 240 * 64 = 15360 total selction bits (240 bits to each
mux). And 240 * 8 = 1920 data bits to whole block of 64 muxs (same data
goes to all MUX). Thus the mux array block will have 17280 input lines
and 64 * 8 output lines. Why you are saying that it is not possible.
All signals are internally generated from other parametrs (I dont know
the internal routing efforts of the FPGA). Please advice.
The mux (the code) you suggested is a single 240 to 1 byte mux. But i
want 64 copies of that. Is that possible. I know that it is not
possible to implement it in asingle design by getting the selction
signal from external sources; is it because of this constrain that the
ISE stops working. I am able to get output if i reduce any of the
parametrs to half (no: out put or no: registers etc).

 

[Adarsh Kumar Jain]

you can try to delete the project implementation files and retry. I also had
this portability error but with a different message but it went off once i
deleted the project implementation files.
Cheers,
Adarsh
"Matthew Plante" <maplante@iol.unh.edu> wrote in message
news:dhjtlc$80c$1@tabloid.unh.edu...

Has anyone else received this error with ISE 7.1i? I added a peripheral
to my embedded system, and when I re-synthesize it it XST, I get:

ERRORortability:3 - This Xilinx application has run out of memory or has
encountered a memory conflict. Current memory usage is 798040 kb. Memory
problems may require a simple increase in available system memory, or
possibly a fix to the software or a special workaround. To troubleshoot or
remedy the problem, first: Try increasing your system's RAM.
Alternatively, you may try increasing your system's virtual memory or swap
space. If this does not fix the problem, please try the following: Search
the Answers Database at support.xilinx.com to locate information on this
error message. If neither of the above resources produces an available
solution, please use Web Support to open a case with Xilinx technical
Support off of support.xilinx.com. As it is likely that this may be an
unforeseen problem, please be prepared to submit relevant design files if
necessary.

Any ideas?


Thanks,
-- Matt


+--
|Matthew Plante
| University of New Hampshire
| InterOperability Lab
| Research & Development
| SMTP: maplante@iol.unh.edu
| Phone: +1-603-862-0203
+-

 

[Simon Peacock]

I always think some positive feedback is important

Simon


"Antti Lukats" <antti@openchip.org> wrote in message
news:dhqq2a$up3$00$1@news.t-online.com...

"Simon Peacock" <simon$actrix.co.nz> schrieb im Newsbeitrag
news:433f22f3$1@news2.actrix.gen.nz...
who the F*** designed your web site.... I know putting frames around
product
briefs lets you keep your logo.. but that's almost 2/3's of the screen
gone...

Simon

translated: fire your web designer


Thanks Simon!

no translation required, I agree with you 2000 %,
but I have no influence to solve the issue.

Antti
PS its not my website. Its from the company I work for at the moment.
(my contract ends 31.12.2005)

 

[Antti Lukats]

"wanch" <wpora@hotmail.com> schrieb im Newsbeitrag
news:1128180264.823258.225880@g47g2000cwa.googlegroups.com...

Could you suggest some devices which are suitable to run at a clock
rate more than 311MHz?

well my comment was only regarding the DCM max output on slowest S3 (-ES !)
I guess that fastest speed grade non -ES S3 parts go above 275MHz as DCM
output.

as of actual measurement I have measured in S3 -4 silicon internal signals
above 400MHz
somewhere above 450MHz the fabric stops toggling

but if you manage to feed in the 311 MHz clock then the S3 fabric should
still work
if the design is properly done

as of other parts that run at rate of more then 311MHz out of curiosity I
tested slowest
speed grade Lattice EC FPGA (LFEC3E-3)

PLL input 100MHz (from LVDS oscillator)
PLL output 325MHz, good signal measured on output pin
PLL output 400MHz, looks like working also but as my 500MHz DSO is sampling
only 1000GS/s (I dont know how to force the 2GS/s mode!) shows not so nice
sinus as there arent much samples. But I think the signals is really 400MHz.

so in any case the Lattice part (cheapest, slowest) is working as of the PLL
output above 311MHz at least.

Antti

 

[Simon Peacock]

That's where my snippet is different.. the "for generate " will repeat that
mux 64 times for you
nice and simple isn't it ???

The problem is you have to think of the resources.. I don't know exactly..
but the number of loads on any CLB are finite.. I doubt they are 64... so
the whole thing gets repeated multiple times as you are talking 8x240
outputs you will chew up resources horribly fast.

The Next problem is Xilinexs as with all FPGA's are a compromise... the 1 M
gate quote is based upon designs which are synchronous.. and yours isn't..
that makes a huge mux very inefficient and not what the tools are designed
to cope with.

The best bet would be to rethink.. possibly use the idea of shifting the
data into a dual port ram.. and using the second port of the ram as the
output of the mux... it does mean your design ends up pipelined.. but you
will be struggling to do it some other way.

The other solution is to put down 4 FPGA's

Simon

"vssumesh" <vssumesh_asic@yahoo.com> wrote in message
news:1128328159.468110.157190@f14g2000cwb.googlegroups.com...

Hello Simon,
Yes i am trying to implement the 64 nos of 8bit wide (240:1) mux.
And there is 240 * 64 = 15360 total selction bits (240 bits to each
mux). And 240 * 8 = 1920 data bits to whole block of 64 muxs (same data
goes to all MUX). Thus the mux array block will have 17280 input lines
and 64 * 8 output lines. Why you are saying that it is not possible.
All signals are internally generated from other parametrs (I dont know
the internal routing efforts of the FPGA). Please advice.
The mux (the code) you suggested is a single 240 to 1 byte mux. But i
want 64 copies of that. Is that possible. I know that it is not
possible to implement it in asingle design by getting the selction
signal from external sources; is it because of this constrain that the
ISE stops working. I am able to get output if i reduce any of the
parametrs to half (no: out put or no: registers etc).

 

[vssumesh]

Every thing is correct. But i cant simply change my design. What i am
thinking now is to proceed with the 120 register version.
If required i can switch over to Virtex "XC2V8000". Will that help
(with 8M gates).
But i am still wondering why Xilinx is not doing any synthesizing work.
And about your code is there any way to implement the same in verilog.
I dont know VHDL.

 

[Ed McGettigan]

Thomas Entner wrote:

The video out has asynchronous resonant spikes running
through it. The spikes are about 100 mV p-p, and have a
resonant frequency of about 250 MHz, with about 6 half-cycles
present.

There is also about 15 mV p-p of pixel clock and harmonics.



Hard to believe when Xilinx tells us that they are signal integrity
leader...

(Sorry, just could not resist ;-)

In case anyone is wondering, the comments being made about the VGA
quality on the ML401, ML402, and ML403 (they share the same PCB) are
correct. All of the initial tests that we did with the VGA output
didn't show any screen effects with the monitors that we were using.
After we released the boards, we received customer feedback on the
VGA quality and after looking over the issue discovered that the
analog portions of the PCB were not optimal.

We have improved the VGA quality on the upcoming ML405 and ML410 boards
that will be released early next year.

Ed

 

[Antti Lukats]

"Ed McGettigan" <ed.mcgettigan@xilinx.com> schrieb im Newsbeitrag
news:dhrn1m$d4n3@xco-news.xilinx.com...

Thomas Entner wrote:
The video out has asynchronous resonant spikes running
through it. The spikes are about 100 mV p-p, and have a
resonant frequency of about 250 MHz, with about 6 half-cycles
present.

There is also about 15 mV p-p of pixel clock and harmonics.

[]
We have improved the VGA quality on the upcoming ML405 and ML410 boards
that will be released early next year.

Ed

Hi Ed,

your comment about 405 "to be released early next year" (2006) sounds like
firm indication that Xilinx has serious problems with 4FX? The ML405 was
announced no later than jan 2005 (maybe earlier), now you are saying that it
is coming sometime in 2006 ? Why announce products that are 'maybe' coming
more than a year later? I would have expect ML405 to be available by now.
Well if there is really an issue with 4FX that would explain why no FX
boards are available from Xilinx online shop. Just wondering.

Antti